CN101770358B - System and method for processing jump instruction of microprocessor in branch prediction way - Google Patents
System and method for processing jump instruction of microprocessor in branch prediction way Download PDFInfo
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Abstract
The invention discloses a system and a method for processing a jump instruction of a microprocessor in a branch prediction way. The system comprises a coding module and a transmission module, wherein the coding module comprises a branch predictor used for predicting by adopting a static prediction method when the jump instruction to be processed is in the jump execution type or adopting a dynamic prediction method when the jump instruction to be processed is not in the jump execution type after the coding module judges that an instruction to be processed is the jump instruction and judges the type of the jump instruction through precoding, and directly writing the jump instruction to be processed and a delay slot instruction thereof in an operational queue in a sequence of the instructions in a program; and the transmission module comprises a prediction result processor used for canceling the instruction executed by error and continue fetching in a correct jump direction when the branch predictor predicts the jump instruction by error after the jump instruction is executed and written back to the transmission module. The system cancels operation by adopting different cancellation methods on the basis that whether the instruction is the jump execution instruction or not when the instruction is cancelled.
Description
Technical field
The present invention relates to the micro-processor architecture field, specially refer to a kind of jump instruction of microprocessor in branch prediction way disposal system and method.
Background technology
In existing microprocessor system, jump instruction brings many challenges to the design of microprocessor.For example for the microprocessor that flowing structure is arranged, when microprocessor when carrying out one section program that jump instruction arranged, if run into jump instruction, may determine so the earliest jump instruction whether the pipelining-stage of redirect and jump target addresses be the decoding stage, for example directly redirect (jump) instruction.
But for most of jump instruction, to wait until that generally the execute phase could determine redirect direction and the jump target addresses of jump instruction after finishing.And during this time follow-up instruction may be taken out from internal memory, What is more has begun to carry out, therefore when jump instruction is finally determined redirect, these acquired instructions or the instruction of having carried out all need to be cancelled, and microprocessor need to again obtain instruction from the correct destination address of jump instruction and also carry out.This will reduce microprocessor performance widely.
Therefore in existing microprocessor Design, mostly adopt diverse ways to process jump instruction, thereby improve processor performance.
Wherein, the method that prior art discloses a kind of general processing jump instruction is branch prediction method, the method is when running into jump instruction, microprocessor adopt specific mode predict the direction of jump instruction (such as, whether conditional branching is predicted its redirect), perhaps predict the destination address (for example for indirect jump instruction and program link order, predicting the destination address of its redirect) of jump instruction.Microprocessor is inferred executive routine according to the result of prediction, and these instructions are taken out then to send in the streamline from internal memory and carried out before the final solution of the result of jump instruction.If branch prediction is correct, the performance of processor will be improved so.This be because the result of jump instruction is final solve before, the instruction after these branch's jump instructions has begun to carry out (no matter be jump target addresses, or the subsequent instructions of jump instruction).If yet the branch prediction mistake, these infer that the instruction of carrying out will be cancelled.
But for the superscalar processor structure, such as the microprocessor of MIPS structure, cancel the design complexities that these instructions will increase processor.
Simultaneously, this branch prediction method of prior art is for the microprocessor of MIPS structure, because the MIPS instruction set stipulates that all jump instructions all must have delay slot instruction, therefore also needs processing delay slot order etc., thereby brings more complicated problem.
So-called delay slot instruction refers to immediately following that instruction after jump instruction.
In the microprocessor of MIPS structure, for most of jump instruction no matter finally whether redirect of jump instruction, the delay slot instruction of its correspondence all must be carried out, but for (branchlikely) instruction is carried out in redirect, delay slot instruction finally whether carry out be come according to the redirect direction that (branch likely) instruction is carried out in redirect fixed.Only have when (branch likely) instruction redirect is carried out in this redirect, the instruction that postpones groove just can be performed; Otherwise the instruction that postpones groove does not need to carry out.Therefore for the MIPS instruction set, for different jump instructions, delay slot instruction needs differentiating and processing.
Because cannot be as the delay slot instruction except jump instruction, the instruction of other any types all can be done delay slot instruction, therefore locate delay slot instruction and corresponding jump instruction determines whether cancelling delay slot instruction according to delay slot instruction, so that existing branch prediction method is more complicated, existing branch prediction method is not suitable for the microprocessor of superscalar processor structure, particularly the microprocessor of MIPS structure.
Summary of the invention
The object of the present invention is to provide a kind of jump instruction of microprocessor in branch prediction way disposal system and method, it is so that the branch prediction method of microprocessor is simpler, thus the performance of raising microprocessor.
A kind of jump instruction of microprocessor in branch prediction way disposal system for realizing that the object of the invention provides comprises decoding module and transmitter module.
Described decoding module comprises branch predictor, being used for judging pending instruction at described decoding module by pre-decode is jump instruction, and after the type of jump instruction, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct;
Described transmitter module comprises the processor that predicts the outcome, is used for after jump instruction executes and write back to described transmitter module, and at described branch predictor during to the prediction error of jump instruction, the wrong instruction of carrying out of cancellation and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation.
More preferably, whether this pending jump instruction of described basis is that type is carried out in redirect, and adopts static prediction or performance prediction method to predict, refers to:
According to the type of pending jump instruction, if instruction is carried out in redirect, then the prediction of static prediction method is adopted in this pending jump instruction, and predicted its redirect; Otherwise, if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict.
More preferably, whether described basis is that instruction is carried out in redirect, takes different canceling methods to cancel operation, refers to:
Carry out instruction if the jump instruction of branch prediction mistake is redirect, then execution is all cancelled in all instructions after this jump instruction; Do not carry out instruction if the jump instruction of branch prediction mistake is not redirect, then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
For realizing that the object of the invention more provides a kind of jump instruction of microprocessor in branch prediction way disposal route, comprise the following steps:
Steps A, jump instruction judge pending instruction by pre-decode, and after the type of jump instruction, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct;
Step B, after jump instruction executes and writes back to transmitter module, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation.
More preferably, in the described steps A, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprise the following steps:
Steps A 1 if instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
More preferably, among the described step B, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation, comprise the following steps:
Step B1 carries out instruction if the jump instruction of branch prediction mistake is redirect, and then execution is all cancelled in all instructions after this jump instruction;
Step B2 does not carry out instruction if the jump instruction of branch prediction mistake is not redirect, and then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
Beneficial effect of the present invention: jump instruction of microprocessor in branch prediction way disposal system of the present invention and method, it takes new Forecasting Methodology, so that carry out new processing at cancellation delay slot instruction after the jump instruction prediction error, so that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Description of drawings
Fig. 1 is jump instruction of microprocessor in branch prediction way disposal system structural representation of the present invention;
Fig. 2 is jump instruction of microprocessor in branch prediction way process flow figure of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, a kind of jump instruction of microprocessor in branch prediction way disposal system of the present invention and method are further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention rather than limitation of the present invention.
In embodiments of the present invention, take based on the microprocessor of MIPS structure of five-stage pipeline structure as example, jump instruction of microprocessor in branch prediction way disposal system of the present invention and method are described, but, it will be understood by those skilled in the art that jump instruction of microprocessor in branch prediction way disposal system of the present invention and method also go in the microprocessor of other superscalar processor structure.
As shown in Figure 1, in order to further specify the present invention, the embodiment of the invention at first illustrate based on the microprocessor of MIPS structure of five-stage pipeline structure, the same with the microprocessor of other most of superscalar processor structures, the embodiment of the invention based on the microprocessor of MIPS structure of pipeline organization, comprise following five part parts, be respectively:
Fetching module 1 is used for the fetching of streamline, and obtains instruction (instruction) according to the precedence that instruction occurs in program from internal memory or instruction buffer (cache);
Its precedence that occurs in program according to instruction is Instruction decoding (instruction after the decoding is called operation), and delivers in the operation queue, and the state of its operation is emission;
It selects not emission and the off-the-shelf operation issue of operand to corresponding functional unit from operation queue, and the status modifier of the operation that will launch is for launching;
Ordering calculation functional unit 4 is used for the computing of instruction;
Its each functional unit (comprising memory hierarchy and a plurality of arithmetic units etc.) is carried out the operation that launches from operation queue, and operation result is write back to corresponding of operation queue, and the mode bit of revising this operation has write back;
Register file module 5 is used for receiving the submission of instruction;
If the operation of its operation queue team head has been launched and operation result returns, submit so instruction to, operation result is write back register.
Jump instruction of microprocessor in branch prediction way disposal system of the present invention, in the decoding module 2 of described microprocessor, comprise branch predictor 21, being used for judging pending instruction at decoding module 2 by pre-decode is jump instruction, and after the type of jump instruction, whether be that (branch likely) type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct.
In the embodiment of the invention, the decoding module 2 of microprocessor enters into the decoding stage in pending instruction, judge by pre-decode, thereby determine whether this pending instruction is jump instruction, and after determining that it is jump instruction, judge the type of this pending jump instruction.
Whether decoding module 2 is jump instruction and the type of determining jump instruction in the decoding stage by the pre-decode decision instruction, it is a kind of prior art, those skilled in the art are according to the description of present embodiment, can realize pre-decode process of the present invention, therefore, describe in detail no longer one by one in embodiments of the present invention.
The branch predictor 21 of the embodiment of the invention according to the type of pending jump instruction, if (branch likely) instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect; Otherwise, if the jump instruction of (branch likely) is carried out in other non-redirects, then adopt the performance prediction method to predict; Then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct.
Performance prediction and static prediction are the key concept in the processor structure, basic on, performance prediction is to carry out direction history according to this jump instruction to predict this redirect direction; Static prediction then refers to whether redirect of only this instruction of simple forecast, and the execution direction of its prediction in the process that whole program is carried out all is the same.
The transmitter module 3 of the embodiment of the invention is used for all instructions, comprises that pending jump instruction and delay slot instruction thereof are transmitted directly in the corresponding ordering calculation functional unit 4 to carry out computing.
The transmitter module 3 of the embodiment of the invention, any delay slot instruction is not carried out special processing, be that any delay slot instruction all need not special processing, and be transmitted directly to the same with other instructions of the jump instruction that all are pending and delay slot instruction thereof carried out computing in the corresponding ordering calculation functional unit 4, reduces the complexity of microprocessor hardware.
The transmitter module 3 of the embodiment of the invention, also comprise the processor 31 that predicts the outcome, be used for after jump instruction executes and write back to transmitter module 3, when the prediction error of 21 pairs of jump instructions of branch predictor, cancel the wrong instruction of carrying out and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that (branch likely) instruction is carried out in redirect, take different canceling methods to cancel operation.
If mistake appears in the prediction of 21 pairs of jump instructions of branch predictor, then cancel mistake and carry out then instruction, then continue instruction fetch from correct execution direction.The processor 31 that predicts the outcome takes different canceling methods to cancel operation according to different jump instruction types.
Carry out (branch likely) instruction if the jump instruction of branch prediction mistake is redirect, then execution is all cancelled in all instructions after this jump instruction; Do not carry out (branch likely) instruction if the jump instruction of branch prediction mistake is not redirect, then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
For instruction is carried out in redirect, when only having the jump instruction redirect, its delay slot instruction just can be performed, if not redirect of jump instruction can not be performed so.Because just with static prediction and predict its redirect, when prediction was carried out, the delay groove that instructions are carried out in all redirects all was performed like this before in jump instruction.If therefore prediction is correct, this jump instruction redirect then is described, then delay slot instruction does not need to be cancelled execution; And if prediction error illustrates that then this jump instruction in fact can redirect, the delay groove that therefore is performed when prediction is carried out is carried out and need to be cancelled.
If the prediction of 21 pairs of jump instructions of branch predictor does not have mistake, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit, the result is write back to transmitter module 3, the result of execution with predict the outcome consistent, be branch predictor 21 prediction redirects, and execution result show redirect; Perhaps predicted branches fallout predictor 21 is predicted not redirect, and execution result is when showing not redirect, does not need transmitter module 3 to carry out other any processing after the mode bit of then revising this operation has write back, directly submits to.
The register file module 5 of the embodiment of the invention is used for directly instruction results being submitted to, and being need not to process after instruction is carried out.
The register file module 5 of the embodiment of the invention in presentation stage, because the processor 31 that predicts the outcome has been processed execution result, therefore only needs directly to submit instruction execution result to according to normal submission logic, need not to carry out other special processings.
So just so that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Correspondingly, the present invention also provides a kind of jump instruction of microprocessor in branch prediction way disposal route, and as shown in Figure 2, it comprises the steps:
Step S100 from the pending instruction of taking-up of the streamline of microprocessor, and obtains instruction according to the precedence that this instruction occurs from internal memory or instruction buffer (cache) in program.
Step S200, jump instruction judge pending instruction by pre-decode, and after the type of jump instruction, whether be that (branch likely) type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct.
In step S200, whether be that (branchlikely) type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprise the following steps:
Step S210 if (branch likely) instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
Step S220 if the jump instruction of (branch likely) is carried out in other non-redirects, then adopts the performance prediction method to predict.
Step S300, with all instructions, comprising that pending jump instruction and delay slot instruction thereof are transmitted directly in the corresponding ordering calculation functional unit 4 carries out computing.
Step S400, after jump instruction executes and writes back to transmitter module 3, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that (branch likely) instruction is carried out in redirect, take different canceling methods to cancel operation.
In step S400, according to whether being that (branch likely) instruction is carried out in redirect, take different canceling methods to cancel operation, comprise the following steps:
Step S410 carries out (branch likely) instruction if the jump instruction of branch prediction mistake is redirect, and then execution is all cancelled in all instructions after this jump instruction;
Step S420 does not carry out (branch likely) instruction if the jump instruction of branch prediction mistake is not redirect, and then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
Described step S400 also comprises the following steps:
If branch predictor does not have mistake to the prediction of jump instruction, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit 4, the result is write back, the result of execution with predict the outcome unanimously, namely predict redirect, and execution result shows redirect; Perhaps predict not redirect, and execution result is when showing not redirect, do not need decoding module 2 to carry out other any processing after the mode bit of then revising this operation has write back, directly submit to.
Step S500 after instruction is carried out, directly is submitted to instruction results the register file module.
The below describes in further detail explanation jump instruction of microprocessor in branch prediction way disposal system of the present invention and method with two examples.
Example 1. is established in this example, and operation queue has 8, namely can have simultaneously 8 instructions to carry out in streamline simultaneously.If operation queue has had three instructions, and queue head pointer points to the second instruction.At first decoding module instruction that the fetching module is got is deciphered; In order to accelerate branch prediction, in decoding, pre-decode is done in these instructions, then the result according to pre-decode does branch prediction.After pre-decode, find that article one instruction is that (branch likely) instruction is carried out in redirect, then predict its redirect, and the redirect that will decipher bus is carried out and is identified (blikely sign) and be set to 1; The second instruction is the delay slot instruction of this instruction.And then these two instructions are fed to operation queue.Wherein the 4th of article one instruction write operation formation the, and the blikely of operation queue sign is set to 1; Emission state sign (issued sign) is set to 0; Result phase sign (WB sign) is set to 0, and the 5th of second instruction write operation formation, its blikely identifies and is set to 0; The issued sign is set to 0; The WB sign is set to 0.Next is clapped, and the fetching module will continue fetching from the jump target addresses of this jump instruction.
At launching phase, transmitter module finds not emission and the off-the-shelf instruction of operand that it is transmitted into corresponding ordering calculation functional unit from operation queue.If second and the 3rd of operation queue launched, and the 4th and the 5th 's operand is ready to, is transmitted into simultaneously corresponding functional unit with the 4th and the 5th so; If only the 4th operand is ready to, so only be transmitted into corresponding functional unit with the 4th; If only the 5th operand is ready to, so only be transmitted into corresponding functional unit with the 5th.In out of order transmitter logic, the shooting sequence of these two instructions is without any contact.
Writing back the stage, if the 4th result writes back, and the execution result of instruction is not redirect, be 1 with the 4th WB position so, and judge whether its blikely sign is 1, if 1, and all instructions of (comprising the 5th) after the 5th are all cancelled execution.Cancel the operation of these instructions, if these operations are just carried out at functional unit, cancellation is carried out; Then the operation queue item that these instructions are shared discharges.Last fetching module will continue instruction fetch from correct path.If writing back the stage, the execution result of instruction was redirect when the 4th result write back, and was left intact so, and only the WB position with four instructions is 1.
Presentation stage is submitted instruction to according to the normal logic of submitting to, need not special processing.
Example 2. is established in this example, and operation queue has 8, namely can have simultaneously 8 instructions to carry out in streamline simultaneously.If operation queue has had three instructions, and queue head pointer points to the second instruction.At first decoding module instruction that the fetching module is got is deciphered; In order to accelerate branch prediction, in decoding, pre-decode is done in these instructions, then the result according to pre-decode does branch prediction.After pre-decode, find that article one instruction is common jump instruction, predict its whether redirect according to branch predictor.And the blikely sign that will decipher bus is set to 0; The second instruction is the delay slot instruction of this instruction.And then these two instructions are fed to operation queue.Wherein the 4th of article one instruction write operation formation the, and the blikely of operation queue sign is set to 0; The issued sign is set to 0; WB sign is set to 0, and the 5th of second instruction write operation formation, its blikely sign is set to 0; The issued sign is set to 0; The WB sign is set to 0.Next is clapped, and the fetching module will continue fetching from the predicted path of this jump instruction.
At launching phase, transmitter module finds not emission and the off-the-shelf instruction of operand that it is transmitted into corresponding ordering calculation functional unit from operation queue.If second and the 3rd of operation queue launched, and the 4th and the 5th 's operand is ready to, is transmitted into simultaneously corresponding functional unit with the 4th and the 5th so; If only the 4th operand is ready to, so only be transmitted into corresponding functional unit with the 4th; If only the 5th operand is ready to, so only be transmitted into corresponding functional unit with the 5th.In out of order transmitter logic, the shooting sequence of these two instructions is without any contact.
Writing back the stage, if the 4th result writes back, and the result of the execution result of instruction and prediction is inconsistent, but predicts that namely the redirect execution result shows not redirect; Perhaps predicting not redirect but execution result shows redirect, is 1 with the 4th WB position so; And judge whether its blikely sign is 1, if be not 1, so execution is all cancelled in all instructions of (not comprising the 5th) after the 5th.Comprise these operations just in the functional unit execution if cancel the operation of these instructions, cancellation is carried out; Then the operation queue item that these instructions are shared discharges.Last fetching module will continue instruction fetch from correct path.If writing back the stage, when the 4th result writes back the execution result of instruction with predict the outcome consistent, but predict that namely the redirect execution result shows redirect; Perhaps predict not redirect but execution result shows not redirect, be left intact so that only the WB position with four instructions is 1.
Presentation stage is submitted instruction to according to the normal logic of submitting to, need not special processing.
Jump instruction of microprocessor in branch prediction way disposal system of the present invention and method, adopt branch predictor to predict, and carry out rear result by the processor that predicts the outcome according to jump instruction and process, so that carry out new processing at cancellation delay slot instruction after the jump instruction prediction error, so that the branch prediction method of microprocessor is simpler, when reducing the microprocessor hardware complexity, can improve the performance of microprocessor.
Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (7)
1. a jump instruction of microprocessor in branch prediction way disposal system comprises decoding module and transmitter module, it is characterized in that:
Described decoding module comprises branch predictor, being used for judging pending instruction at described decoding module by pre-decode is jump instruction, and after the type of jump instruction, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct;
Described transmitter module comprises the processor that predicts the outcome, is used for after jump instruction executes and write back to described transmitter module, and at described branch predictor during to the prediction error of jump instruction, the wrong instruction of carrying out of cancellation and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation;
Whether this pending jump instruction of described basis is that type is carried out in redirect, and adopts static prediction or performance prediction method to predict, refers to:
According to the type of pending jump instruction, if instruction is carried out in redirect, then the prediction of static prediction method is adopted in this pending jump instruction, and predicted its redirect; Otherwise, if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict;
Whether described basis is that instruction is carried out in redirect, takes different canceling methods to cancel operation, refers to:
Carry out instruction if the jump instruction of branch prediction mistake is redirect, then execution is all cancelled in all instructions after this jump instruction; Do not carry out instruction if the jump instruction of branch prediction mistake is not redirect, then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
2. branch prediction disposal system according to claim 1 is characterized in that, also comprises ordering calculation functional unit and register file module;
The jump instruction that transmitter module is pending with all and delay slot instruction thereof are transmitted directly in the corresponding ordering calculation functional unit and carry out computing;
Described register file module is used for directly instruction results being submitted to after instruction is carried out.
3. a jump instruction of microprocessor in branch prediction way disposal route is characterized in that, comprises the following steps:
Steps A, jump instruction judge pending instruction by pre-decode, and after the type of jump instruction, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, then will this pending jump instruction and delay slot instruction according to the order of instruction in the program operation queue item that writes direct;
Step B, after jump instruction executes and writes back to transmitter module, to the prediction error of jump instruction the time, the wrong instruction of carrying out of cancellation and continue fetching from correct redirect direction; When the cancellation instruction, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation;
In the described steps A, whether be that type is carried out in redirect according to this pending jump instruction, and adopt static prediction or performance prediction method to predict, comprise the following steps:
Steps A 1 if instruction is carried out in redirect, then adopts the prediction of static prediction method to this pending jump instruction, and predicts its redirect;
Steps A 2 is if the jump instruction that other non-redirects are carried out then adopts the performance prediction method to predict;
Among the described step B, according to whether being that instruction is carried out in redirect, take different canceling methods to cancel operation, comprise the following steps:
Step B1 carries out instruction if the jump instruction of branch prediction mistake is redirect, and then execution is all cancelled in all instructions after this jump instruction;
Step B2 does not carry out instruction if the jump instruction of branch prediction mistake is not redirect, and then execution is all cancelled in all instructions behind the delay slot instruction of this jump instruction.
4. branch prediction disposal route according to claim 3 is characterized in that, among the described step B, also comprises the following steps:
If branch predictor does not have mistake to the prediction of jump instruction, jump instruction is transmitted into carries out computing in the ordering calculation corresponding functional unit, the result is write back, the result of execution with predict the outcome unanimously, namely predict redirect, and execution result shows redirect; Perhaps predict not redirect, and execution result is when showing not redirect, do not need decoding module to carry out other any processing after the mode bit of then revising this operation has write back, directly submit to.
5. according to claim 3 or 4 described branch prediction disposal routes, it is characterized in that, also comprise the following steps: before the described steps A
From the pending instruction of taking-up of the streamline of microprocessor, and from internal memory or instruction buffer, obtain instruction according to the precedence that this instruction occurs in program.
6. branch prediction disposal route according to claim 5 is characterized in that, also comprises the following steps: between described steps A and the step B
The jump instruction that all are pending and delay slot instruction thereof are transmitted directly in the corresponding ordering calculation functional unit and carry out computing.
7. branch prediction disposal route according to claim 6 is characterized in that, also comprises the following steps: after the described step B
After instruction is carried out, directly instruction results is submitted to the register file module.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247122B1 (en) * | 1998-12-02 | 2001-06-12 | Ip-First, L.L.C. | Method and apparatus for performing branch prediction combining static and dynamic branch predictors |
| CN1359488A (en) * | 1999-05-03 | 2002-07-17 | 英特尔公司 | Optimized execution of statically strongly predicted branch instructions |
| CN1560735A (en) * | 2004-03-09 | 2005-01-05 | 中国人民解放军国防科学技术大学 | Recovery method of return address stack in double stack return address predicator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247122B1 (en) * | 1998-12-02 | 2001-06-12 | Ip-First, L.L.C. | Method and apparatus for performing branch prediction combining static and dynamic branch predictors |
| CN1359488A (en) * | 1999-05-03 | 2002-07-17 | 英特尔公司 | Optimized execution of statically strongly predicted branch instructions |
| CN1560735A (en) * | 2004-03-09 | 2005-01-05 | 中国人民解放军国防科学技术大学 | Recovery method of return address stack in double stack return address predicator |
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