CN101800245A - 在屏蔽的栅极场效应晶体管中形成多晶硅层间电介质的结构和方法 - Google Patents

在屏蔽的栅极场效应晶体管中形成多晶硅层间电介质的结构和方法 Download PDF

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CN101800245A
CN101800245A CN201010118650A CN201010118650A CN101800245A CN 101800245 A CN101800245 A CN 101800245A CN 201010118650 A CN201010118650 A CN 201010118650A CN 201010118650 A CN201010118650 A CN 201010118650A CN 101800245 A CN101800245 A CN 101800245A
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罗伯特·赫里克
迪安·E·普罗布斯特
弗雷德·塞西诺
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

如下所述形成一种屏蔽的栅极沟槽FET。在第一导电类型的硅区域(204)中形成沟槽(202)，该沟槽(202)包括通过屏蔽电介质(206)与硅区域(204)绝缘的屏蔽电极(208)。沿屏蔽电极(208)的上表面形成包括热氧化物层(210)和共形电介质层(212)的多晶硅层间电介质(IPD)(214)。至少顺着上部沟槽(202)侧壁形成栅极电介质(216)。在沟槽中形成栅电极(218)，使得栅电极通过IPD与屏蔽电极绝缘。

Description

在屏蔽的栅极场效应晶体管中形成多晶硅层间电介质的结构和方法
本申请是分案申请，其原案申请的申请号为200680028769.8，申请日为2006年8月4日，发明名称为“在屏蔽的栅极场效应晶体管中形成多晶硅层间电介质的结构和方法”。
背景技术
本发明总体上涉及半导体功率场效应晶体管(FET)，并且更具体地涉及在屏蔽的栅极FET中形成改进的多晶硅层间电介质(IPD)的结构和方法。
由于屏蔽电极降低栅-漏电容(Cgd)，并且提高晶体管的击穿电压，因此，屏蔽的栅极沟槽FET具有优势。图1是传统的屏蔽的栅极沟槽MOSFET的简化横截面图。沟槽110包括位于栅电极122正下方的屏蔽电极114。屏蔽电极114通过通常比栅极电介质120厚的屏蔽电介质112与相邻的硅区域绝缘。栅电极和屏蔽电极通过一般被称为多晶硅层间电介质或IPD的电介质层116彼此绝缘。该IPD层必须具有足够的品质和厚度以承受(support)栅电极与屏蔽电极之间所需的电压。
图1的传统的屏蔽的栅极FET具有许多缺陷。首先，栅电极122具有尖底角，其和屏蔽电极114的平坦顶面一起在这些区域中产生强电场。其次，用于形成IPD的传统方法典型地在沟槽之间的台面(mesa)上引入氧化层，但是在形成栅电极之后的某时刻其又必须被去除。在去除该氧化物期间，不可避免地会发生将某些栅极氧化物蚀刻到沟槽侧壁上，其可能导致栅极短路和栅极泄漏。其它已知技术使IPD的形成依赖于栅极电介质的形成，因此IPD厚度被限于栅极电介质厚度的一组倍数。这不允许栅极电介质和IPD的单独优化。获得的IPD与栅极电介质之间的最大厚度差已经是大约3比1(即，对于给定的目标栅极电介质厚度，已经获得的最大IPD厚度大约为已经获得的目标栅极电介质厚度的三倍)。
因此，存在对形成具有改进的IPD和栅极电介质的屏蔽的栅极沟槽FET的结构和方法的需求。
发明内容
根据本发明的实施例，形成FET的方法如下。在第一导电类型的硅区域中形成沟槽。沟槽包括通过屏蔽电介质与硅区域绝缘的屏蔽电极。沿屏蔽电极的上表面形成包括热氧化物层和共形电介质(conformal dielectric)层的多晶硅层间电介质(IPD)。至少顺着上部沟槽侧壁形成栅极电介质。在沟槽中形成栅电极。栅电极通过IPD与屏蔽电极绝缘。
在一实施例中，IPD具有凹的上表面。
在另一实施例中，IPD的厚度与栅极电介质的厚度比大于3比1。
在又一实施例中，在形成IPD之后形成栅极电介质。
在另一实施例中，如下形成IPD。沿沟槽侧壁的上部以及沿屏蔽电极的上表面形成热氧化物层。用共形电介质层填充沟槽。部分地去除共形电介质层和热氧化物层，从而形成包括热电介质层剩余部分以及共形电介质层剩余部分的IPD。
根据本发明的另一实施例，FET包括延伸至第一导电类型的硅区域中的沟槽。通过屏蔽电介质与硅区域绝缘的屏蔽电极在沟槽的下部中延伸。栅电极位于沟槽中，在屏蔽电极之上，但通过多晶硅层间电介质(IPD)与屏蔽电极绝缘。IPD包括共形电介质层和热氧化物层。
在一实施例中，栅电极通过沿上部沟槽侧壁延伸的栅极电介质与硅区域绝缘，并且IPD的厚度与栅极电介质的厚度比大于3比1。
在另一实施例中，IPD沿其上表面具有凹的轮廓。
在又一实施例中，栅极沿其下表面具有凹的轮廓。
在另一实施例中，共形电介质层被热电介质沿电介质共形层的下表面和侧壁所围绕。
在另一实施例中，共形电介质层具有凸的下表面和凹的上表面。
在另一实施例中，屏蔽电极具有圆形顶面。
在另一实施例中，硅区域包括在第一导电类型的衬底之上延伸的第一导电类型的外延层、外延层中的第二导电类型的阱区、以及阱区中的第一导电类型的源区。源区位于沟槽的侧面。
在一实施例中，沟槽延伸至并终止于外延层内。
在另一实施例中，沟槽延伸穿过外延层并终止于衬底内。
下面的详细描述以及附图提供了对本发明的本质和优点的更好的理解。
附图说明
图1是传统的屏蔽的栅极沟槽MOSFET的简化横截面图；以及
图2A至图2L是根据本发明的实施例，在形成具有改进的多晶硅层间电介质和栅极电介质的屏蔽的栅极沟槽FET的示例性工艺顺序的各个阶段的简化横截面图。
具体实施方式
根据本发明，通过执行热氧化接下来进行共形电介质层的沉积来形成屏蔽的栅极FET的IPD层。然后形成栅极电介质，接下来形成栅电极。该方法将形成IPD层的工艺与形成栅极电介质的工艺分离开，从而使这些电介质层中的每一个都能够被独立地优化。因此，在不损害栅极电介质品质或厚度的情况下，可以形成高品质、厚的IPD以承受栅电极与屏蔽电极之间所需的电压。再者，共形电介质层有助于沿IPD的顶面获得平滑的凹的轮廓(即，像碗的内部)，从而其为栅电极产生平滑的底部轮廓。这与图1中的栅电极具有尖下角的传统FET结构相比，有助于减小电场。
图2A至图2L是根据本发明的实施例，在形成具有改进的IPD和栅极电介质的屏蔽的栅极沟槽FET的示例性工艺顺序的各个阶段的简化横截面图。在图2A中，利用传统的掩模和硅蚀刻技术在硅区域204中形成沟槽202。在一实施例中，硅区域204包括在高导电n型衬底之上延伸的相对轻掺杂的n型外延层。在此实施例中，取决于设计目的，沟槽可以被蚀刻以终止于外延层内或更深地延伸以终止于衬底内。在图2B中，利用已知技术，顺着沟槽侧壁和底部以及临近沟槽的台面区域的表面形成屏蔽电介质层206(例如，包含氧化物)。在一实施例中，使用高温(例如，1150℃)干氧化来形成屏蔽氧化物。高温有助于使沟槽底角变圆，并形成足以承受器件击穿的大约
Figure GSA00000026661200051
的屏蔽氧化物。
在图2C中，利用传统的多晶硅沉积技术来沉积多晶硅层以填充沟槽。然后，所沉积的多晶硅被凹进到沟槽中从而形成屏蔽电极208。然后，屏蔽电介质层的暴露部分被变薄至，例如
Figure GSA00000026661200052
在屏蔽电极包括氧化物的实施例中，使用湿缓冲(wet buffered)氧化物蚀刻来将屏蔽氧化物变薄。屏蔽电介质的剩余暴露部分206a有助于防止在随后的热氧化步骤中沿沟槽侧壁和台面表面的氧化物的过度生长，并有助于控制沟槽腔的轮廓。热氧化物的过度生长可导致在随后沉积的共形电介质中空腔的形成。在一实施例中，完全去除屏蔽电介质206的暴露部分，或者可选地原封不动地保留整个屏蔽电介质206。
在图2D中，执行热氧化步骤以沿着沟槽侧壁、在临近沟槽的台面区的表面之上、以及屏蔽电极208之上形成热氧化层210。热氧化有利地氧化屏蔽电极208的上部，从而产生圆形顶部轮廓。该圆形顶部有助于最小化屏蔽电极208与稍后形成的栅电极之间的区域中的电场。在一实施例中，通过执行低温、湿氧化，之后是高温、干氧化，来形成热氧化物层210。在另一实施例中，热氧化产生具有
Figure GSA00000026661200053
至
Figure GSA00000026661200054
范围内的厚度的热氧化物层210。在又一实施例中，进行低温热氧化(例如，大约850℃)以便沿屏蔽电极的顶面形成比沿沟槽侧壁和台面表面之上更厚的热氧化物层。在这样的实施例中，1.5∶1至2∶1范围内的厚度比将是理想的。在一具体实施例中，热氧化沿屏蔽电极的顶面产生具有厚度约为的热氧化物层以及沿沟槽侧壁和台面表面产生具有厚度约为
Figure GSA00000026661200056
的热氧化物层。
在图2E中，沉积共形电介质层212(例如，包含氧化物)以填充沟槽。在一实施例中，利用次大气压化学气相沉积(SACVD)正硅酸乙脂(TEOS)/臭氧工艺在温度约为510℃和压强约为480托的环境下沉积共形电介质层212。所沉积的氧化物完全填充沟槽而不留空隙。
在图2F中，共形电介质层212和热氧化物层210被向下蚀刻至沟槽中直至期望的深度。台面表面之上和沿沟槽侧壁的上部的全部电介质被完全去除，并且具有凹的顶面的多晶硅层间电介质(IPD)层214保留在屏蔽电极208之上。因此，IPD层214包括热电介质层和共形电介质层的叠层。在一实施例中，在将电介质叠层凹进沟槽期间，进行电介质叠层的均匀回蚀(etch back)。可以执行干式各向异性等离子体蚀刻或湿蚀刻以获得所期望的IPD厚度，并且确保沿沟槽侧壁和台面之上的氧化物被完全去除。也可以进行传统的致密(densification)步骤以密化SACVD氧化物。在一实施例中，进行干蚀刻和随后的致密，接下来为湿蚀刻。
在图2G中，利用传统技术来形成沿沟槽侧壁、在IPD层之上、并且在临近沟槽的台面区域之上延伸的栅极电介质层216(例如，来自氧化物)。由于IPD的形成被完全与栅极电介质的形成分离，因此，可以单独优化栅极电介质以具有所期望的特性。在图2H中，利用传统技术，多晶硅层被沉积以填充沟槽，接下来被回蚀以在沟槽202中形成凹进的栅电极218。
在图2I中，在台面之上延伸的栅极电介质216的部分被回蚀至适合于体(body)注入和源注入的厚度。执行传统的毯式体注入(blanket body implant)和推进(drive in)工艺以沿硅区域204的上部形成p型体区220。然后利用传统的源注入以及掩模层(未示出)在沟槽202侧面形成源区222。在图2J中，利用传统技术在该结构之上形成金属前(pre-metal)电介质层224(例如，包括BPSG)。在图2K中，利用掩模层(未示出)，部分去除电介质层224以暴露由掩模层所限定的体区220和源区222的表面。然后进行传统的硅蚀刻(例如，干蚀刻)使暴露的表面区域凹进。从而，所凹进的硅区域形成接触窗口(contact opening)226。
在图2L中，进行毯式重体注入以在体区220中形成自对准p型重体区228。接下来进行电介质224的回流以获得接触窗口的更佳纵横比(aspect ratio)和在随后步骤中被形成以电接触重体区228和源区222的金属层226的更佳阶梯覆盖(step coverage)。水平延伸的虚线被包含在图2L中以示出其中外延层203在衬底201之上延伸、并且沟槽202延伸穿过外延层203并终止于衬底201中的实施例。可选地，沟槽202可以被终止于外延层203内。同样，通过图2A至2L中的横截面图所描述的工艺顺序仅仅是示例性的，并且各个步骤可以被修改或按照与所示顺序不同的顺序来进行。尤其是，为获得具有所期望特征和特性的屏蔽的栅极结构，可以执行多个已知工艺步骤中的任意一个而不是由图2I至2L所描述的步骤。
根据本发明的结构和方法，获得了包括热生长的电介质和共形沉积的电介质的膜叠层的改进的IPD层。热生长的电介质提供了高品质电介质，并用于使屏蔽电极的顶角变圆。共形沉积的电介质(1)填充屏蔽电极上面的间隙，(2)在蚀刻沿沟槽侧壁的电介质时，用作硬掩模以保护屏蔽电极之上的热电介质，以及(3)产生平滑的凹的轮廓，在该凹的轮廓上形成栅电极。沿屏蔽电极的顶面和栅电极的底部的圆形轮廓在这些局部区域中产生较小的电场。
此外，根据本发明形成IPD的方法用于将IPD的形成与栅极氧化物的形成相分离，使得IPD和栅极电介质能够被独立地优化以，例如，获得厚的、高品质IPD和薄的、高品质栅极电介质。在一实施例中，通过利用大于约5比1的IPD厚度与栅极电介质厚度之比来得到最佳晶体管特性。例如，发现大于约的IPD厚度和小于约
Figure GSA00000026661200072
的栅极电介质厚度能够提供最佳晶体管特性。形成薄栅极电介质的能力能够被有利地用于获得更低的导通电阻。
为达到甚至更低的导通电阻、更强的阻断能力和更高的效率，以及其他优点和特征，本发明的多种结构和方法可以与大量电荷扩展技术中的一种或更多种以及于2004年12月29日提交的第11/026,276号普通转让申请中所公开的并且其全部内容结合于此作为参考的其它屏蔽栅极结构和制造工艺相结合。
尽管上面示出并描述了多个具体实施例，但是本发明的实施例并不限于此。例如，应当理解在不背离本发明的情况下，可以反转示出的和描述的结构的掺杂极性和/或可以改变各个成分的掺杂浓度。由图2A至2L所描述的工艺顺序是用于形成n沟道FET的，然而鉴于该公开，对于本领域技术人员来说修改该工艺顺序以形成p沟道FET将是显而易见的。同样，尽管上述各个实施例是在传统硅中实现的，但也可以在碳化硅、砷化镓、氮化镓、金刚石或其它半导体材料中实现这些实施例和它们的明显变体。此外，不同实施例的横截面图可能是未按比例的，并且同样也不意味着在相应结构的布图设计中限制可能的变化。同样，可以以带状或包括六边形或方形晶体管单元的蜂窝结构形成所示的FET及其明显的变体。而且，在不背离本发明的范围的情况下，可以将本发明的一个或更多个实施例的特征与本发明的其它实施例的一个或更多个特征相结合。因此，本发明的范围不应被限于所描述的实施例，而是由所附的权利要求所限定。

Claims (11)

1.一种场效应晶体管，包括：
沟槽，延伸至第一导电类型的硅区域中；
屏蔽电极，位于所述沟槽下部中，所述屏蔽电极通过屏蔽电介质与所述硅区域绝缘；以及
栅电极，位于所述沟槽中，在所述屏蔽电极之上，但通过沿其上表面的至少中间部分具有凹的轮廓的层间电介质与所述屏蔽电极绝缘。
2.根据权利要求1所述的场效应晶体管，其中，所述屏蔽电极具有圆形顶面。
3.根据权利要求1所述的场效应晶体管，其中，所述硅区域包括：
所述第一导电类型的外延层，在所述第一导电类型的衬底之上延伸；
第二导电类型的阱区，位于所述外延层中；以及
所述第一导电类型的源区，位于所述阱区中，所述源区位于所述沟槽侧面。
4.根据权利要求3所述的场效应晶体管，其中，所述沟槽延伸至并且终止于所述外延层中。
5.根据权利要求3所述的场效应晶体管，其中，所述沟槽延伸穿过所述外延层并且终止于所述衬底中。
6.一种场效应晶体管，包括：
沟槽，延伸至第一导电类型的硅区域中；
屏蔽电极，位于所述沟槽下部中，所述屏蔽电极通过屏蔽电介质与所述硅区域绝缘；以及
栅电极，位于所述沟槽中，在所述屏蔽电极之上，但通过层间电介质与所述屏蔽电极绝缘，所述层间电介质包括共形电介质层，所述共形电介质层具有沿其下表面的凸的轮廓和沿其上表面的至少中间部分的凹的轮廓。
7.根据权利要求6所述的场效应晶体管，其中，所述栅电极沿其下表面具有凹的轮廓。
8.根据权利要求6所述的场效应晶体管，其中，所述层间电介质进一步包括沿所述共形电介质层下表面和侧壁环绕所述共形电介质层的热电介质。
9.根据权利要求6所述的场效应晶体管，其中，所述硅区域包括：
所述第一导电类型的外延层，在所述第一导电类型的衬底之上延伸；
第二导电类型的阱区，位于所述外延层中；以及
所述第一导电类型的源区，位于所述阱区中，所述源区位于所述沟槽侧面。
10.根据权利要求9所述的场效应晶体管，其中，所述沟槽延伸至并且终止于所述外延层中。
11.根据权利要求9所述的场效应晶体管，其中，所述沟槽延伸穿过所述外延层并且终止于所述衬底中。
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CN103367144A (zh) * 2012-03-26 2013-10-23 马克斯半导体股份有限公司 沟槽式井区电场屏蔽功率mosfet结构及制作方法
CN105789043A (zh) * 2014-12-25 2016-07-20 中航（重庆）微电子有限公司 沟槽型半导体器件及其制作方法
CN111613674A (zh) * 2019-02-25 2020-09-01 恒泰柯半导体（上海）有限公司 深沟道mosfet

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WO2007021701A3 (en) 2007-09-13
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TW200715416A (en) 2007-04-16
WO2007021701A2 (en) 2007-02-22
KR101221242B1 (ko) 2013-01-11
JP5075823B2 (ja) 2012-11-21
KR20080035686A (ko) 2008-04-23
US7385248B2 (en) 2008-06-10
CN101238581B (zh) 2010-04-14
TWI417963B (zh) 2013-12-01
MY141412A (en) 2010-04-30
AT504736A2 (de) 2008-07-15
US20070037327A1 (en) 2007-02-15
DE112006002077T5 (de) 2008-07-03
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US7598144B2 (en) 2009-10-06
DE112006002077B4 (de) 2020-01-02
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