CN101916720B - Method for improving threshold voltage variation curve of high-pressure device below 60 nanometers - Google Patents
Method for improving threshold voltage variation curve of high-pressure device below 60 nanometers Download PDFInfo
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Abstract
The invention discloses a method for improving a threshold voltage variation curve of a high-pressure device below 60 nanometers along width direction of the device. The method is characterized by comprising the following steps: sequentially forming a gate dielectric layer and a gate electrode on a semiconductor substrate, wherein a gap is formed on the gate electrode and divides the gate electrode into two parts, the gate dielectric layer is divided into a first part of gate dielectric layer and a second part of gate dielectric layer by the gap and the parts of the gate electrode, one part of the gate dielectric layer, which is covered by the gate electrode, is the first part of gate dielectric layer, the other part of the gate dielectric layer, which is uncovered by the gate electrode, is the second part of gate dielectric layer, and the width of the gap is gradually reduced from both sides to the middle in the channel width direction of the high-pressure device. The method of the invention adjusts the variation range of a threshold voltage varying with the high-pressure device by editing the construction of the gate electrode so that the small-size high-pressure device can be also designed by a designer to provide the threshold voltage according with specifications.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the particularly following embedded high-voltage device of a kind of improvement 60 nanoscales, along with the high tension apparatus width changes the method for threshold voltage variation curve, the high-voltage device structure after the improvement also proposes in the lump.
Background technology
Field effect transistor device (MOSFET hereinafter is called " device ") is one of basic components and parts in the integrated circuit, and its basic physical principle is known by the industry technology personnel.Listed the computing formula of the threshold voltage (Vth) of device in the following formula (1).
In the formula (1), Vth is threshold voltage, ψ
FBBe flat band voltage,
Be Fermi potential, N
ABe channel doping concentration (this formula is the computing formula of NMOSFET) that ε is dielectric constant, C
OXBe unit-area capacitance.According to above computing formula, the main and ψ of the size of threshold voltage
FB,
N
A, C
OXFour factor analysis, in the situation that the structural parameters (such as channel doping concentration, gate material, gate oxide thickness etc.) of MOSFET pipe are fixed, its threshold voltage vt h is can be well-determined.
In the circuit design of reality, need the high tension apparatus of different threshold voltages to satisfy different circuit design demands, the threshold voltage vt h of high tension apparatus calculates and follows equally formula (1).Its operating voltage is generally higher, operating voltage is generally more than or equal to 12 volts, sometimes can reach tens volts, the thickness of gate oxide is relative also thicker, it is as the power device extensive use, for example, can be applied in the driving chip of LCD (Liquid Crystal Display, liquid crystal display).
Figure 1 shows that the structural representation of the high tension apparatus of prior art.As shown in Figure 1, this high tension apparatus 100 comprises gate electrode 150, gate dielectric layer 140, source electrode (Source) 120, drain electrode (Drain) 130, deviate region (Drift Drain) 170 and Semiconductor substrate 110.The certain distance in difference interval forms deviate region 170 between source electrode (Source) 120, drain electrode (Drain) 130 and the gate electrode 150, with applicable its high working voltage characteristic.Take substrate as the P type as example, add forward voltage on the gate electrode 140, can the inversion charge layer appear the channel region under gate dielectric layer 140, between source electrode and drain electrode, form raceway groove.Figure 2 shows that the structural representation of the another high tension apparatus of prior art, compare with high tension apparatus shown in Figure 1, mainly be to have increased respectively a STI layer (Shallow Trench Insulator in the deviate region 160 between gate dielectric layer 140 and source electrode 120, drain electrode 130, shallow groove isolation layer) 260, STI layer 260 is used for preventing the break-through between the source electrode and drain electrode under the high-pressure situations; This structure is more applicable for the relatively high high tension apparatus of operating voltage (for example operating voltage is higher than 32 volts).
Continue to see also Fig. 1 and Fig. 2, in the prior art, high tension apparatus is obvious thinner than mid portion at the gate oxide thickness of the edge part of STI (ShallowTrench Isolation), this will cause high tension apparatus threshold voltage reducing along with channel width, sharply descend (shown in Fig. 5 dotted line, this curve is because along with the reduce rapid decline of high tension apparatus along device widths direction size, in the industry cycle be also referred to as " Roll-off curve "), this curvilinear trend causes those skilled in the art to bring certain difficulty and inconvenience when the design high tension apparatus, when high tension apparatus when lateral dimension has variation, threshold voltage vt h can sharply diminish, can bring difficulty to processing procedure, cause device not reach specification requirement.
Summary of the invention
The present invention is intended to by adjusting the following high tension apparatus of 60 nanometers, along with the high tension apparatus width changes the threshold voltage variation curve, to solve a series of difficult problems in the design of small size high tension apparatus.
In view of this, the invention provides the method for the following high tension apparatus threshold voltage variation of a kind of improvement 60 nanometers curve, it is characterized in that, may further comprise the steps:
Form gate dielectric layer in Semiconductor substrate;
Form gate electrode at gate dielectric layer,
Wherein gate electrode has the gap, the gap is divided into two parts with gate electrode, these parts of gap and gate electrode are divided into first's gate dielectric layer and second portion gate dielectric layer with gate dielectric layer, wherein first's gate dielectric layer is the part that gate dielectric layer is covered by gate electrode, the second portion gate dielectric layer is the part that gate dielectric layer is not covered by gate electrode
Wherein on the channel width dimension of high tension apparatus, the width to the centre successively decreases from both sides in the gap.
Further, if wherein the size of high tension apparatus is fixed, when the ratio increase of second portion gate dielectric layer and first's gate dielectric layer, the threshold voltage of high tension apparatus increases.
The present invention also provides a kind of high tension apparatus, comprising: Semiconductor substrate has gate dielectric layer and the gate electrode that is formed on the gate dielectric layer on it; Wherein, gate electrode has the gap, the gap is divided into first and second portion with gate electrode, these parts of gap and gate electrode are divided into first's gate dielectric layer and second portion gate dielectric layer with gate dielectric layer, wherein first's gate dielectric layer is the part that gate dielectric layer is covered by gate electrode, the second portion gate dielectric layer is the part that gate dielectric layer is not covered by gate electrode, and the width in the middle of two side direction of its intermediate gap on the channel width dimension of high tension apparatus successively decreases.
Further, described high tension apparatus is by 60 nanometer nodes or the following technology manufacturing of 60 nanometer nodes.
Further, the ratio when described second portion gate dielectric layer and first's gate dielectric layer increases the threshold voltage increase of described high tension apparatus.
Further, the thickness of described gate dielectric layer is more than or equal to 400A.
Further, the spacing between described a plurality of gap can be 2～3 times of gate electrode thickness.
Further, also comprise source electrode and drain electrode, described source electrode and drain electrode be distributed in described gate dielectric layer both sides and with the alternate certain distance in edge of described gate dielectric layer.
Further, described gate electrode is polygate electrodes or metal gate electrode.
The following high tension apparatus threshold voltage of a kind of improvement 60 nanometers provided by the invention is along the method for the change curve of channel width, by the modification to the gate electrode composition, gate electrode is revised not by the Area Ratio of the gate electrode gate dielectric layer that covers and the gate dielectric layer that is covered by gate electrode, can cause unit-area capacitance Cox to change, thereby cause its threshold voltage variation, compensated thus because the phenomenon that the threshold voltage that STI edge gate oxide structure thin is brought diminishes, therefore, the method has been adjusted high tension apparatus, the following high tension apparatus of 60 nanometer nodes particularly, threshold voltage is along with the amplitude of variation that device size (no matter being channel length or width) changes can reduce greatly, even so that the designer of high tension apparatus in the design of undersized high tension apparatus, also can allow this high tension apparatus that threshold voltage up to specification is provided.
Description of drawings
Fig. 1 is the structural representation of the high tension apparatus of prior art;
Fig. 2 is the structural representation of the another high tension apparatus of prior art;
Figure 3 shows that the vertical view of the high-voltage device structure that the method according to this invention is made;
Figure 4 shows that the sectional view of the high-voltage device structure that the method according to this invention is made;
Figure 5 shows that high tension apparatus threshold voltage after prior art and this enforcement improve is along with the change curve contrast figure of gate electrode width.
Figure 6 shows that the structural representation of adjusting the high tension apparatus threshold voltage by adjusting maximum spacing and minimum spacing.
Embodiment
For technical characterictic of the present invention is become apparent, below in conjunction with accompanying drawing, provide specific embodiment, the present invention will be further described.
Below will provide the actual solution to the problems described above of the present invention.
Figure 3 shows that the vertical view of the high-voltage device structure that the method according to this invention is made, Figure 4 shows that the sectional view of the high-voltage device structure that the method according to this invention is made, this sectional view is the sectional view that A-A ' locates among Fig. 3.
High tension apparatus device 300 comprises: Semiconductor substrate 310 has gate dielectric layer 340 and the gate electrode 350 that is formed on the gate dielectric layer 340 on it; Wherein, described gate electrode 350 has a gap, and described gate electrode is divided into two parts 350a, 350b.
As shown in Figure 3, Figure 4, high tension apparatus 300 comprises two part 350a, 350b of gate electrode, gate dielectric layer 340, source electrode (Source) 320, drain electrode (Drain) 330, deviate region 370 and Semiconductor substrate 310.Take the high tension apparatus of N-type as example, Semiconductor substrate 310 is P type doped semiconductor, and the concrete doping content of Semiconductor substrate 310 is not limited by the present invention, can require to select different doping contents according to difference.
The width W of gate electrode 350 as shown in Figure 4, width W is subject to the restriction of high tension apparatus overall dimensions, along with the impact of the change of high tension apparatus overall dimensions.
It should be noted that, width in the middle of two side direction of its intermediate gap on the channel width dimension of high tension apparatus successively decreases, namely, place, both sides on channel width dimension, spacing between gate electrode two part 350a, 350b is maximum spacing m ', place in the middle of on channel width dimension, the spacing between gate electrode two part 350a, 350b is minimum spacing m, m is less than m '.
Therefore, two part 350a, 350b of gate electrode are divided into the part that is covered by gate electrode and the part that is not covered by gate electrode with gate dielectric layer 340, the part that 350a, 350b cover is defined as first's gate dielectric layer, and the unlapped part of 350a, 350b is defined as the second portion gate dielectric layer.
When gate electrode 350 applies forward gate bias greater than threshold voltage, can the local substrate zone transoid under gate dielectric layer 340 form N-type carrier accumulation district, thereby the source electrode 320 of gate dielectric layer 340 both sides and drain apply the source drain bias between 330 after, can form conducting channel (among the figure shown in the dotted arrow).Gate electrode can be polygate electrodes, also can be metal gate electrode, and the material of gate electrode and film thickness thereof are not limited by the present invention.
Gap shown in Fig. 3,4 only is one, in other embodiments, also can optionally at gate electrode a plurality of gaps be set, thereby these gaps and gate electrode can be divided into gate dielectric layer a plurality of firsts gate dielectric layer and second portion gate dielectric layer.
See also Fig. 5, it is depicted as high tension apparatus threshold voltage after prior art and this enforcement improve along with the change curve contrast figure of gate electrode width.
Dotted portion is that high tension apparatus in the prior art is in the immovable situation of its dependent variable, along with gate electrode 150 width changes, the change curve of the threshold voltage of high tension apparatus among Fig. 5.Can find out that from curve shown in Figure 5 when the width of gate electrode reduced, threshold voltage vt just can significantly reduce.When this effect is further diminished to 60 nanometers by 65 nanometers when the volume of high tension apparatus, owing to the width of gate electrode 150 also can correspondingly reduce to seem particularly evident so that the threshold voltage of small size high tension apparatus difficulty design according to actual needs.
Continue to consult Fig. 3 and Fig. 4, can find out that according to principle introduction and the formula (1) about high tension apparatus in the background technology material impact factor of high tension apparatus threshold voltage vt h is exactly unit-area capacitance C
OXIf change unit-area capacitance C wherein
OX, the threshold voltage vt of whole high tension apparatus then can access change.
High tension apparatus unit-area capacitance C
OXVariation, also can go from the effective thickness of gate dielectric layer 340 to understand, as shown in Figure 4, if gate electrode all standing gate dielectric layer 340, the effective thickness that its P is ordered is d, but, if not during covering grid electrode, its effective thickness becomes d1 directly over the P point, d1 is greater than d, according to the electric capacity computing formula as can be known, unit-area capacitance C
OXValue descends, and threshold voltage vt h increases.Among this embodiment, just provided the physical principle that the threshold voltage of the high-voltage device structure of N-type adjusts and explained, the physical principle that the threshold voltage of the high-voltage device structure of P type is adjusted is explained can the rest may be inferred.
With reference to figure 3,4, because the existence in the gap of gate electrode 350 in the present embodiment, unit area capacitance density reduces, thereby has reduced C
OX, compare the high tension apparatus of gate electrode all standing gate dielectric layer, its unit-area capacitance C
OXDescend, thereby threshold voltage vt h rises, and realizes easily the characteristic of high threshold voltage.And the minimum clearance distance m between 350a, the 350b is larger, and second portion gate dielectric layer and first's gate dielectric layer Area Ratio are larger, unit-area capacitance C
OXLess, h is larger for its threshold voltage vt.
Say further, when the size of high tension apparatus is fixed, the designer can also be by adjusting the ratio of second portion gate dielectric layer and first's gate dielectric layer Area Ratio or adjustment m ' and m, adjust the threshold voltage of high tension apparatus along with the change curve of gate electrode width, for example shown in the solid line among Fig. 5, by adjusting second portion gate dielectric layer and first's gate dielectric layer Area Ratio, can so that the threshold voltage of high tension apparatus along with gate electrode width reduce that numerical value descends more slow, thus, can solve high tension apparatus along with self reducing of size and according to the problem that descends of threshold voltage.
The solid line of Fig. 5 has partly represented the disclosed method through the present invention, the method made high tension apparatus out, variation along with device widths, the change curve of the high tension apparatus of the change curve of its threshold voltage in the prior art comes gently, namely, when the threshold voltage of high tension apparatus reduced, threshold voltage descended comparatively slowly along the change curve of channel width.
More preferably, this high tension apparatus is suitable for 60 nanometer nodes and the following technology manufacturing of 60 nanometer nodes, for example, when 32nm foundry technology is made this high tension apparatus, when threshold voltage was 32V, the thickness d of gate dielectric layer 340 was more than or equal to 400A, and the minimum spacing m between a plurality of gaps can be 2～3 times of thickness d, comparable with the thickness d of gate dielectric layer 340 between the gap, be easy to revise to adjust its threshold voltage by the gate electrode composition.
Figure 6 shows that in another embodiment of the present invention, adjust the structural representation of high tension apparatus threshold voltage by adjusting maximum spacing and minimum spacing.
High tension apparatus device and the high tension apparatus device architecture among Fig. 3 among Fig. 6 are almost identical, and unique difference is maximum spacing m " large than the m ' among Fig. 3, the threshold voltage of the high tension apparatus device that therefore high tension apparatus device shown in Figure 6 can be more shown in Figure 3 is large.
In sum, the method of the following high tension apparatus threshold voltage variation of a kind of improvement 60 nanometers provided by the invention curve, by the modification to the gate electrode composition, gate electrode is revised not by the Area Ratio of the gate electrode gate dielectric layer that covers and the gate dielectric layer that is covered by gate electrode, can cause unit-area capacitance Cox to change, thereby cause its threshold voltage variation, therefore, the method has been adjusted high tension apparatus, the following high tension apparatus of 60 nanometer nodes particularly, threshold voltage changes the amplitude of variation of (no matter being channel length or width) along with device size, even so that the designer of high tension apparatus in the design of undersized high tension apparatus, also can allow this high tension apparatus that threshold voltage up to specification is provided.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. one kind is improved the following high tension apparatus threshold voltage of 60 nanometers along the method for device widths change curve, it is characterized in that, may further comprise the steps:
Form gate dielectric layer in Semiconductor substrate;
Form gate electrode at described gate dielectric layer,
Wherein said gate electrode has the gap, described gate electrode is separated in described gap, described gap and gate electrode are divided into first's gate dielectric layer and second portion gate dielectric layer with described gate dielectric layer, wherein first's gate dielectric layer is the part that described gate dielectric layer is covered by described gate electrode, the second portion gate dielectric layer is the part that described gate dielectric layer is not covered by gate electrode
Wherein on the channel width dimension of described high tension apparatus, the width to the centre successively decreases from both sides in described gap.
2. the method for the following high tension apparatus threshold voltage variation of improvement 60 nanometers according to claim 1 curve, it is characterized in that, if wherein the size of high tension apparatus is fixed, when the Area Ratio increase of described second portion gate dielectric layer and first's gate dielectric layer, the threshold voltage of described high tension apparatus increases.
3. a high tension apparatus is characterized in that, comprising:
Semiconductor substrate has gate dielectric layer and the gate electrode that is formed on the gate dielectric layer on it;
Wherein said gate electrode has the gap, described gate electrode is separated in described gap, described gap and gate electrode are divided into first's gate dielectric layer and second portion gate dielectric layer with described gate dielectric layer, wherein first's gate dielectric layer is the part that described gate dielectric layer is covered by described gate electrode, the second portion gate dielectric layer is the part that described gate dielectric layer is not covered by gate electrode
Wherein on the channel width dimension of described high tension apparatus, the width to the centre successively decreases from both sides in described gap.
4. high tension apparatus according to claim 3 is characterized in that, described high tension apparatus is by 60 nanometer nodes or the following technology manufacturing of 60 nanometer nodes.
5. high tension apparatus according to claim 3 is characterized in that, if wherein the size of high tension apparatus is fixed, when the Area Ratio increase of described second portion gate dielectric layer and first's gate dielectric layer, the threshold voltage of described high tension apparatus increases.
6. high tension apparatus according to claim 3 is characterized in that, the thickness of described gate dielectric layer is more than or equal to 400 dusts.
7. high tension apparatus according to claim 6 is characterized in that, the minimum spacing between the described gap is 2～3 times of thickness of described gate dielectric layer.
8. high tension apparatus according to claim 3 is characterized in that, also comprises source electrode and drain electrode, described source electrode and drain electrode be distributed in described gate dielectric layer both sides and with the alternate certain distance in edge of described gate dielectric layer.
9. high tension apparatus according to claim 3 is characterized in that, described gate electrode is polygate electrodes or metal gate electrode.
10. high tension apparatus according to claim 3 is characterized in that, the number in described gap is a plurality of, and described gap and gate electrode are divided into a plurality of firsts gate dielectric layer and second portion gate dielectric layer with described gate dielectric layer.
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| US10461078B2 (en) * | 2018-02-26 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Creating devices with multiple threshold voltage by cut-metal-gate process |
| CN116489988A (en) * | 2022-01-12 | 2023-07-25 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714412A (en) * | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN1467845A (en) * | 2002-07-11 | 2004-01-14 | 中国科学院物理研究所 | Single electron memory workable under room temperature and method for making the same |
| CN101635311A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | Multi-threshold field MOSFET and multi-threshold field MOSFET unit |
| CN101635310A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | High voltage multi-threshold MOSFET device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7504676B2 (en) * | 2006-05-31 | 2009-03-17 | Alpha & Omega Semiconductor, Ltd. | Planar split-gate high-performance MOSFET structure and manufacturing method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714412A (en) * | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
| US6090652A (en) * | 1996-12-28 | 2000-07-18 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
| CN1467845A (en) * | 2002-07-11 | 2004-01-14 | 中国科学院物理研究所 | Single electron memory workable under room temperature and method for making the same |
| CN101635311A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | Multi-threshold field MOSFET and multi-threshold field MOSFET unit |
| CN101635310A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | High voltage multi-threshold MOSFET device |
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