CN101937858A - Wafer level making method with flip-chip bump structure - Google Patents
Wafer level making method with flip-chip bump structure Download PDFInfo
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- CN101937858A CN101937858A CN201010243645XA CN201010243645A CN101937858A CN 101937858 A CN101937858 A CN 101937858A CN 201010243645X A CN201010243645X A CN 201010243645XA CN 201010243645 A CN201010243645 A CN 201010243645A CN 101937858 A CN101937858 A CN 101937858A
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- Prior art keywords
- bump
- conducting material
- electric conducting
- salient point
- mould
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a wafer level making method with a flip-chip bump structure, comprising the following steps of: making a nailhead bump on a metal bonding pad of a wafer; aligning the nailhead bump with an opening of a mould; filling a conductive material in the opening of the mould; demoulding; heating and refluxing or curing to form a second bump. The second bump and the nailhead bump form a bump structure. For carrying out production by simultaneously adopting a printing method based on the wafer and also saving the making procedure of a UBM (Under Bump Metal) layer, the method enhances the production efficiency, also lowers the production cost and has remarkable economic benefit.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to a kind of wafer level manufacture method that is used for the flipchip-bumped structure.
Background technology
Exist multiple being used for to provide the different technologies that is electrically connected between semiconductor chip and the substrate at present, in numerous technology, present trend is to use solder bump to be electrically connected to fetch with formation to replace the lead-in wire bonding, adopt the mode of upside-down mounting to encapsulate then.Flip chip technology (fct) refers to is exactly that the active face of chip is downward, realizes Interworking Technology by salient point and substrate.In order to guarantee the reliability of whole encapsulation, corresponding metal layer under the salient point (Under Bump Metallization) technology, just the UBM technology of having produced.Solder bump adopts modes such as evaporation, plating, printing to finish usually.
It is to adopt stud bump to replace the UBM layer that a kind of Flip-Chip Using technology (US005508561A) is arranged at present, and then carries out scolder and fill and make second salient point on stud bump, and bare chip (die) carries out but this technology is based on.Though this method has been simplified technology with respect to common electroforming, reduced cost, but production efficiency is still very low, mainly be because be to process realization one by one, and the scolder fill process of second salient point is to adopt the mode of solder sheet punching press or filling solder ball is finished at single nude film.
Summary of the invention
In order to overcome the deficiency of said method, the object of the present invention is to provide a kind of novel high efficiency wafer level salient point manufacture method, mainly be to utilize stud bump, and adopt the mode of printing to fill electric conducting material, form second salient point at disk as UBM.
To achieve these goals, the present invention adopts following technological means, comprising:
On the metal pad of disk, produce one or more stud bump as first salient point, it is characterized in that, the perforate of stud bump and mould is aligned, then electric conducting material is filled in the perforate of described mould, carry out the demoulding then.
The present invention further improves and is, uses scraper that described electric conducting material is scraped in the perforate of described mould.
The present invention further improves and is that described electric conducting material is a soldering paste.
After the present invention further improves and is the demoulding, place it in and be heated in the reflow ovens on the soldering paste melting temperature, through refluxing, described soldering paste covers described stud bump and forms second salient point.
The present invention further improves and is that described soldering paste is lead-free solder paste or lead welding cream is arranged.
The present invention further improves and is that described electric conducting material is a conductive silver paste.
After the present invention further improved and is the demoulding, described conductive silver paste was through solidifying to form second salient point.
The present invention further improves and is that described stud bump can be Cu, Au, Pd and alloy thereof.
Adopt the advantage of such production method to be: one, be based on the manufacturing that disk carries out second salient point owing to this, and adopt the mode of printing to finish, and then carry out scribing, improved production efficiency; Its two, the manufacturing of adopting this production method to save the UBM layer with respect to salient point forming methods such as traditional evaporation, plating, printing has realized the simplification of technology, has reduced production cost.
Description of drawings
Below in conjunction with accompanying drawing the present invention is elaborated:
Fig. 1 a-f is the flow chart of making according to the soldering paste bump structure of the embodiment of the invention one;
Fig. 2 a-d is the flow chart of making according to the silver slurry bump structure of the embodiment of the invention two.
Description of drawings:
The 1-disk; The 2-A1 pad; The 3-stud bump; 4-first mould;
The 5-soldering paste; 51-scolder second salient point; 6-second mould;
7-silver slurry; 71-silver slurry second salient point.
Embodiment
Embodiment one:
Fig. 1 a-f is the flow chart of making according to the soldering paste bump structure of the embodiment of the invention one, and this method may further comprise the steps:
Step S101 produces stud bump 3, shown in Fig. 1 b on the A1 of disk 1 pad 2;
Step S102 aligns the perforate of the stud bump 3 and first mould 4, shown in Fig. 1 c, soldering paste 5 is scraped in the perforate of first mould 4, shown in Fig. 1 d with scraper then;
Step S103 carries out the demoulding, shown in Fig. 1 e;
Step S104, after the demoulding, place it in and be heated to lead-free solder in the reflow ovens to melting temperature, through refluxing, described lead-free solder covers stud bump and forms scolder second salient point 51, stud bump 3 is as first salient point and complete bump structure of scolder second salient point, 51 common formations, shown in Fig. 1 f.
Embodiment two:
Fig. 2 a-d is the flow chart of making according to the silver slurry bump structure of the embodiment of the invention two, and this method may further comprise the steps:
Step S201, identical with step S101 among the embodiment one, promptly on the A1 of disk 1 pad 2, produce stud bump 3, shown in Fig. 1 b;
Step S202 aligns the perforate of the stud bump 3 and second mould 6, shown in Fig. 2 a, conductive silver paste 7 is scraped in the perforate of second mould 6, shown in Fig. 2 b with scraper then;
Step S203 carries out the demoulding, shown in Fig. 2 c;
Step S204 after the demoulding, starches second salient point 71 through solidifying to form silver, and stud bump 4 is as complete bump structure of first salient point and silver slurry second salient point, 71 common formations, shown in Fig. 2 d.
Claims (8)
1. the wafer level manufacture method of a flipchip-bumped structure, on the metal pad (2) of disk (1), produce one or more stud bump (3) as first salient point, it is characterized in that, the perforate of stud bump (3) with mould aligned, then electric conducting material is filled in the perforate of described mould, carries out the demoulding then.
2. the method for claim 1 is characterized in that, uses scraper that described electric conducting material is scraped in the perforate of described mould.
3. the method for claim 1 is characterized in that, described electric conducting material is a soldering paste.
4. the method for claim 1 is characterized in that, when described electric conducting material is soldering paste, after the demoulding, described disk is placed on is heated in the reflow ovens on the described soldering paste melting temperature, through refluxing, described soldering paste covers described stud bump (3) and forms second salient point.
5. as claim 5 or 6 described methods, it is characterized in that described soldering paste is lead-free solder paste or lead welding cream is arranged.
6. the method for claim 1 is characterized in that, described electric conducting material is a conductive silver paste.
7. the method for claim 1 is characterized in that, when described electric conducting material was conductive silver paste, after the demoulding, described conductive silver paste was through solidifying to form second salient point.
8. the method for claim 1 is characterized in that, the material of described stud bump is Cu, Au, Pd and alloy thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010243645XA CN101937858A (en) | 2010-08-03 | 2010-08-03 | Wafer level making method with flip-chip bump structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010243645XA CN101937858A (en) | 2010-08-03 | 2010-08-03 | Wafer level making method with flip-chip bump structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101937858A true CN101937858A (en) | 2011-01-05 |
Family
ID=43391101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010243645XA Pending CN101937858A (en) | 2010-08-03 | 2010-08-03 | Wafer level making method with flip-chip bump structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN101937858A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709197A (en) * | 2012-06-21 | 2012-10-03 | 清华大学 | Technical method for packaging salient point of welded ball based on substrate etching mode |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
| CN1159077A (en) * | 1994-08-08 | 1997-09-10 | 惠普公司 | Method of bulging substrate by holding soldering paste stacking |
| JPH10242148A (en) * | 1997-02-26 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Method for forming solder bumps |
| JP2002313985A (en) * | 2002-04-05 | 2002-10-25 | Oki Electric Ind Co Ltd | Method of manufacturing chip size package |
| US20020190392A1 (en) * | 2001-06-14 | 2002-12-19 | Yoshihide Iwazaki | Semiconductor device and manufacturing method thereof |
| US20030032277A1 (en) * | 2001-08-08 | 2003-02-13 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit board and electronic instrument |
| US20060189116A1 (en) * | 2003-03-10 | 2006-08-24 | Rajeev Joshi | Dual metal stud bumping for flip chip applications |
-
2010
- 2010-08-03 CN CN201010243645XA patent/CN101937858A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
| CN1159077A (en) * | 1994-08-08 | 1997-09-10 | 惠普公司 | Method of bulging substrate by holding soldering paste stacking |
| JPH10242148A (en) * | 1997-02-26 | 1998-09-11 | Matsushita Electric Ind Co Ltd | Method for forming solder bumps |
| US20020190392A1 (en) * | 2001-06-14 | 2002-12-19 | Yoshihide Iwazaki | Semiconductor device and manufacturing method thereof |
| US20030032277A1 (en) * | 2001-08-08 | 2003-02-13 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit board and electronic instrument |
| JP2002313985A (en) * | 2002-04-05 | 2002-10-25 | Oki Electric Ind Co Ltd | Method of manufacturing chip size package |
| US20060189116A1 (en) * | 2003-03-10 | 2006-08-24 | Rajeev Joshi | Dual metal stud bumping for flip chip applications |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709197A (en) * | 2012-06-21 | 2012-10-03 | 清华大学 | Technical method for packaging salient point of welded ball based on substrate etching mode |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110105 |