CN101968611A - Phase distribution-based single point mask silicon wafer leveling method - Google Patents

Abstract

The invention discloses a phase distribution-based single point mask silicon wafer leveling method, which is characterized by comprising the following steps of: transmitting plane waves to a first group of marked grating and a second group of marked grating which are positioned on a mask, diffracting for several times, reflecting by a silicon wafer, transmitting the marked gratings again, and forming a constant interference field on the mask surface; when the silicon wafer is inclined in a cross section direction and a longitudinal section direction, changing the phase distribution causing the interference field, namely the distribution direction of equal phase lines and spacial frequency; and directly adjusting the silicon wafer according to the phase distribution condition, and timely correcting the inclination of the silicon wafer relative to the mask to directly realize local leveling of the single point mask silicon wafer. The method is intuitive, simple and easy to operate, has high practicability and has significance for developing of micro-nano processing technology.

Description

A kind of single-point mask silicon chip leveling method based on PHASE DISTRIBUTION

Technical field

The present invention relates to the leveling of a kind of nano-photoetching mask silicon chip, particularly a kind of single-point mask silicon chip leveling method based on PHASE DISTRIBUTION belongs to micro-nano processing correlative technology field.

Background technology

Along with the research and development of highly integrated circuit and related device, the IC characteristic dimension is more and more little, has obtained significant progress with the high resolution micro-nano process technology that is lithographically representative.With its feature such as simple to operate, with low cost, become one of mainstream technology of future generation, near the contact type nanometer manufacturing process as nano impression, array of zone plates imaging and photo-etching and X-ray lithography.Along with the raising of photolithography resolution, the leveling of mask silicon chip, clearance control and measurement become influences one of device feature size accuracy factors.

Traditional mask silicon chip leveling generally is to realize by the clearance measurement of 3 or multiple spot, promptly carry out clearance measurement control at 3 by what do not go out in collinear or multiple spot position, principle or other leveling algorithms according to 3 definite planes, when reach unanimity in three places or gap, many places, both are parallel fully for the mask silicon chip.And clearance measurement generally adopts imaging, interference strength and difference interference several method how much.In measuring process, this several method all is subjected to the influence of silicon chip surface technological processs such as photoresist easily, introduce the asymmetry error that is subjected to silicon chip technology pollution back introducing of additional optical distance, mark etc. as the repeatedly reflection in the photoresist, it is inconsistent that these comparatively tangible systematic errors cause what time locating gap measurement, finally has influence on the precision of mask silicon chip leveling.In order directly to avoid and eliminate in the classic method the inconsistent site error that causes in the multimetering, the present invention is based on spot measurement, directly measure and eliminate silicon chip with respect to the inclination of mask on horizontal stroke, two vertical direction in longitudinal section, to reach the purpose of leveling in single position.

Summary of the invention

The technical issues that need to address of the present invention are: overcome the deficiencies in the prior art, a kind of single-point mask silicon chip leveling method based on PHASE DISTRIBUTION is provided, it can directly realize the local leveling of mask and silicon chip a position, be not vulnerable to the influence of silicon chip technology, the leveling precision is higher, and operation is simple.

Technical solution of the present invention is: a kind of single-point mask silicon chip leveling method based on PHASE DISTRIBUTION, its characteristics are that the direct incident of plane wave (1) is positioned at the two groups of adjacent marker gratings (3,5) on the mask (2), mark grating (3)+1 order diffraction light returns through silicon chip (4) surface reflection, see through once more mask (2) surface and mark grating (5)+1 order diffraction light forms two groups of interference fringes; When mask (2) and silicon chip (4) when being in parastate, the PHASE DISTRIBUTION unanimity of two groups of interference fringes; When exist between mask (2) and the silicon chip (4), the PHASE DISTRIBUTION of two groups of interference fringes is inconsistent, there are differences, and described difference is embodied in the difference on the frequency of two groups of interference fringes and the relative tilt angle of two groups of interference fringes; According to the difference on the frequency of two groups of interference fringes, calculate mask (2) and silicon chip (4) tilt quantity by formula (1), to eliminate the inclination of mask (2) and silicon chip (4), the leveling of realization cross-sectional direction in cross-sectional direction in cross-sectional direction; According to the relative tilt angle of two groups of interference fringes, calculate mask (2) and silicon chip (4) tilt quantity by formula (2), to eliminate the inclination of mask (2) and silicon chip (4), the leveling of realization longitudinal section direction in the longitudinal section direction in cross-sectional direction;

$\mathrm{\δf}=\frac{2(\cos {\mathrm{\θ}}_1+\cos {\mathrm{\θ}}_2)}{\mathrm{\λ}}\·\mathrm{\δ\θ}---\left(1\right)$

Wherein: δ f represents the difference on the frequency of two groups of interference fringes, θ _fThe relative tilt angle of representing two groups of interference fringes; δ θ represents the tilt quantity of silicon chip (4) in cross-sectional direction, and λ is the incident plane wave wavelength, θ ₁, θ ₂Be respectively two groups of adjacent marker gratings (3,5)+1 order diffraction angle;

Expression silicon chip (4) is in the tilt quantity of longitudinal section direction.

Principle of the present invention: the direct incident of plane wave is positioned at two groups of adjacent marker gratings on the mask, the inferior mark grating group that after the silicon chip reflection, sees through once more of the order of diffraction, form two groups of constant interference fields at the mask face, its phase characteristic directly reflects the inclined degree of mask silicon chip.Thereby according to the PHASE DISTRIBUTION characteristics of interference field, directly eliminate the inclination of mask silicon chip on two vertical direction, realize the leveling of mask silicon chip.Wherein, according to the difference on the frequency of two groups of stripeds, calculate and eliminate the inclination of cross-sectional direction; According to the relative tilt angle of two groups of stripeds, calculate and eliminate the inclination of longitudinal section direction.

The present invention's beneficial effect compared with prior art is:

(1) the present invention can directly realize the local leveling of mask and silicon chip a position, the efficient height, and be not vulnerable to the influence of silicon chip technology, the leveling precision is higher.

(2) the present invention is independent of clearance measurement, directly carries out mask and silicon chip leveling according to spatial phase feature, can avoid influencing the influence of the silicon chip technological factors such as photoresist of light intensity to leveling.

(3) the present invention not only can avoid the influence of silicon chip technology such as photoresist to spot measurement, can also eliminate the error of the inconsistent introducing of multimetering, and process technology is significant to receiving near declining.

Description of drawings

Fig. 1 is the inventive method principle schematic;

Fig. 2 is that the silicon chip on horizontal stroke of the present invention, two vertical direction in longitudinal section tilts and beam deflection; (a) the cross-sectional direction silicon chip tilts to cause the beam deflection synoptic diagram; (b) be the synoptic diagram that longitudinal section direction silicon chip tilts to cause beam deflection,

Fig. 3 is two group echo grating schematic layout patterns on the mask of the present invention;

Fig. 4 is the PHASE DISTRIBUTION situation of several groups of interference field intensity fringes in the leveling process of the present invention, wherein: (a) PHASE DISTRIBUTION that is respectively for inclination horizontal, that indulge two cross-wise direction; (b) be the PHASE DISTRIBUTION of cross-sectional direction after being eliminated; (c) be that the longitudinal section direction is by the PHASE DISTRIBUTION after eliminating separately; (d) be the PHASE DISTRIBUTION of the inclination of both direction after all being eliminated.

Embodiment

As shown in Figure 1, plane wave 1 direct incident is positioned at the two groups of adjacent marker gratings 3 and 5 on the mask 2, + 1 order diffraction light returns through silicon chip 4 surface reflections, see through the mark grating 5 on the mask face once more, two groups of grating pairs answer+and 1 order diffraction light forms two groups of corresponding interference fringes at mask surface, received by ccd detector 8 through catoptron 6, object lens 7 backs.When mask 2 and silicon chip 4 are in parastate, the PHASE DISTRIBUTION unanimity of two groups of stripeds, frequency equates that direction is identical; When exist between mask 2 and the silicon chip 4, the PHASE DISTRIBUTION of two groups of stripeds changes, no longer consistent, and it is directly related with both difference to tilt.

As shown in Figure 2, when mask 2 and silicon chip 4 horizontal, longitudinal section both direction exist respectively certain tilt quantity δ θ and

The time, through silicon chip reflection+1 diffraction light will on corresponding direction, be deflected corresponding angle 2 δ θ and

The deflection of light beam directly influence two bundles from the reflection of silicon chip and mask+1 diffraction light B _wAnd B _mInterference.Wherein, the light beam B that is reflected _wDeflection on cross-sectional direction directly influences the size of interfering angle, thereby influences the spatial frequency of interference fringe; Light beam B is reflected _wDeflection on the longitudinal section directly makes the interference plane of two-beam be rotated, thereby makes the space distribution direction of striped that corresponding rotation take place.In brief, the inclination δ θ of cross-sectional direction has directly changed the spatial frequency of two groups of stripeds, the inclination of longitudinal section direction

Then directly changed the angle of inclination of two groups of stripeds, specifically by formula (1), (2) decision.

$\mathrm{\δf}=\frac{2(\cos {\mathrm{\θ}}_1+\cos {\mathrm{\θ}}_2)}{\mathrm{\λ}}\·\mathrm{\δ\θ}---\left(1\right)$

Wherein: δ f represents the difference on the frequency of two groups of interference fringes, θ _fThe relative tilt angle of representing two groups of interference fringes; δ θ represents the tilt quantity of silicon chip 4 in cross-sectional direction, and λ is the incident plane wave wavelength,

Expression silicon chip 4 is in the tilt quantity of longitudinal section direction; θ ₁, θ ₂The cycle of being respectively is respectively P ₁, P ₂Adjacent marker grating 3,5+1 order diffraction angle, by the decision of following formula.By following optical grating diffraction equation decision

P ₁sinθ ₁＝λ (3)

P ₂sinθ ₂＝λ (4)

Wherein, the cycle of two adjacent gratings is P ₁=2.0 μ m, P ₂=2.2 μ m, wavelength X=633nm.

Two group echo gratings adopt layout as shown in Figure 3 on the mask 2, about two group echo gratings 3,5 be respectively P by the cycle respectively ₁With P ₂, P ₂With P ₁Two gratings constitute P in the embodiment of the invention wherein up and down ₁=2.0 μ m, P ₂=2.2 μ m.Reflection through silicon chip 4 surfaces, two groups of gratings+meet on 5 on the 1 order diffraction light mark grating on the right and produce two groups of interference fringes.In addition, Fig. 4 is two groups of interference fringes according to mark emulation shown in Figure 3, and the PHASE DISTRIBUTION situation of striped in the mask silicon chip leveling process.When silicon chip is configured to δ θ=1.5 * 10 with respect to mask respectively in inclination horizontal, the longitudinal section direction ^-3Rad and δ φ=1 * 10 ^-3During rad, its PHASE DISTRIBUTION such as Fig. 4 (a), two groups of corresponding inclinations of striped up and down at this moment, and also spatial frequency is inconsistent, and two groups of stripeds are easy to by difference; After the inclination of cross-sectional direction is eliminated separately, the density degree of striped (being spatial frequency) much at one, arrange relative tilt, shown in Fig. 4 (b), mean the existence that the longitudinal section direction tilts, and the relative tilt angle of striped (i.e. the angle of two groups of stripeds) is directly related with the tilt quantity of longitudinal section direction, is determined by formula (2); On the other hand, after the inclination of longitudinal section direction was eliminated separately, striped is consistent to be arranged, all along the x direction, as Fig. 4 (c), but the inconsistent existence that means that cross-sectional direction tilts of frequency, and frequency difference is directly related with the tilt quantity of cross-sectional direction, is determined by formula (1); When inclination horizontal, the longitudinal section direction all is eliminated, two groups of striped frequencies are equal fully, and orientation is in full accord, and as Fig. 4 (d), at this moment, the local leveling of mask silicon chip is finished, and reaches perfect condition.

In addition, show according to numerical result shown in Figure 4 that according to the PHASE DISTRIBUTION feature of single width stripe pattern, this method can directly be eliminated the inclination of two orthogonal directionss in single position, realize the local leveling of mask silicon chip, its precision is better than 10 ^-3Rad.In conjunction with the Flame Image Process in later stage, the phase analysis algorithm, precision is expected to reach 10 ^-4More than the rad.As a kind of effectively preliminary leveling scheme, can satisfy the prior art requirement.

The non-elaborated part of the present invention belongs to techniques well known.

Claims (2)

1. single-point mask silicon chip leveling method based on PHASE DISTRIBUTION, it is characterized in that: the direct incident of plane wave (1) is positioned at the two groups of adjacent marker gratings (3,5) on the mask (2), mark grating (3)+1 order diffraction light returns through silicon chip (4) surface reflection, see through once more mask (2) surface and mark grating (5)+1 order diffraction light forms two groups of interference fringes; When mask (2) and silicon chip (4) when being in parastate, the PHASE DISTRIBUTION unanimity of two groups of interference fringes; When exist between mask (2) and the silicon chip (4), the PHASE DISTRIBUTION of two groups of interference fringes is inconsistent, there are differences, and described difference is embodied in the difference on the frequency of two groups of interference fringes and the relative tilt angle of two groups of interference fringes; According to the difference on the frequency of two groups of interference fringes, calculate mask (2) and silicon chip (4) tilt quantity by formula (1), to eliminate the inclination of mask (2) and silicon chip (4), the leveling of realization cross-sectional direction in cross-sectional direction in cross-sectional direction; According to the relative tilt angle of two groups of interference fringes, calculate mask (2) and silicon chip (4) tilt quantity by formula (2), to eliminate the inclination of mask (2) and silicon chip (4), the leveling of realization longitudinal section direction in the longitudinal section direction in cross-sectional direction;

$\mathrm{\δf}=\frac{2(\cos {\mathrm{\θ}}_1+\cos {\mathrm{\θ}}_2)}{\mathrm{\λ}}\·\mathrm{\δ\θ}---\left(1\right)$

Wherein: δ f represents the difference on the frequency of two groups of interference fringes, θ _fThe relative tilt angle of representing two groups of interference fringes; δ θ represents the tilt quantity of silicon chip (4) in cross-sectional direction, and λ is the incident plane wave wavelength, θ ₁, θ ₂Be respectively two groups of adjacent marker gratings (3,5)+1 order diffraction angle;

Expression silicon chip (4) is in the tilt quantity of longitudinal section direction.

2. the single-point mask silicon chip leveling method based on PHASE DISTRIBUTION according to claim 1 is characterized in that: described two groups of adjacent marker gratings (3,5) are P by the cycle respectively ₁With P ₂, P ₂With P ₁Two gratings constitute up and down.

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