CN101995546A - Automatic test system and method of programmable logic device on basis of boundary scan - Google Patents
Automatic test system and method of programmable logic device on basis of boundary scan Download PDFInfo
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Abstract
The invention belongs to the field of electronic technology, in particular to an automatic test system and method of a programmable logic device on the basis of boundary scan. The test method comprises the following steps: generating a chip configuration file; downloading and configuring an FPGA (field programmable gate array) chip; generating and loading a test vector; comparing test results; building a corresponding test system; and completely realizing automation. In the invention, the test vector of an item to be tested is automatically generated by a user through software, and the on-line test of the hardware function of a user circuit is realized by combining JTAG (joint test action group) automatic downloading test software. Scripted test environment converts a series of complex manual test operation into full automatic software flow so as to greatly improve test speed and accuracy.
Description
Technical field
The invention belongs to electronic technology field, be specifically related to a kind of automatic test approach of programming device.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA), it is at programmable logic array (Programmable Array Logic, PAL), generic array logic (Generic Array Logic, GAL), (Complex Programmable Logic Device CPLD) waits the product that further develops on the basis of programming device to CPLD.It is at first as special IC (Application Specific Integrated Circuit, ASIC) approach of prototype functional verification and occurring, both solve the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.
Because the FPGA design cycle is short, Time To Market is fast, non-repetition engineering cost (Non-Recursive Engineering, NRE) low characteristics, have dynamically reconfigurable characteristic in addition, thereby in fields such as commercial communication, consumer electronics product, automobile, medical treatment, obtained to use widely.
Yet along with the explosive growth of fpga chip complicacy and density, the challenge that chip testing is faced is also increasing.Traditional method of testing is that chip is placed on the special exploitation motherboard, bit stream file is downloaded in the chip, produce the input signal of appointment then by signal generator, act on the port on the chip, be whether the signal of external each output pins of observation such as LED lamp of chip meets expection, the correctness of artificial judgment bit stream file by CRO coupling or mother matrix again.This method efficient is very low, can not do batch testing, can only observe the signal situation of change of limited output pin roughly, and is easy to take place mistake.
Second kind of method of testing is to use commercial on-line debugging software, as the SignalTap of altera corp and the ChipScope of Xilinx company etc.The supporting use of design software of the general and product company of this type of debugging software, can catch with the display chip system in the state [1] of live signal, but these debugging softwares are only supported the chip that own company produces, and whole flow process also must be carried out in corresponding supporting design software.This method versatility is not high, can not be used to test self-designed fpga chip and autonomous design software flow process.
The third method is to use commercial test macro, as the Agilent 93000 Pin Scale test machines [2] of Agilent Technologies.This method has high universalizable, high accuracy, but its corresponding software kit is comparatively complicated, and learning cost is higher, and the hardware support kit price is very expensive, does not meet the requirement of testing fast at lower cost.
In order to overcome the various shortcoming of above method, the present invention has realized a kind of based on JTAG(Joint Test Action Group) the automatic download test method of [3] boundary scan technique, satisfied mass test request fast and accurately.
List of references
[1]Altera,?“Design?Debugging?Using?the?SignalTap?II?Embedded?Logic?Analyzer”,?2009；
[2]Verigy,?V93000?Technical?Documentation?Center,?“Verigy?V93000?SmarTest?6.5.3?Help?Documentation”,?2010；
[3]IEEE?Standards,?Piscataway,?N.J.,?“ANSI/IEEE?Std?1149.1-1990?Standard Test?Access Port?and?Boundary-Scan?Architecture”,?1993。
Summary of the invention
The object of the present invention is to provide a kind of energy to satisfy mass test request fast and accurately, and low programmable logic device (PLD) Auto-Test System and the method for learning cost.
Programmable logic device (PLD) automatic test approach provided by the invention is a kind of based on JTAG(Joint Test Action Group) the automatic download test method of [3] boundary scan technique.Specifically comprise generation, the download configuration fpga chip of chip configuration file, the generation and the loading of test vector, and test result relatively waits, and made up corresponding detection system, all realize robotization, make things convenient for the user that design circuit is carried out simulation hardware, improve the efficient and the accuracy of test greatly.Specifically be described below:
1. based on the jtag boundary scanning technique
The jtag test method provides very high test coverage, in any case simultaneously complicated circuit only needs simple 4 ports (if comprise asynchronous reset signal TRST then be 5 ports) can realize test, this interface is known as TAP(Test Access Port again), this scheme has alleviated the problem that chip does not have enough physical addresss to be used to visit greatly.These TAP ports are respectively: test clock TCK(input), test mode selects the TMS(input), serial test data input TDI(input), serial test data output TDO(output).
The core of jtag test is the TAP controller, and its effect is that the tms signal of serial input is deciphered, and makes border scanning system enter corresponding work mode, and produces needed each control signal under this pattern.In the IEEE1149.1 standard, the decoding state of TMS list entries and TAP controller has been provided constitutional diagram as shown in Figure 1, the value of 0 or 1 numeral TMS on the arrow limit.
After system powers on, the TAP controller enters (Test-Logic-Reset) state that resets, the mode of operation of JTAG at first will be set, need the update instruction register for this reason, concrete state exchange flow process is as follows: " free time " (Run-Test/Idle), " selection data register " (Select-DR-Scan), " selection instruction register " (Select-IR-Scan), " catch instruction " (Capture-IR), " instruction shift " (Shift-IR), (Exit1-IR), " instruction comes into force " (Update-IR) gets back to " free time " state at last " to finish 1 "." catching instruction " state in said process, old director data is loaded in the middle of the order register; Enter into " instruction shift " state then, under this state,, a new specific instruction can be pushed in the middle of the order register by the driving of TCK; Again to " instruction comes into force " state, be input to instruction in the order register just now with decoded and make instruction formally effective, specify TDI, TDO port be connected with specific data register (as shown in Figure 2); At last, enter into " free time " state, wait for the next round control flow.
The test data register group that is shown in Figure 2, mainly comprise boundary scan register (Boundary Scan Register), bypass register (Bypass Register), device identification register (Identification Register), configuration register (Config Register) and order register (Instruction Register).Boundary scan register is a most important work register in the boundary scan testing, and it finishes the input of test vector, the essential operation of tests such as output latch and displacement (Fig. 2 make a circle outward register be boundary scan register); Bypass register is exactly one one bit register in fact, and it gets up the boundary scan chain short circuit of this chip, is mainly used in the series connection test of multicore sheet, and whether the basic function that also can be used for testing JTAG is normal; The device identification register is one 32 a standard register, and its content comprises information such as the version number, device model, manufacturer of this chip, and whether can be used for test chip working properly; Configuration register is mainly used in the configuration download and the retaking of a year or grade of chip, and it is as the impact damper of 32 bus datas, and the also string when string when being used for realizing disposing and conversion and retaking of a year or grade is changed; Order register promptly is used for selecting the register of mode of operation, selects one of above-mentioned test data register group to be connected between TDI and the TDO according to specific order code.
Visit by the selected data register of specific instruction, need be starting point still with " free time ", enter " selection data register " successively, " catch data " (Capture-DR), " data shift " (Shift-DR), (Exit1-DR), " data come into force " (Update-DR) gets back to " free time " state at last " to finish 1 ".To have selected the boundary scan register link is example, " catching data " state in said process, and current chip pin output state data are caught in the data register; Enter into " data shift " state then, under this state, by the driving of TCK, can be in the middle of data register with a new test vector data push, old pin output state data are exported from the TDO port simultaneously; To " data come into force " state, the test vector that was input to just now in the data register will formally be loaded on the chip pin by latch again; At last, get back to " free time " state, finish a loading of taking turns test vector.
2. based on the programmable logic device (PLD) Auto-Test System of JTAG
In order to realize above-mentioned automatic test approach, the present invention has at first proposed a cover and has been used for the system of test automatically.System forms as shown in Figure 3, and be divided into the hardware and software two large divisions: hardware components comprises the computing machine that is used to move automatic testing software, and programmable chip test board to be measured; Software section comprises composing software, test vector generator, serial ports Control Software and the regression test system that they are combined.Wherein:
Described composing software matches with chip to be measured, and it is used for user's project project file is compiled into the chip configuration file, and this document is downloaded to fpga chip just can become chip configuration the needed function of user.
Described test vector generator, use the perl script language compilation, it carries out emulation by call traditional simulation software (ModelSim instrument) under command line environment to user's design to be measured, and the waveform recording file conversion that generates after the emulation is become needed test vector form.In this way, can generate the test vector of various projects like clockwork, the coverage rate of test vector also can effectively be guaranteed.
Described serial ports Control Software uses C Plus Plus to write, and the general chained library control serial ports that it uses Windows XP operating system to provide makes it transmit and receive data by certain format.Because the TAP port of JTAG has 4, is respectively TCK, TMS, TDI, TDO, and the data of serial ports output have 8, and we stipulate that corresponding relation is as follows:
| The serial ports port | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| The TAP port | TDO | ? | ? | TMS | ? | TCK | TDI | ? |
Described regression test system, the irrelevant TCL script of usage platform is realized, can seamlessly call above-mentioned all test subsystems.By setting up regression testing policy, make things convenient for the user to carry out the system testing of many versions, do not introduce new mistake or cause other codes to produce mistake with the modification of confirming each version.Automatic regression test will significantly reduce the cost in stages such as system testing, maintenance upgrade.
3. based on the programmable logic device (PLD) automatic test approach of JTAG
In order to finish the purpose of full-automatic test, concrete steps of the present invention following (as shown in Figure 4):
(1). use TCL script environment to call the perl script that is used to generate a series of documents automatically.This script can call composing software user's project source program is compiled into the bit stream file that is used for the download configuration fpga chip; Call the test vector file that test vector generator generates prescribed form simultaneously.
(2). the serial ports of PC is connected to the jtag test port (TAP) of FPGA, and the jtag port of operation serial ports Control Software control chip changes the state of its TAP controller, makes it to move respectively following test pattern:
A) test bypass.Send the Bypass instruction, this instruction is connected to bypass register between TDI and the TDO port, is used to test whether operate as normal of JTAG.
Detailed process is: control JTAG state machine enters " instruction shift " state earlier, send Bypass order code (being " 1111 " in the test chip), control state machine enters " data shift " state again, one group of data that input is fixing, read the output of TDO again, and whether consistent with software approach inspection input with the output result.If two groups of data consistents then show the JTAG operate as normal.
B) test identification code.Send the IDCode instruction, this instruction is connected to the device identification register between TDI and the TDO port, is used for whether operate as normal of test chip.
Detailed process is: control JTAG state machine enters " instruction shift " state earlier, send IDCode order code (being " 1001 " in the test chip), control state machine enters " data shift " state again, import random one group 32 data, read 32 outputs of TDO again, the data of exporting under the normal condition should be consistent with predefined device identification sign indicating number in the chip.If two groups of data consistents then show the chip operate as normal.
C) configuring chip.Send the ConfigIn instruction, this instruction is connected to configuration register between TDI and the TDO port, is used to download the chip configuration file.
Detailed process is: control JTAG state machine enters " instruction shift " state earlier, send ConfigIn order code (being " 0101 " in the test chip), control state machine enters " data shift " state again, then read in the chip configuration file that step (1) generates, be downloaded to fpga chip by the TDI port, so far the function of chip has been configured and has finished.
D) test vector loads and compares.Send the Extest instruction, this instruction is connected to boundary scan register between TDI and the TDO port, is used for carrying out testing authentication according to test vector.
Detailed process is: control JTAG state machine enters " instruction shift " state earlier, send Extest order code (being " 0000 " in the test chip), control state machine enters " data shift " state again, then read in step (1) and generate test vector file, load successively by TDI and respectively to organize test vector, and, compare with expected results from the output result that TDO reads chip.All consistent as comparative result, then test is passed through, otherwise is defective.
(3). the statistical test result generates waveform and relatively reports.
Use TCL script environment to read in the next project in the tabulation to be measured automatically and repeat above process.
Description of drawings
The boundary scan state machine that Fig. 1 ieee standard 1149.1-1990 formulates.
Fig. 2 boundary scan register group.
Fig. 3 Auto-Test System is formed.
Fig. 4 automatic test approach process flow diagram.
Embodiment
For the testing requirement of analog subscriber, we have chosen various example to be measured and have amounted to 105, and wherein pure combinational circuit example amounts to 51, and the sequential circuit example amounts to 56; On function, comprise simple totalizer, multiplier, comparer, encryption and decryption logic, also comprise application such as complicated singing, VGA port are controlled, communication.In addition, a fpga chip that test board is selected for use is supported the jtag boundary scanning technique, and supporting with it composing software is arranged, and satisfies test request.
Only need import an order under command line environment during test, just can carry out comprehensively, compile, download, test and add up all 105 examples, whole process need not manually-operated, greatly makes things convenient for the user to carry out repeated test.Empirical tests, most examples all can pass through by disposable test, and the example of test crash can relatively be reported the problem of finding existence by checking waveform, the relevant issues of manual amendment's source file finally also can be tested and be passed through.
With simple totalizer project adder4 is example, and its source program comprises adder4.v and adder4_test.v, and the former is the behavioral scaling net meter file, and the latter is a simulation document.During operation regression test system, at first can call perl script and generate bit stream file adder4.bit and the test vector file adder4.txt that is used for configuring chip automatically.Then can call the serial ports Control Software and carry out jtag test, after carrying out the test of bypass test and identification code successively, bit stream file is downloaded to FPGA, read in test vector file and load test vector by boundary scan chain, read behind the result of test with the expected results that simulates relatively, obtain relatively report file adder4.rpt of waveform at last.
In whole testing process, the user only needs simply to import an order just can finish whole testing process automatically.And if use old-fashioned pure manual test, not only efficient is extremely low, and various mistakes very easily take place; Again with respect to the SignalTap of altera corp and the ChipScope of Xilinx company, though these instrument tests accurately, but in test process, still need certain manual operations, for large batch of test assignment, the user still needs to expend a large amount of time and efforts and operates, and it is applicable to the chip of company's production separately; Last Agilent 93000 Pin Scale test machines for Agilent Technologies, though its test accuracy, versatility and speed are all high, but also need the user to be ready to bit stream file and test vector in advance, the supporting software of this machine uses threshold high in addition, needs the cost plenty of time to learn its using method.
When using Auto-Test System that the present invention proposes and method, reality finds, this cover instrument not only is very easy to the simulation hardware test of user to the engineering code, also can be used in fpga chip itself is carried out hardware testing as the test of interconnection traversal, quite have practicality.
Claims (6)
1. based on the programmable logic device (PLD) Auto-Test System of boundary scan, it is characterized in that comprising the hardware and software two large divisions: hardware components comprises the computing machine that is used to move automatic testing software, and programmable chip test board to be measured; Software section comprises composing software, test vector generator, serial ports Control Software and the regression test system that they are combined; Wherein:
Described composing software matches with chip to be measured, and it is used for user's project project file is compiled into the chip configuration file, and this document is downloaded to fpga chip, and chip configuration is become the needed function of user;
Described test vector generator by call simulation software under command line environment, carries out emulation to user's design to be measured, and the waveform recording file conversion that generates after the emulation is become needed test vector form;
Described serial ports Control Software, the general chained library control serial ports that uses Windows XP operating system to provide makes it transmit and receive data by certain format; Corresponding to 4 TAP port: TCK, TMS, TDI, the TDO of JTAG, the data of serial ports output have 8, and its corresponding relation is as follows:
Described regression test system, the irrelevant TCL script of usage platform realizes that it seamlessly calls above-mentioned all test subsystems; By setting up regression testing policy, realize that the user carries out the system testing of many versions, do not introduce new mistake or cause other codes to produce mistake with the modification of confirming each version.
2. programmable logic device (PLD) automatic test approach based on boundary scan is characterized in that concrete steps are as follows:
(1) use TCL script environment to call the perl script that is used to generate a series of documents automatically, this script calls composing software user's project source program is compiled into the bit stream file that is used for the download configuration fpga chip; Call the test vector file that test vector generator generates prescribed form simultaneously;
(2) serial ports of PC is connected to the jtag test port of FPGA, the jtag test port of operation serial ports Control Software control chip changes the state of its TAP controller, makes it to move respectively following test pattern:
A), the test bypass sends the Bypass instruction, this instruction is connected to bypass register between TDI and the TDO port, is used to test whether operate as normal of JTAG;
B), the test identification code sends the IDCode instruction, this instruction is connected to the device identification register between TDI and the TDO port, is used for whether operate as normal of test chip;
C), configuring chip sends the ConfigIn instruction, this instruction is connected to configuration register between TDI and the TDO port, is used to download the chip configuration file;
D), test vector loads and relatively send the Extest instruction, this instruction is connected to boundary scan register between TDI and the TDO port, is used for carrying out testing authentication according to test vector;
(3) statistical test result generates waveform and relatively reports;
(4) use TCL script environment reads in the next project in the tabulation to be measured automatically, and repeats above process.
3. method according to claim 2, the concrete steps that it is characterized in that described test bypass are: control JTAG state machine enters " instruction shift " state earlier, send the Bypass order code, control state machine enters " data shift " state again, one group of data that input is fixing, read the output of TDO again, and whether consistent with software approach inspection input with the output result; If two groups of data consistents then show the JTAG operate as normal.
4. method according to claim 2, the concrete steps that it is characterized in that described test identification code are: control JTAG state machine enters " instruction shift " state earlier, send the IDCode order code, control state machine enters " data shift " state again, import random one group 32 data, read 32 outputs of TDO again, if the default identification code of these group data and chip internal is consistent then show the chip operate as normal.
5. method according to claim 2, the concrete steps that it is characterized in that described configuring chip are: control JTAG state machine enters " instruction shift " state earlier, send the ConfigIn order code, control state machine enters " data shift " state again, then read in the chip configuration file that step (1) generates, be downloaded to fpga chip by the TDI port.
6. method according to claim 2, it is characterized in that described test vector loads and concrete steps relatively are: control JTAG state machine enters " instruction shift " state earlier, send the Extest order code, control state machine enters " data shift " state again, then read in step (1) and generate test vector file, load successively by TDI and respectively to organize test vector, and read the output result of chip from TDO, compare with expected results, all consistent as comparative result, then test is passed through, otherwise is defective.
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