CN102054661B - Winding method and device of flip chip package - Google Patents
Winding method and device of flip chip package Download PDFInfo
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- CN102054661B CN102054661B CN200910209629.6A CN200910209629A CN102054661B CN 102054661 B CN102054661 B CN 102054661B CN 200910209629 A CN200910209629 A CN 200910209629A CN 102054661 B CN102054661 B CN 102054661B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to winding method and device applied to the flip chip package, wherein a flip chip comprises a plurality of outer liners and a plurality of inner liners. The winding method comprises the following steps of: setting a plurality of liner lines according to the arrangement sequence of the outer liner and the inner liner; and establishing a winding track from the innermost liner to the outermost liner sequentially, and selecting a winding track capable of contributing most direct connection between each liner line and the upper liner.
Description
Technical field
The invention relates to a kind of method for winding and device, especially about method for winding and the device of Flip-Chip Using (flip-chippackage).
Background technology
Along with the development of processing procedure, integrated circuit is now compared to having higher complexity and less volume in the past, and this characteristic also increases the degree of difficulty that chip import and export connects.Accordingly, a kind of have namely arise compared with high density of integration and compared with the flip-chip packaging techniques of multi output/enter pin count.Flip-Chip Using is a kind of technology that semiconductor devices can be connected to external circuit, and wherein said external circuit can comprise encapsulation loading bin (package carrier) or printed circuit board (PCB) (printed circuit board) etc.Compared to other encapsulation technology, the advantage of flip-chip packaging techniques comprises to have and can be used for area that import and export connects more, less interference can reach higher transfer rate, and can prevent external environment factor undesired signal.
Flip-chip packaging techniques uses the soldered ball (solder bump) be deposited in chip pad to be connected with external circuit, and wherein said soldered ball is the soldered ball liner (bump pad) in final wafer manufacturing phase deposition in wafer top layer.For described chip is installed on an external circuit, described chip is inverted to make its top layer downward, to make the liner of the external circuit described in the alignment of its soldered ball liner.Fig. 1 shows the schematic diagram of a Flip-Chip Using.As shown in Figure 1, a chip 100 is inverted to be installed on an encapsulation loading bin 200, and the top layer of wherein said chip 100 has several soldered ball liners 102, and it is connected on described encapsulation loading bin 200 by several soldered balls 104.Described chip 100 also has several wires in conjunction with liner (wire bonding pad) or driving liner (driver pad) 106.Fig. 2 shows the sectional view of described chip 100.As shown in Figure 2, for reducing the complexity of circuit design and reaching the object reducing change design, described chip 100 has one and is called that the extra metal level of redistribution layer (re-distribution layer) is on the top layer metallic layer of described chip 100, to connect described driving liner 106 to described soldered ball liner 102.
Compared to pin grid array (pin grid array) or the winding mode of ball grid array (ball grid array), the winding mode of Flip-Chip Using has more restriction.Because described redistribution layer is formed when the wafer manufacturing stage, the angled restriction of its winding mode tool, and the design rule (design rule) that must meet processing procedure.The winding mode of Flip-Chip Using can be divided into free distribution (freeassignment) coiling and allocate (pre-assignment) coiling two kinds of modes in advance.When using the flip-chip packaging techniques of free dispensing winding, the corresponding relation between liner and soldered ball liner is driven to be determined by user or winding tool software.Therefore, user or winding tool software have the coiling track between higher degree of freedom decision driving liner and soldered ball liner.On the other hand, when the flip-chip packaging techniques of coiling is allocated in use in advance, drive the corresponding relation between liner and soldered ball liner to be predetermine, and this corresponding relation cannot change when determining coiling.Therefore, user or winding tool software only can carry out coiling in accordance with this corresponding relation and be subject to more restriction.
Generally speaking, use the degree of difficulty allocating the Flip-Chip Using of the winding mode of coiling in advance high far beyond the Flip-Chip Using of the winding mode using free dispensing winding.But, because integrated circuit or the many customs of package design personnel predetermine the corresponding relation driven between liner and soldered ball liner, and be applied to the winding tool software allocating winding mode in advance also can be used for assessing described in the quality of corresponding relation, current industry mostly still uses and allocates winding mode in advance in flip-chip packaging techniques.
A kind of integer linear programming of current existence (integer linear programming) algorithm is for calculating the coiling track used when allocating the flip-chip packaging techniques of winding mode in advance.Integer linear programmed algorithm comprises two stages: the first stage is the coiling track connected between each driving liner of decision of complete-disc and the soldered ball liner of correspondence, and what subordinate phase was aided with details formula again completes described coiling track.But namely a wherein shortcoming of integer linear programmed algorithm is that it needs at substantial temporal calculation.For the industry of efficient and R&D costs, integer linear programmed algorithm the demand do not met in use.
Accordingly, required for industry is a kind ofly be applied to the method for winding of Flip-Chip Using and the device for realizing, it not only can respectively drive the coiling track connected between the soldered ball liner of liner and correspondence in efficient decision flip-chip packaging techniques, and can reach the object reducing required winding length.
Summary of the invention
Provided by the present invention be applied to Flip-Chip Using method for winding and device set several liners arrange according to putting in order of several liners on a chip, and utilize an algorithm to draw connection of detouring minimum needed for each liner Lie Inter.
The invention provides a kind of method for winding being applied to Flip-Chip Using, wherein said flip-chip comprises several outer liners and several internal layer liners, and described method for winding comprises the following step: several liners of setting that put in order according to described outer liner and internal layer liner arrange; And set up coiling track from the liner row of the liner leu time outer layers of innermost layer, and select to contribute the coiling track at most directly connected between each liner row and last layer liner row thereof.
The invention provides a kind of device of the winding mode for setting up Flip-Chip Using, wherein said flip-chip comprises several outer liners and several internal layer liners, and described device comprises a sequencing unit and a coiling unit.Described sequencing unit be arrangement described in outer liner and interior sequence of layer become several liners to arrange.Described coiling unit be to set up from the liner row of the liner leu time outer layers of innermost layer according to the ranking results of described sequencing unit described in outer liner and the coiling track of internal layer liner, to arrange to make each liner and detouring needed for coiling track between last layer liner row connects minimum.
Provided by the present invention be applied to Flip-Chip Using method for winding and device set several liners arrange according to putting in order of several liners on a chip, and utilize an algorithm to draw connection of detouring minimum needed for each liner Lie Inter.Because utilized algorithm only needs a little Time Calculation, therefore the method for winding being applied to Flip-Chip Using provided by the present invention can significantly reduce required operation time.
Accompanying drawing explanation
Fig. 1 shows the schematic diagram of a Flip-Chip Using;
Fig. 2 shows the sectional view of a Flip-Chip Using chip;
Fig. 3 show a flip-chip several drive annexation between liners and soldered ball liner;
Fig. 4 show a flip-chip several drive coiling track between liners and soldered ball liner;
Fig. 5 display is according to the process flow diagram being applied to the method for winding of Flip-Chip Using of one embodiment of the invention;
Fig. 6 display is according to the annexation between several driving liners of a flip-chip of one embodiment of the invention and soldered ball liner;
Fig. 7 display is according to the line of cut of one embodiment of the invention;
Fig. 8 display is according to the dummy pads of one embodiment of the invention;
Fig. 9 A ~ 9C shows dummy pads according to another embodiment of the present invention;
The annexation of the liner of Figure 10 display representated by a ground floor internal layer liner of one embodiment of the invention and outer liner row;
The annexation of the liner of Figure 11 display representated by a second layer internal layer liner of one embodiment of the invention and outer liner row;
The dummy pads that the current internal layer liner that Figure 12 shows one embodiment of the invention arranges builds on the schematic diagram in its last layer internal layer liner row;
The dummy pads of the liner connected that detours that the last layer internal layer liner that Figure 13 shows one embodiment of the invention arranges builds on the schematic diagram in described last layer internal layer liner row;
Figure 14 shows the virtual ring of one embodiment of the invention;
Figure 15 shows the result of calculation of maximum plane subclass string algorithms of one embodiment of the invention;
Figure 16 shows the coiling result set up according to one embodiment of the invention; And
Figure 17 display is according to the schematic diagram of the device of the winding mode for setting up Flip-Chip Using of one embodiment of the invention.
Embodiment
Provided by the present inventionly being applied to the method for winding of Flip-Chip Using and the device for realizing, is that several outer liners of a chip and putting in order of internal layer liner are set as that several liners arrange.Then, coiling track is set up from the liner row of the liner leu time outer layers of innermost layer according to maximum plane subclass string algorithm (maximum planar subset of chords), until complete described outer liner and the coiling track of internal layer liner, the coiling track wherein between each liner row and last layer liner row thereof be make required detour connect minimum.Because maximum plane subclass string algorithm can calculate in the mode of dynamic programming (dynamic programming) in low polynomial time (polynomial time), therefore the method for winding being applied to Flip-Chip Using provided by the present invention can significantly reduce required operation time.Again, because the coiling track between each liner row and last layer liner row thereof only needs minimum connection of detouring, therefore the object reducing required winding length can be reached.
Fig. 3 show a flip-chip several drive annexation between liners and soldered ball liner.As shown in Figure 3, described flip-chip 300 has 16 and drives liner and 16 soldered ball liners, and wherein said driving liner represents with square, and described soldered ball liner represents with octagon.In described annexation, most of annexation does not all produce coiling and interlocks, and so has local annexation to be produce coiling to interlock.Because the coiling of most flip-chip all completes in same layer metal level, that is redistribution layer, its coiling does not allow the staggered generation of coiling.In other words, the coiling that described generation coiling is cross-linked relation need complete with the connected mode that detours.Fig. 4 show described flip-chip 300 several drive coiling track between liners and soldered ball liner.As shown in Figure 4, the coiling that described generation coiling is cross-linked relation changes by the connected mode that detours to complete coiling.
Flip-chip annexation shown in Fig. 3 can determine which annexation can directly connected mode coiling by naked eyes, and which annexation can detour connected mode coiling.But the flip-chip packaging techniques that current industry uses comprises driving liner and the soldered ball liner of more than several order of magnitude, therefore driving liner described in cannot only determining with naked eyes and the annexation of soldered ball liner.Accordingly, the method for winding of Flip-Chip Using and the device for realizing of being applied to provided by the present invention sets up the track that detours between each liner, for reaching the object reducing required winding length according to maximum plane subclass string algorithm.
Fig. 5 display is according to the process flow diagram being applied to the method for winding of Flip-Chip Using of one embodiment of the invention.In step S1, determine that according to wish several internal layer liners of the flip-chip of coiling track and outer liner set an initial setting, and enter step S2.In step S2, set outer liner row and several internal layer liners row according to described internal layer liner and outer liner, the internal layer liner of setting innermost layer is classified as current internal layer liner row, and enters step S3.The dummy pads setting up current internal layer liner row is in the last layer internal layer liner row of described current internal layer liner row, and the dummy pads of the liner connected that detours in the last layer internal layer liner row described in foundation is in described last layer internal layer liner row; Set up a virtual ring according to described current internal layer liner row and last layer internal layer liner row thereof, and enter step S4.In step S4, according to the annexation of the liner on maximum plane subclass string algorithms and described virtual ring and the string set up on described virtual ring, connect for direct with the annexation defined corresponding to described string, and the not corresponding annexation of string described in definition is connection of detouring, set the internal layer liner row that current internal layer liner is classified as described last layer, and enter step S5.In step S5, determine the annexation whether defined all internal layer liners arrange.If so, then enter step S6, otherwise get back to step S3.In step S6, the internal layer liner described in foundation and the coiling track of outer liner.
Referring again to Fig. 3 and the method for application drawing 5 teachings, in step S1, carry out the initial setting of described flip-chip 300.As shown in Figure 6,16 described driving liners of the flip-chip 300 described in definition are outer liner, and 16 soldered ball liners described in definition are internal layer liner.Described outer liner annular form can divide into the outer liner ring of ground floor and the outer liner ring of the second layer, the outer liner ring of wherein said ground floor comprises the driving liner of D2, D3, D6, D7, D10, D11, D14 and D15, and the outer liner ring of the described second layer comprises the driving liner of D1, D4, D5, D8, D9, D12, D13 and D16.Described internal layer liner annular form can also divide into ground floor internal layer liner ring and second layer internal layer liner ring, wherein said ground floor internal layer liner ring comprises the soldered ball liner of B1 to B12, and described second layer internal layer liner ring comprises the soldered ball liner of B13 to B16.
In step S2, set outer liner row and several internal layer liners row according to described internal layer liner and outer liner.First, as shown in Figure 7, the outer liner ring described in cutting with a line of cut and internal layer liner ring also launch to become several liners row, and wherein said line of cut can not cut off described outer liner and the annexation of internal layer liner.If there is not this line of cut, then head/the portion of the outer liner row that the head/tail unit of reproducible outer liner row is extremely described.Such as, outer liner row (D1, D4, D1, D2, D5, D2, D3, D6, D3) can copy as (D3, D6, D3, D1, D4, D1, D2, D5, D2, D3, D6, D3, D1, D4, D1).
The method for winding being applied to Flip-Chip Using of the present embodiment is the order arranged to meet described outer liner as far as possible by the order of each liner in the internal layer liner row described in exchange, and reaches the object reducing connection of detouring.Accordingly, the method for winding being applied to Flip-Chip Using of the present embodiment uses may putting in order of the outer liner described in dummy pads representative.As shown in Figure 8, in another embodiment of the invention, one flip-chip has a ground floor outer liner row and the outer liner row of a second layer, the outer liner row of wherein said ground floor comprise d1 to d3 totally three outer liners, and the outer liner row of the described second layer comprise d4 to d6 totally three outer liners.Described outer liner d1 is connected to an internal layer liner, and wherein said connection can via the left side of described outer liner d4 or right side.Accordingly, namely described ground floor outer liner row and the described second layer outer liner row merge into outer liner row (d1, d4, d1, d2, d5, d2, d3, d6, d3), as shown in Figure 8.Referring again to Fig. 3, because the outer liner row described in the present embodiment do not exist multiple different path, in other words, except the annexation shown in Fig. 3, all the other paths all belong to connection of detouring, therefore namely described ground floor outer liner row and the described second layer outer liner row merge into outer liner row (D7, D8, a D9, D10, D11, D12, D13, D14, D15, D16, D1, D2, D3, D4, D5, D6).
In another embodiment of the invention, a flip-chip has an annexation, and it is the liner of connection more than three.As shown in Figure 9 A, a flip-chip comprises an annexation, and it connects a two outer liner d1 and d3 and internal layer liner b1.In the embodiment shown, produce a dummy pads b1 ' copied on described internal layer liner b1 side, wherein said internal layer liner b1 is connected to described outer liner d1, and described dummy pads b1 ' is connected to described outer liner d3, as shown in Figure 9 B.After coiling terminates, remerge described internal layer liner b1 and described dummy pads b1 ', as shown in Figure 9 C.Referring again to Fig. 3, do not comprise the annexation of the liner of connection more than three due to the present embodiment, therefore do not need to produce dummy pads separately.
Figure 10 shows the annexation of described ground floor internal layer liner row and the described liner representated by outer liner row.According to described annexation, namely ground floor internal layer liner row are defined as (n7, n8, n10, n11, n3, n12, n14, n15, n16, n1, n4, n6).
Figure 11 shows the annexation of described second layer internal layer liner row and the described liner representated by outer liner row.According to described annexation, namely second layer internal layer liner row are defined as (n9, n13, n2, n5).Then, the internal layer liner of setting innermost layer is classified as current internal layer liner row, that is setting second layer internal layer liner is classified as current internal layer liner row.
In step S3, the dummy pads of current internal layer liner row is set up in the last layer internal layer liner row of described current internal layer liner row, in described last layer internal layer liner row, set up in described last layer internal layer liner row the dummy pads of the liner connected that detours, and set up a virtual ring according to described current internal layer liner row and last layer internal layer liner row thereof.The dummy pads that Figure 12 shows described second layer internal layer liner row builds on the schematic diagram in described ground floor internal layer liner row.The method for winding being applied to Flip-Chip Using of the present embodiment is putting in order, to reach the maximized object of direct connection relational of the outer liner row described in as far as possible meeting that put in order that described dummy pads and described last layer internal layer liner are arranged.As shown in figure 12, the dummy pads B14 ' of described internal layer liner B14 is between described internal layer liner B6 and B7, to make the annexation of described internal layer liner B14 and described outer liner D9 for direct connection relational.In like manner, the dummy pads B15 ' of described internal layer liner B15 is between described internal layer liner B10 and B11, the dummy pads B16 ' of described internal layer liner B16 is between described internal layer liner B2 and B3, and the dummy pads B13 ' of described internal layer liner B13 is between described internal layer liner B3 and B4; To make the annexation of described internal layer liner B15 and described outer liner D13, the annexation of described internal layer liner B16 and described outer liner D2, and the annexation of described internal layer liner B13 and described outer liner D5 is direct connection relational.
Secondly, according to Figure 10, be need with annexation coiling of detouring between described internal layer liner B9 and described outer liner D2.The dummy pads that Figure 13 shows the liner connected that detours of described ground floor internal layer liner row builds on the schematic diagram in described ground floor internal layer liner row.As shown in figure 13, the dummy pads B9 ' of described internal layer liner B9 builds between described internal layer liner B3 and described dummy pads B16 ', to make the annexation of described dummy pads B9 ' and described outer liner D2 for be directly connected.
Then, virtual ring is set up according to described ground floor internal layer liner row and described second layer internal layer liner row.Figure 14 shows the virtual ring of described foundation, wherein said virtual ring has the liner B13 ~ B16 on dummy pads B14 ', B15 ' on described ground floor internal layer liner row, B16 ', B13 ', B9 ', described detour the liner B9 and described second layer internal layer liner row that connect.As shown in figure 14, according to the annexation of the liner described on described virtual ring, five strings can be set up on described virtual ring.
In step S4, string on virtual ring described in setting up according to the annexation of the liner on maximum plane subclass string algorithms and described virtual ring, to define annexation corresponding to described string for directly connecting, and the not corresponding annexation of string described in definition is connection of detouring.The method for winding being applied to Flip-Chip Using of the present embodiment is that the maximum plane subclass string algorithm of application is found out on described virtual ring and can be there is the string do not intersected each other at most simultaneously, wherein at most the calculating of plane subclass string algorithm can according to algorithm known at present or other algorithm any, and person skilled in the art can the account form of apparent maximum plane subclass string algorithm.
As shown in figure 15, according to maximum plane subclass string algorithm, described virtual ring can exist at most simultaneously described liner B13 and its dummy pads B13 ', described liner B14 and its dummy pads B14 ', described liner B15 and its dummy pads B15 ' and totally four strings between described liner B16 and its dummy pads B16 ', annexation corresponding to it is directly connect, and the annexation between described liner B9 and its dummy pads B9 ' is then defined as connection of detouring.Then, the internal layer liner row that current internal layer liner is classified as described ground floor are set.
In step S5, determine the annexation whether defined all internal layer liners arrange.Because the annexation between the internal layer liner row of described ground floor and the internal layer liner row of the described second layer has been set up complete, therefore enter step S6.
In step S6, the internal layer liner described in foundation and the coiling track of outer liner.Accordingly, the coiling track according to Figure 16, namely the coiling of described flip-chip 300 completes result as shown in Figure 4.
Figure 17 display is according to the schematic diagram of the device of the winding mode for setting up Flip-Chip Using of one embodiment of the invention.As shown in figure 17, described device 1700 comprises sequencing unit 1710, computing unit 1720 and a coiling unit 1730.Described sequencing unit 1710 is that several outer liners of arrangement and interior sequence of layer become several liners to arrange.Described computing unit 1720 is the annexations according to the coiling result of described coiling unit 1730 and the outer liner at most described in the definition of plane subclass string algorithm and internal layer liner, and provides result of calculation to described coiling unit 1730 to set up described outer liner and the coiling track of internal layer liner.Described coiling unit 1730 sets up virtual ring according to the ranking results of described sequencing unit, and the coiling track of outer liner described in setting up from the liner row of the liner leu time outer layers of innermost layer according to the result of calculation of described computing unit 1720 and internal layer liner, to arrange to make each liner and detouring needed for coiling track between last layer liner row connects minimum.
The method of corresponding teachings of the present invention, described sequencing unit 1710 determines that several internal layer liners of the flip-chip of coiling track and outer liner set an initial setting according to wish, and set outer liner row and several internal layer liners row according to described internal layer liner and outer liner.For individual other internal layer liner row, described coiling unit 1730 be set up described in the dummy pads of the internal layer liner row last layer internal layer liner that arrange in described internal layer liner arrange, described in foundation last layer internal layer liner row in detour connect liner dummy pads in described last layer internal layer liner row in, and according to described internal layer liner row and last layer internal layer liner row set up a virtual ring.Again, described coiling unit 1730 be set up described in internal layer liner and the coiling track of outer liner.Described computing unit 1720 be set up according to the annexation of the liner on maximum plane subclass string algorithms and described virtual ring described in virtual ring on string to define annexation corresponding to described string for directly connecting, and the not corresponding annexation of string described in definition is connection of detouring.
Device shown in Figure 17 can realize in hardware, can also utilize a hardware implementing by software.Such as, in sum, provided by the present inventionly be applied to the method for winding of Flip-Chip Using and the device for realizing, be that putting in order of several outer liners of a chip is set as outer liner row, and putting in order of several internal layer liners of described chip is set as that several internal layer liners arrange.Then, the annexation between the internal layer liner row described in the foundation of maximum plane subclass string algorithm is utilized, minimum to make detouring needed for it connect.Because described maximum plane subclass string algorithms can the mode with dynamic programming in low polynomial time calculate, therefore the method for winding being applied to Flip-Chip Using provided by the present invention can significantly reduce required operation time.In addition, because the method for winding of Flip-Chip Using and the device for realizing of being applied to provided by the present invention is for finding out the minimum winding mode connected that detours, therefore the object reducing required winding length is reached.
Technology contents of the present invention and technical characterstic disclose as above, but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by present patent application claim.
Claims (11)
1. be applied to a method for winding for Flip-Chip Using, described flip-chip comprises several outer liners and several internal layer liners, it is characterized in that described method for winding comprises the following step:
Several liners of setting that put in order according to described outer liner and internal layer liner arrange; And
Set up coiling track from the liner row of the liner leu time outer layers of innermost layer, and select to contribute the coiling track at most directly connected between each liner row and last layer liner row thereof,
The wherein said step setting up coiling track comprises the following step further:
The liner of setting innermost layer is classified as current liner row;
The dummy pads of current liner row is set up in the last layer liner row of described current liner row, in described last layer liner row, set up in described last layer liner row the dummy pads of the liner connected that detours, and set up a virtual ring according to described current liner row and last layer liner row thereof;
String on virtual ring described in setting up according to the annexation of the liner on maximum plane subclass string algorithms and described virtual ring is to define annexation corresponding to described string for directly connecting, and the not corresponding annexation of string described in definition is for detouring connection; And
If the annexation between undefined complete described outer liner and internal layer liner, then set described last layer liner and be classified as current liner row, and the step setting up virtual ring and definition annexation described in repeating.
2. method for winding according to claim 1, is characterized in that, wherein said outer liner and putting in order of described internal layer liner are on described flip-chip, form several liner rings.
3. method for winding according to claim 1, is characterized in that, wherein said liner row are that the virtual ring described in a line of cut cuts obtains with expansion.
4. method for winding according to claim 2, is characterized in that, if wherein do not have one without the line of cut crossing over annexation, then copies the head/portion of head/tail unit to described outer liner row of the outer liner row corresponding to described outer liner.
5. method for winding according to claim 1, is characterized in that, if putting in order of wherein described outer liner forms several outer liner row, then and the outer liner row described in merging.
6. method for winding according to claim 5, is characterized in that, wherein said merging process is may put in order with the outer liner described in dummy pads representative, and wherein said dummy pads represents the possible coiling track of the outer liner of its correspondence.
7. method for winding according to claim 1, is characterized in that, if wherein there is an annexation to connect the liner of more than three, then produces virtual internal layer liner and only connects two liners to make each annexation.
8., for setting up a device for the winding mode of Flip-Chip Using, described flip-chip comprises several outer liners and several internal layer liners, it is characterized in that described device comprises:
One sequencing unit, the outer liner described in arrangement and interior sequence of layer become several liners to arrange;
One coiling unit, outer liner described in setting up from the liner row of the liner leu time outer layers of innermost layer according to the ranking results of described sequencing unit and the coiling track of internal layer liner, minimum to make detouring needed for the coiling track between each liner row and last layer liner row thereof connect, and
One computing unit, according to the annexation of the coiling result of described coiling unit and the outer liner at most described in the definition of plane subclass string algorithm and internal layer liner, and provide result of calculation to described coiling unit to set up described outer liner and the coiling track of internal layer liner.
9. device according to claim 8, is characterized in that, wherein said sequencing unit is the liner row put in order described in setting according to described outer liner and internal layer liner.
10. device according to claim 8, is characterized in that, wherein said outer liner is the driving liner of described flip-chip.
11. devices according to claim 8, is characterized in that, wherein said internal layer liner is the soldered ball liner of described flip-chip.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209629.6A CN102054661B (en) | 2009-10-30 | 2009-10-30 | Winding method and device of flip chip package |
| PCT/IB2010/002738 WO2011051785A2 (en) | 2009-10-30 | 2010-10-27 | Routing method for flip chip package and apparatus using the same |
| US13/504,374 US8578317B2 (en) | 2009-10-30 | 2010-10-27 | Routing method for flip chip package and apparatus using the same |
| US14/045,090 US8875083B2 (en) | 2009-10-30 | 2013-10-03 | Routing method for flip chip package and apparatus using the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209629.6A CN102054661B (en) | 2009-10-30 | 2009-10-30 | Winding method and device of flip chip package |
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| Publication Number | Publication Date |
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| CN102054661A CN102054661A (en) | 2011-05-11 |
| CN102054661B true CN102054661B (en) | 2015-02-18 |
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| CN103886157B (en) * | 2014-03-28 | 2016-10-12 | 清华大学 | In system in package, bus at the bilateral solution winding methods detoured under constraint more |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6490713B2 (en) * | 2000-01-26 | 2002-12-03 | International Business Machines Corporation | Method and apparatus for automatically generating multi-terminal nets, and program storage medium storing program for executing automatic multi-terminal net generation method |
| US7496878B2 (en) * | 2004-04-13 | 2009-02-24 | Shinko Electrics Industries Co., Ltd. | Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package |
| CN201608164U (en) * | 2009-10-30 | 2010-10-13 | 新思科技有限公司 | Winding device for packaging flip chip |
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2009
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6490713B2 (en) * | 2000-01-26 | 2002-12-03 | International Business Machines Corporation | Method and apparatus for automatically generating multi-terminal nets, and program storage medium storing program for executing automatic multi-terminal net generation method |
| US7496878B2 (en) * | 2004-04-13 | 2009-02-24 | Shinko Electrics Industries Co., Ltd. | Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package |
| CN201608164U (en) * | 2009-10-30 | 2010-10-13 | 新思科技有限公司 | Winding device for packaging flip chip |
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