CN102137547B - Manufacturing method of circuit structure of circuit board - Google Patents
Manufacturing method of circuit structure of circuit board Download PDFInfo
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- CN102137547B CN102137547B CN2010101101529A CN201010110152A CN102137547B CN 102137547 B CN102137547 B CN 102137547B CN 2010101101529 A CN2010101101529 A CN 2010101101529A CN 201010110152 A CN201010110152 A CN 201010110152A CN 102137547 B CN102137547 B CN 102137547B
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- layer
- rete
- insulating barrier
- wiring board
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Abstract
The invention relates to a manufacturing method of a circuit structure of a circuit board, which comprises: firstly, providing a substrate which comprises an insulation layer and a film layer arranged on the insulation layer; secondly, forming a barrier layer which covers the film layer completely; thirdly, forming a chiseled pattern exposing the insulation layer locally on the outside surface of the barrier layer; fourthly, forming an activated layer on the outside surface and in the chiseled pattern; fifthly, removing the activated layer on the outside surface and keeping the activated layer in the chiseled pattern; sixthly, forming a conductive material in the chiseled pattern by a chemical deposition method after the activated layer on the outside surface is removed; and finally, removing the barrier layer and the film layer after the conductive material is formed. The circuit structure can be manufactured without forming a patterned photoresisting layer, so the manufacturing method of the circuit structure can avoid using a lithographic step.
Description
Technical field
The present invention relates to the manufacturing process of a kind of wiring board (wiring board), particularly relate to a kind of manufacture method of line construction of wiring board.
Background technology
In wiring board manufacturing technology now, the line construction of wiring board is all to utilize electroless-plating (electroless plating) to form with electricity plating (electroplating) is arranged usually.Specifically, in the manufacture process of present line construction, usually first carry out electroless-plating, sequentially form Seed Layer (seed layer) and electroless plating layer (chemical plating layer) on dielectric layer (dielectric layer), wherein Seed Layer and electroless plating layer cover the surface of dielectric layer all comprehensively.
Then, utilize little shadow (lithograph), form patterning photoresist layer (patterned photoresist layer) on the electroless plating layer, its local electroless plating layer that exposes.Afterwards, there is electricity to electroplate, form electroplated metal layer (electroplating metal layer) on the electroless plating layer.Then, carry out etching (etching), part electroless plating layer is removed, to form line layer (wiring layer).So, the line construction of wiring board is accomplished.
Summary of the invention
The object of the invention is to, overcome the defect that the manufacture method of existing wiring board exists, and a kind of manufacture method of line construction of new wiring board is provided, in order to make the line construction of wiring board.
The invention provides a kind of manufacture method of line construction of wiring board, it comprises, a substrate is provided, and it comprises that an insulating barrier and is configured in the rete on insulating barrier, and wherein rete covers insulating barrier comprehensively.Then, form the barrier layer of a comprehensive covering rete, wherein barrier layer has an outer surface.Afterwards, form on the outer surface a local intaglio pattern that exposes insulating barrier.Then, form an active layer on the outer surface and in intaglio pattern, wherein active layer covers all surface of outer surface and intaglio pattern comprehensively.Then, remove the active layer on outer surface, and only be retained in intaglio pattern and the active layer that contacts with this insulating barrier.After active layer on removing outer surface, utilize a chemical deposition, form an electric conducting material in intaglio pattern, wherein active layer participates in the chemical reaction of chemical deposition.After forming electric conducting material, remove barrier layer and rete.
In an embodiment of the present invention, above-mentioned chemical deposition comprises electroless-plating.
In an embodiment of the present invention, above-mentioned chemical deposition is chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD).
In an embodiment of the present invention, the method for above-mentioned formation active layer comprises barrier layer, this rete and insulating barrier is immersed in the solion that contains a plurality of metal ions.
In an embodiment of the present invention, above-mentioned rete can be metal level, and the method for formation substrate is included in depositing metal layers on insulating barrier.
In an embodiment of the present invention, wherein said rete is a metal level, and the method for this rete of configuration comprises on this insulating barrier, and pressing one tinsel (metallic foil) is on insulating barrier.After the pressing tinsel, reduce the thickness of tinsel.
In an embodiment of the present invention, above-mentioned barrier layer can be metal level, and the method for formation barrier layer is included in depositing metal layers on rete.
In an embodiment of the present invention, the method for above-mentioned formation intaglio pattern comprises substrate is carried out laser ablation (laser ablation) or plasma etching (plasma etching).
In an embodiment of the present invention, the flow process of above-mentioned formation intaglio pattern comprises the grooves (trench) that form on the outer surface many local exposure insulating barriers, and the flow process of above-mentioned formation electric conducting material is included in formation one patterned conductive layer in these grooves.
In an embodiment of the present invention, aforesaid substrate more comprises a line layer.This line layer is positioned on the another side of the insulating barrier relative with rete, and insulating barrier covers line layer.
In an embodiment of the present invention, aforesaid substrate more comprises an internal layer circuit substrate (inner wiring board).Edge layer and line layer all are configured on the internal layer circuit substrate, and line layer is electrically connected the internal layer circuit substrate.The flow process of above-mentioned formation intaglio pattern comprises the blind hole (blind via) that forms at least one local exposed line layer, and the flow process of above-mentioned formation electric conducting material is included in formation one conductive pole in blind hole.
In sum, utilization of the present invention remains in active layer and the above-mentioned chemical deposition in intaglio pattern, allows electric conducting material be formed in intaglio pattern.So, the line construction of wiring board can be out manufactured.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above and other purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by embodiment, and the cooperation accompanying drawing, be described in detail as follows.
Description of drawings
Figure 1A to Fig. 1 G is the schematic flow sheet of manufacture method of line construction of the wiring board of one embodiment of the invention.
110: substrate
112: insulating barrier
114: rete
116: line layer
118: the internal layer circuit substrate
118a: surface
119: barrier layer
119a: outer surface
120: intaglio pattern
122: groove
124: blind hole
130: active layer
140: electric conducting material
142: patterned conductive layer
142a: connection pad
142b: cabling
144: conductive pole
B1, B2: bottom
S1, S2: sidewall
Embodiment
Reach for further setting forth the present invention technological means and the effect that predetermined goal of the invention is taked, below in conjunction with drawings and Examples, its embodiment of manufacture method, method, step, feature and the effect thereof of the line construction of the wiring board that foundation the present invention is proposed, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic, can clearly present in the following detailed description that coordinates with reference to graphic embodiment.For convenience of description, in following embodiment, identical element represents with identical numbering.
Figure 1A to Fig. 1 G is the schematic flow sheet of manufacture method of line construction of the wiring board of one embodiment of the invention.See also Figure 1A, the manufacture method about the line construction of the wiring board of the present embodiment, at first, provide a substrate 110.Substrate 110 comprises an insulating barrier 112 and a rete 114, and wherein rete 114 is configured on insulating barrier 112, and comprehensive the insulating barrier 112 that covers.
Rete 114 can be metal level, and its material is such as being the metal materials such as copper, nickel, chromium or aluminium.Insulating barrier 112 can be solidified under HTHP by semi-solid preparation film (prepreg) form, wherein the material of insulating barrier 112 can be the rete that resin (resin) and glass fibre both mix.In addition, insulating barrier 112 can be also a kind of polymer material layer, its material is for example polyimides (polyimide, PI), liquid crystal polymer (Liquid Crystal Polymer, LCP) or ABF (Ajinomoto Build-up Film).
When rete 114 was metal level, the method that forms substrate 110 can be deposition this metal level (being rete 114) on insulating barrier 112, and the method for depositing metal layers can be sputter (sputter) or electroless-plating.In addition, the method that forms substrate 110 can be pressing piece of metal paillon foil on insulating barrier 112, wherein this tinsel can be for example Copper Foil or gum Copper Foil (Resin Coated Copper, RCC).
Hold above-mentionedly, after the pressing tinsel, then, reduce the thickness of tinsel, to form rete 114, the method that wherein reduces the thickness of tinsel is for example that tinsel is carried out etching, and this etching is for example Wet-type etching.Can remove the part metals paillon foil like this, allow the thickness attenuation of tinsel.
In the present embodiment, substrate 110 can more comprise a line layer 116 and an internal layer circuit substrate 118, wherein 116 of line layers are on the relative position of rete 114, and can be electrically connected internal layer circuit substrate 118, and insulating barrier 112 all is configured on internal layer circuit substrate 118 with line layer 116, and wherein insulating barrier 112 covers the surperficial 118a of line layer 116 and internal layer circuit substrate 118.
The inside of internal layer circuit substrate 118 has at least one sandwich circuit layer (not illustrating), be that internal layer circuit substrate 118 can be considered in fact a kind of wiring board, and in follow-up manufacturing process, will can form line layer on insulating barrier 112, so the manufacture method of the line construction of the present embodiment can be applied to the manufacturing of multilayer circuit board (multilayer wiring board).
In the embodiment that other do not illustrate, line layer 116 is all selection element with internal layer circuit substrate 118, and inessential element, be that substrate 110 not necessarily will comprise line layer 116 and internal layer circuit substrate 118, and the manufacture method of the line construction of the present embodiment also can be applied to one-sided circuit board (single-side wiring board) and double-sided wiring board (double-side wiring board) manufacturing both.
Specifically, when substrate 110 comprises line layer 116, and while not comprising internal layer circuit substrate 118, the manufacture method of the line construction of the present embodiment can be applied to the manufacturing of double-sided wiring board.When substrate 110 did not all comprise line layer 116 with internal layer circuit substrate 118, the manufacture method of the line construction of the present embodiment can be applied to the manufacturing of one-sided circuit board.
See also Figure 1B, then, form a barrier layer 119 on rete 114, the comprehensive covering rete 114 of barrier layer 119 wherein, and have an outer surface 119a.Barrier layer 119 can be metal level or non-metallic layer, and the material of this non-metallic layer is for example macromolecular material or ceramic material.
When barrier layer 119 and rete 114 were all metal level, barrier layer 119 and rete 114 both material can be the metal materials such as copper, nickel, chromium or aluminium, but both material can be different, and for example barrier layer 119 is the chromium metal level, and rete 114 is copper metal layer.In addition, the method that forms barrier layer 119 can be depositing metal layers on rete 114 (being barrier layer 119), and wherein the method for depositing metal layers can be sputter, have electricity to electroplate or electroless-plating.
See also Figure 1B and Fig. 1 C, then, form Shu intaglio pattern 120 on the outer surface 119a of barrier layer 119, wherein intaglio pattern 120 is local exposes insulating barriers 112, thus intaglio pattern 120 be remove part barrier layer 119, part rete 114 forms with partial insulative layer 112.In addition, the method for formation intaglio pattern 120 can be that substrate 110 is carried out laser ablation or plasma etching.
In Fig. 1 C, intaglio pattern 120 can comprise many local grooves 122 and a plurality of blind holes 124 that expose insulating barrier 112, and wherein at least one blind hole 124 is positioned at the wherein below of a groove 122, and is communicated with groove 122.In addition, in the embodiment that other do not illustrate, the quantity of the blind hole 124 that intaglio pattern 120 is included can be only one, thus the quantity of the blind hole 124 shown in Fig. 1 C only for illustrating, and non-limiting the present invention.
In forming the flow process of intaglio pattern 120, at first, can form these grooves 122 on the outer surface 119a of barrier layer 119, wherein groove 122 is for example to form with laser ablation or plasma etching.Then, form the blind hole 124 of these local exposed line layers 116, the method that wherein forms blind hole 124 can be that substrate 110 is carried out machine drilling (mechanical drilling), laser drill (laser drilling) or plasma etching.
It is worth mentioning that, in the embodiment that other do not illustrate, intaglio pattern 120 can only comprise groove 122 and blind hole 124 both one of them, namely intaglio pattern 120 only comprises these grooves 122, and does not comprise any blind hole 124; Or intaglio pattern 120 only comprises at least one blind hole 124, and does not comprise any groove 122.Therefore, the intaglio pattern 120 shown in Fig. 1 C, only for illustrating, is not to limit the present invention.
See also Fig. 1 D, then, on outer surface 119a and at interior formation one active layer 130 of intaglio pattern 120, wherein active layer 130 covers all surface of outer surface 119a and intaglio pattern 120 comprehensively.Specifically, take Fig. 1 D as example, active layer 130 covers outer surface 119a not only comprehensively, and property ground covers these grooves 122 and blind hole 124 bottom (bottom) B1, B2 and sidewall (sidewall) S1, S2 both more comprehensively, and namely active layer 130 also covers line layer 116 in part.
The method that forms active layer 130 has a variety of enforcement means, and in the present embodiment, the method that forms active layer 130 can be that barrier layer 119 and insulating barrier 112 are immersed in solion (not illustrating), wherein this solion contains a plurality of metal ions, and these metal ions can be for example nickel ion, palladium ion, platinum ion, chromium ion, silver ion or molybdenum ion.
In the present embodiment, when barrier layer 119 and insulating barrier 112 are immersed in solion, the barrier layer 119, rete 114, insulating barrier 112 and the line layer 116 that are exposed in intaglio pattern 120 all can contact with solion, allow these adsorption of metal ions on barrier layer 119, rete 114, insulating barrier 112 and line layer 116, to form active layer 130.Therefore, active layer 130 can contact barrier layer 119, rete 114, insulating barrier 112 and line layer 116.
Specifically, when solion contact barrier layer 119, rete 114, insulating barrier 112 and line layer 116, these metal ions can be transformed into chelate (chelate), and these metal ions that become chelate can be adsorbed on all surface of outer surface 119a and intaglio pattern 120, and wherein the adsorption strength between rete 114, barrier layer 119 and line layer 116 threes and metal ion is all less than the adsorption strength between insulating barrier 112 and metal ion.In other words, active layer 130 easily removes with line layer 116 from rete 114, barrier layer 119, but active layer 130 but is difficult to remove from insulating barrier 112.
See also Fig. 1 D and Fig. 1 E, then, remove the active layer 130 on outer surface 119a, to expose barrier layer 119 and line layer 116, and keep the active layer 130 in intaglio pattern 120, the method that wherein removes the active layer 130 on outer surface 119a can be etching, and it is for example Wet-type etching, and in the present embodiment, the active layer 130 that contacts with insulating barrier 112 can be retained.
Particularly, when utilizing etched mode to remove active layer 130 on outer surface 119a, because active layer 130 easily removes with line layer 116 from rete 114, barrier layer 119, and be difficult to remove from insulating barrier 112, therefore the active layer 130 that contacts with rete 114, barrier layer 119 and line layer 116 can be by ablation, and the active layer 130 of transference insulating barrier 112 contacts is retained.
See also Fig. 1 F, then, utilize chemical deposition, at interior formation one electric conducting material 140 of intaglio pattern 120, wherein active layer 130 participates in the chemical reaction of this chemical deposition, be that electric conducting material 140 is chemical reactions that occur via active layer 130 and forming, so chemical deposition can limit the formation of electric conducting material 140, allow electric conducting material 140 only be formed on active layer 130.In addition, electric conducting material 140 can be identical with rete 114 material both, such as both material, can be all the metal materials such as copper, nickel, chromium or aluminium.
Above-mentioned chemical deposition can be chemical vapour deposition (CVD) or electroless-plating; Perhaps, chemical deposition can comprise electroless-plating and have electricity to electroplate.When chemical deposition comprises electroless-plating and have electricity to electroplate, the flow process that forms electric conducting material 140 can be sequentially to carry out electroless-plating and have electricity to electroplate, wherein after carrying out electroless-plating and the electricity plating arranged, if barrier layer 119 is the words of metal level, not only form electric conducting material 140, simultaneously also can deposit one deck electroplated metal layer (not illustrating) on barrier layer 119, wherein both material is identical with electric conducting material 140 for this electroplated metal layer.
In the flow process that forms electric conducting material 140, can be at the interior formation patterned conductive layer 142 of these grooves 122, and at the interior formation conductive pole 144 of these blind holes 124, wherein patterned conductive layer 142 is a kind of line layer, and namely patterned conductive layer 142 comprises connection pad (pad) 142a and many cablings (trace) 142b.Therefore, electric conducting material 140 can comprise patterned conductive layer 142 and at least one conductive pole 144.
Hold above-mentioned, these conductive poles 144 are electrically connected between patterned conductive layer 142 and line layer 116, for example at least one conductive pole 144 is positioned at the below of one of them connection pad 142a, and connect connection pad 142a, so patterned conductive layer 142 can be electrically connected internal layer circuit substrate 118 by conductive pole 144 and line layer 116.In addition, these conductive poles 144 can fill up these blind holes 124.But, in the embodiment that other do not illustrate, conductive pole 144 also can not fill up blind hole 124, so conductive pole 144 and the non-limiting the present invention shown in Fig. 1 F.
Should be noted that, in the embodiment that other do not illustrate, due to intaglio pattern 120 can only comprise groove 122 and blind hole 124 both one of them, therefore in the flow process that forms electric conducting material 140, also can only form conductive pole 144 or patterned conductive layer 142, so the electric conducting material 140 shown in Fig. 1 F, only for illustrating, does not limit the present invention.
Specifically, when intaglio pattern 120 only comprises blind hole 124, and while not comprising any groove 122, the present embodiment can only form conductive pole 144, and does not form patterned conductive layer 142.When intaglio pattern 120 only comprises groove 122, and while not comprising any blind hole 124, the present embodiment can only form patterned conductive layer 142, and does not form conductive pole 144.
See also Fig. 1 F and Fig. 1 G, after forming electric conducting material 140, remove barrier layer 119 and rete 114, wherein removing barrier layer 119 can be etching with the method for rete 114, and it can be for example Wet-type etching.So far, basically, a kind ofly comprise that the line construction of the wiring board of electric conducting material 140 and insulating barrier 112 made.
In addition, when electric conducting material 140 is to utilize electroless-plating to form with there being electricity to electroplate, and electric conducting material 140 is when both material is identical with rete 114, the electroplated metal layer that is deposited on barrier layer 119 also can be by the mode of etching (for example Wet-type etching), along with rete 114 is removed together, namely electroplated metal layer and rete 114 can remove in same etching liquid.
In sum, utilization of the present invention remains in active layer and the above-mentioned chemical deposition in intaglio pattern, allows electric conducting material be formed in intaglio pattern, and then produces the line construction that comprises line layer (being patterned conductive layer) or conductive pole.Compared to the manufacture method of the line construction of known wiring board, the present invention can form the patterning photoresist layer, can produce line construction, and therefore the manufacture method of line construction of the present invention can be omitted the step of carrying out little shadow.
the above, only embodiments of the invention, not the present invention is done any pro forma restriction, although the present invention discloses as above with embodiment, yet not in order to limit the present invention, anyly be familiar with those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, any simple modification that foundation technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. the manufacture method of the line construction of a wiring board is characterized in that it comprises:
One substrate is provided, and it comprises that an insulating barrier and is configured in the rete on this insulating barrier, and wherein this rete covers this insulating barrier comprehensively;
Form the barrier layer of comprehensive this rete of covering, wherein this barrier layer has an outer surface;
Form a local intaglio pattern that exposes this insulating barrier on this outer surface;
Forming an active layer on this outer surface and in this intaglio pattern, wherein this active layer covers all surface of this outer surface and this intaglio pattern comprehensively, the method that forms this active layer comprises this barrier layer, this rete and this insulating barrier is soaked in the solion that contains a plurality of metal ions, and the adsorption strength between this rete and this barrier layer and described metal ion is all less than the adsorption strength between this insulating barrier and described metal ion;
Remove the active layer on this outer surface, and only be retained in this intaglio pattern and the active layer that contacts with this insulating barrier;
After active layer on removing this outer surface, utilize a chemical deposition, form an electric conducting material in this intaglio pattern, wherein this active layer participates in the chemical reaction of this chemical deposition; And
After forming this electric conducting material, remove this barrier layer and this rete.
2. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said chemical deposition comprises electroless-plating.
3. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said chemical deposition is chemical vapour deposition (CVD).
4. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said rete is a metal level, and the method that forms this substrate is included in this metal level of deposition on this insulating barrier.
5. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said rete is a metal level, and the method for this rete of configuration comprises on this insulating barrier:
Pressing one tinsel is on this insulating barrier; And
After this tinsel of pressing, reduce the thickness of this tinsel.
6. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said barrier layer is a metal level, and the method that forms this barrier layer is included in this metal level of deposition on this rete.
7. the manufacture method of the line construction of wiring board according to claim 1, the method that it is characterized in that wherein forming this intaglio pattern comprises carries out laser ablation or plasma etching to this substrate.
8. the manufacture method of the line construction of wiring board according to claim 1, the flow process that it is characterized in that wherein forming this intaglio pattern is included on this outer surface and forms many local grooves that expose these insulating barriers, and the flow process that forms this electric conducting material is included in those grooves and forms a patterned conductive layer.
9. the manufacture method of the line construction of wiring board according to claim 1, is characterized in that wherein said substrate more comprises a line layer, and this line layer is positioned on the another side of this insulating barrier relative with this rete, and this insulating barrier covers this line layer.
10. the manufacture method of the line construction of wiring board according to claim 9, it is characterized in that wherein said substrate more comprises an internal layer circuit substrate, this insulating barrier and line layer all are configured on this internal layer circuit substrate, and this line layer is electrically connected this internal layer circuit substrate, the flow process that forms this intaglio pattern comprises the blind hole that forms at least one local this line layer of exposure, and the flow process that forms this electric conducting material is included in formation one conductive pole in this blind hole, wherein the adsorption strength between this line layer and described metal ion is less than the adsorption strength between this insulating barrier and described metal ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101101529A CN102137547B (en) | 2010-01-26 | 2010-01-26 | Manufacturing method of circuit structure of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101101529A CN102137547B (en) | 2010-01-26 | 2010-01-26 | Manufacturing method of circuit structure of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102137547A CN102137547A (en) | 2011-07-27 |
| CN102137547B true CN102137547B (en) | 2013-11-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101101529A Expired - Fee Related CN102137547B (en) | 2010-01-26 | 2010-01-26 | Manufacturing method of circuit structure of circuit board |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246817A (en) * | 1985-08-02 | 1993-09-21 | Shipley Company, Inc. | Method for manufacture of multilayer circuit board |
| CN101185384A (en) * | 2005-04-18 | 2008-05-21 | 精炼株式会社 | Transparent electrically conductive film and process for producing the same |
-
2010
- 2010-01-26 CN CN2010101101529A patent/CN102137547B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246817A (en) * | 1985-08-02 | 1993-09-21 | Shipley Company, Inc. | Method for manufacture of multilayer circuit board |
| CN101185384A (en) * | 2005-04-18 | 2008-05-21 | 精炼株式会社 | Transparent electrically conductive film and process for producing the same |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2007-109921A 2007.04.26 |
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| CN102137547A (en) | 2011-07-27 |
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Granted publication date: 20131120 Termination date: 20180126 |