CN102142268B - Control device and relevant control method thereof - Google Patents
Control device and relevant control method thereof Download PDFInfo
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- CN102142268B CN102142268B CN201010121046.0A CN201010121046A CN102142268B CN 102142268 B CN102142268 B CN 102142268B CN 201010121046 A CN201010121046 A CN 201010121046A CN 102142268 B CN102142268 B CN 102142268B
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Abstract
The invention relates to a control device which comprises a first delay circuit, a second delay circuit, a first control circuit, a third delay circuit and a second control circuit, wherein the first delay circuit is provided with a first retardation, and used for selectively delaying one of a first input clock or a second input clock according to a selection signal so as to generate an output clock to a storage device; the second delay circuit is used for delaying a second retardation for the selection signal so as to generate a second delay selection signal; the first control circuit is used for selectively accessing the storage device according to the second delay selection signal; the third delay circuit is used for delaying a third retardation for the selection signal so as to generate a third delay selection signal; and the second control circuit is used for selectively accessing the storage device according to the third delay selection signal. The invention also relates to a control method. The device and method disclosed by the invention have the advantages that the response time is fast, the problem that a clock suddenly sends signals is solved, and the speed of accessing a single-port FIFO (first in, first out) memory by a control circuit is increased.
Description
Technical field
The present invention relates to control device and its corresponding control methods technical field, more particularly, relate to control device and its corresponding control methods of a single port push-up storage.
Background technology
In an access system; one storage device; a for example single port first in first out (One-port FIFO) storer, can be assigned to the control circuit for example, with different clocks characteristic (different clock frequencies or work period) and carry out the action of access conventionally.Take this single port push-up storage as example, an I/O port of this single port push-up storage just must usually switch between different control circuits.But in the process of switching, for fear of the generation of clock burst signal (Glitch), the firmware (firmware) of traditional access system can be carried out a protection mechanism and guarantee can not produce burst signal.Further, when a first control circuit with one first clock is during just at this single port push-up storage of access, this firmware is wanted the circuit of this single port push-up storage of switch access (use), and the circuit of this single port push-up storage of access (use) is switched to a second control circuit from first control circuit.Wherein this first control circuit has one first and controls clock and this second control circuit and have one second and control clock, and now the tough cognition of traditional access system first is controlled this of this single port push-up storage of input clock and switched to this and second control clock.Then,, after this one specific delays time of firmware counting, just control this second control circuit and started this single port push-up storage of access.In other words, must this single port push-up storage of enough long guarantee received this of this specific delays time first control clock successful switch be this second control clock after, this second control circuit just starts this single port push-up storage of access to avoid producing the clock signal that happens suddenly.But, when this is first when controlling clock frequency that clock and this second control clock and being high-frequency, its cycle length relative minimizing, therefore this first is controlled clock and switches to this and second control required time of clock and also reduced.But if now this specific delays time still remains unchanged, this specific delays time just seems long and produces unnecessary time waste, and then has dragged slowly the speed of a control circuit access one single port push-up storage.Therefore, how this specific delays time is adjusted on adaptive ground has become the problem of a solution that access system is needed badly to improve the speed of a control circuit access one single port push-up storage.
Summary of the invention
The technical problem to be solved in the present invention is, for the above-mentioned defect of prior art, provides control device and its corresponding control methods of a single port push-up storage, the problem being faced to solve known techniques.
One of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of control device.This control device includes one first delay circuit, one second delay circuit, a first control circuit, one the 3rd delay circuit and a second control circuit.This first delay circuit has one first retardation, and is used for selecting signal one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device according to one.This second delay circuit is coupled to this first delay circuit, and is used for to this selection signal delay one second retardation to produce one second the delayed selection culture signal.This first control circuit operates in this first input clock and is coupled to this second delay circuit, and is used for carrying out this storage device of optionally access according to this second the delayed selection culture signal.The 3rd delay circuit is coupled to this first delay circuit, and is used for to this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal.This second control circuit operates in this second input clock and is coupled to the 3rd delay circuit, and is used for carrying out this storage device of optionally access according to the 3rd the delayed selection culture signal.
Control device of the present invention, wherein, when this second the delayed selection culture signal allows this this storage device of first control circuit access, the 3rd the delayed selection culture signal does not allow this this storage device of second control circuit access.
Control device of the present invention, wherein in this second retardation and the 3rd retardation, at least one is greater than this first retardation.
Control device of the present invention, wherein this second delay circuit includes:
Multiple the first specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the first specific delays unit includes at least one the first delay cell and one second delay cell, wherein this first delay cell operates under this first input clock, and this second delay cell operates under this second input clock.
Control device of the present invention, wherein the retardation summation of this first delay cell and this second delay cell equals this second retardation haply.
Control device of the present invention, wherein the 3rd delay circuit bag includes:
Multiple the second specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the second specific delays unit includes at least one the 3rd delay cell and one the 4th delay cell, wherein the 3rd delay cell operates under this first input clock, and the 4th delay cell operates under this second input clock; And
One phase inverter, is serially connected with a delay cell in the plurality of the second specific delays unit.
Control device of the present invention, wherein the retardation summation of the 3rd delay cell and the 4th delay cell equals the 3rd retardation haply.
Control device of the present invention, separately includes:
One selects circuit, be coupled to this first delay circuit, this second delay circuit, the 3rd delay circuit, this first control circuit and this second control circuit, be used for being controlled the one second control signal that signal and this second control circuit produce and producing this selection signal to this first delay circuit, this second delay circuit and the 3rd delay circuit according to produce one first by this first control circuit.
Control device of the present invention, wherein this second delay circuit, the 3rd delay circuit and this selection circuit are pure hardware circuit.
Control device of the present invention, wherein this selection circuit includes:
One first triggers (toggle) circuit, is controlled by this first input clock, is used for triggering one first according to this first control signal and triggers output signal;
One second trigger circuit, are controlled by this second input clock, are used for triggering one second according to this second control signal and trigger output signal; And
One logic gate, is coupled to these first trigger circuit and this second trigger circuit, is used for producing this selection signal according to this first triggering output signal and this second triggering output signal.
Control device of the present invention, wherein this logic gate is an XOR gate.
Two of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of control method.This control method includes the following step: according to one, select signal one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device; To this selection signal delay one second retardation to produce one second the delayed selection culture signal; According to this second the delayed selection culture signal, indicate optionally this storage device of access of a first control circuit; To this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal; And indicate optionally this storage device of access of a second control circuit according to the 3rd the delayed selection culture signal.
Control method of the present invention, wherein, when this second the delayed selection culture signal indicates this first control circuit to allow this storage device of access, the 3rd the delayed selection culture signal indicates this second control circuit not allow this storage device of access.
Control method of the present invention, wherein in this second retardation and the 3rd retardation, at least one is greater than this first retardation.
Control method of the present invention, separately includes:
According to one first control signal and one second, control signal and produce this selection signal.
Control method of the present invention, the step that wherein produces this selection signal according to this first control signal and this second control signal includes:
According to this first control signal, trigger one first and trigger output signal;
According to this second control signal, trigger one second and trigger output signal; And
According to this first triggering output signal and this second triggering output signal, produce this selection signal.
Implement control device of the present invention and control method thereof, there is following beneficial effect: the present invention can pure hardware circuit and do not needed to carry out implementation in addition by the mode of firmware, not only there is faster the reaction time (that is clock switching time), also overcome the problem of clock burst signal simultaneously, improved the speed of a control circuit access one single port push-up storage.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is an embodiment schematic diagram of a kind of control device of the present invention;
Fig. 2 be one of the present invention's one first delay circuit select signal, one first input clock, one second input clock with and the sequential chart of multiple signals;
Fig. 3 is the waveform sequential chart that one first of this control device of the present invention is controlled signal, one second control signal, one first triggering output signal, one second triggering output signal and this selection signal;
Fig. 4 is another embodiment schematic diagram of one first delay circuit of this control device of the present invention;
Fig. 5 is the embodiment process flow diagram according to a kind of control method of the present invention.
[primary clustering symbol description]
100 control device
101,201 first delay circuits
102 second delay circuits
103 first control circuits
104 the 3rd delay circuits
105 second control circuits
106 select circuit
107 storage devices
101a, 101b, 101c, 101d, 201a, 201b, 201c, 201d and door
101e, 101f, 101g, 101h, 201e, 201f, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b D type flip-flop
101i, 201g or door
101j phase inverter
1022 first delay cells
1024 second delay cells
1042 the 3rd delay cells
1044 the 4th delay cells
1062 first trigger circuit
1064 second trigger circuit
1066 logic gates
Embodiment
In the middle of instructions and follow-up claim, used some vocabulary to censure specific assembly.Person with usual knowledge in their respective areas should understand, and hardware manufacturer may be called same assembly with different nouns.This instructions and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but the difference in function is used as the criterion of distinguishing with assembly.In the whole text, in the middle of instructions and follow-up claims, be an open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this, therefore, if describe a first device in literary composition, be coupled to one second device, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device by other device or connection means.
Please refer to Fig. 1.Shown in Fig. 1 according to an embodiment schematic diagram of a kind of control device 100 of the present invention.Control device 100 includes one first delay circuit 101, one second delay circuit 102, a first control circuit 103, one the 3rd delay circuit 104, a second control circuit 105 and a selection circuit 106.
The first delay circuit 101 has one first retardation D1, is used for selecting signal Ss one of optionally to postpone in one first input clock C1 and one second input clock C2 to produce output clock Cout to storage device 107 according to one.
The second delay circuit 102 is coupled to the first delay circuit 101, is used for to selecting signal Ss to postpone one second retardation D2 to produce one second the delayed selection culture signal Ssd2.First control circuit 102 operates in the first input clock C1 and is coupled to the second delay circuit 102, is used for carrying out optionally accessing storing device 107 according to the second the delayed selection culture signal Ssd2.
The 3rd delay circuit 104 is coupled to the first delay circuit 101, is used for to selecting signal Ss to postpone one the 3rd retardation D3 to produce one the 3rd the delayed selection culture signal Ssd3.Second control circuit 105 operates in the second input clock C2 and is coupled to the 3rd delay circuit 104, is used for carrying out optionally accessing storing device 107 according to the 3rd the delayed selection culture signal Ssd3.
The first delay circuit 101 includes and door (And Gate) 101a, 101b, 101c, 101d, D type flip-flop (D Flip-Flop) 101e, 101f, 101g, 101h, one or door (Or Gate) 101i and a phase inverter 101j.D type flip-flop 101e, 101f are connected in series mutually, and being used for provides a retardation 1,5Ta according to the first input clock C1, and wherein Ta is the cycle of the first input clock C1.D type flip-flop 101g, 101h are connected in series mutually, and being used for provides a retardation 1,5Tb according to the second input clock C2, and wherein Tb is the cycle of the second input clock C2.Be used for receiving with an input end N1 of door 101a and select signal Ss, an output terminal N2 is coupled to an input end of D type flip-flop 101e.A positive output end N3 of D type flip-flop 101f is coupled to the input end with door 101c.N4 receives the first input clock C1 with another input end of door 101c.In addition, phase inverter 101j be coupled to input end N1 and and an input end N5 of door 101b between.Be coupled to a reversed-phase output of D type flip-flop 101f with another input end N6 of door 101b, be coupled to an input end of D type flip-flop 101g with an output terminal N7 of door 101b.A positive output end N8 of D type flip-flop 101h is coupled to the input end with door 101d.Receive the second input clock C2 with another input end N9 of door 101d.With door 101c with door 101d other output terminal N10, N11, be respectively coupled to or two input ends of door (Or Gate) 101i.Or the output terminal N12 of door 101i is used for exporting output clock Cout.The thin portion annexation that note that the first delay circuit 101 please refer to Fig. 1 of the present invention, at this, does not separately repeat.
Due to the structure of the first delay circuit 101, therefore produce the first control signal Sc1/ second from first control circuit 103/ second control circuit 105, control signal Sc2 to represent to want access (use) storage device 107, until storage device 107 is received the output clock Cout after change, altogether by the time delay of needs 1,5Ta+1,5Tb.Owing to usually can produce clock burst signal (Glitch) when switching clock; for fear of storage device 107, receive to there is the clock signal of clock burst signal and misoperation; for example, therefore utilize the first delay circuit 101 to postpone a period of time (1,5Ta+1,5Tb), input again storage device 107 after the stable clock signal after clock changes.The first delay circuit 101 shown in Fig. 1 is only an example embodiment, but not restriction of the present invention, those who are familiar with this art work as under instruction of the present invention, change the D type flip-flop number in the first delay circuit 101, and realize the first delay circuit 101 with various variation examples, for example can produce 2, the first delay circuit 101 of 5Ta+1,5Tb maybe can produce 2,5Ta+2,5Tb the first delay circuit 101 etc.
The second delay circuit 102 includes multiple the first specific delays unit, and its tandem connection is to provide respectively a retardation.In the present embodiment, the plurality of the first specific delays unit includes one first delay cell 1022 and one second delay cell 1024, wherein the first delay cell 1022 operates under the second input clock C2, and the second delay cell 1024 operates under the first input clock C1.The first delay cell 1022 includes D type flip-flop 1022a, 1022b, and its tandem connection is to provide a retardation 2Tb.The second delay cell 1024 includes D type flip-flop 1024a, 1024b, and its tandem connection is to provide a retardation 2Ta.Note that, the serial connection sequence of D type flip-flop 1022a, 1022b, 1024a, 1024b is only the use of explanation in the present embodiment, but not the present invention's restriction, the serial connection sequence of D type flip-flop 1022a, 1022b, 1024a, 1024b obtains arbitrarily and adjusts.In the present embodiment, the retardation summation of the first delay cell 1022 and the second delay cell 1024 equals the second retardation D2 haply, that is 2Ta+2Tb=D2.In other words, the second delay circuit 102 is used to provide retardation 2Ta+2Tb in selecting signal Ss, and the second the delayed selection culture signal Ssd2 producing after postponing is output in an output terminal N13 of D type flip-flop 1024b.
On the other hand, the 3rd delay circuit 104 includes multiple the second specific delays unit, and its tandem connection is to provide respectively a retardation.In the present embodiment, the plurality of the second specific delays unit includes one the 3rd delay cell 1042 and one the 4th delay cell 1044, wherein the 3rd delay cell 1042 operates under the first input clock C1, and the 4th delay cell 1044 operates under the second input clock C2.The 3rd delay cell 1042 includes D type flip-flop 1042a, 1042b, and its tandem connection is to provide a retardation 2Ta.The 4th delay cell 1044 includes D type flip-flop 1044a, 1044b, and its tandem connection is to provide a retardation 2Tb.Note that, the serial connection sequence of D type flip-flop 1042a, 1042b, 1044a, 1044b is only the use of explanation in the present embodiment, but not the present invention's restriction, the serial connection sequence of D type flip-flop 1042a, 1042b, 1044a, 1044b obtains arbitrarily and adjusts.In addition, the 3rd delay circuit 104 of the present invention separately includes a phase inverter 1046 and is coupled between input end N1 and an input end N14 of D type flip-flop 1042a with according to selecting signal Ss to produce an anti-phase selection signal Ssb.In the present embodiment, the retardation summation of the 3rd delay cell 1042 and the 4th delay cell 1044 equals the 3rd retardation D3 haply, that is 2Ta+2Tb=D3.In other words, the 3rd delay circuit 104 is used to provide retardation 2Ta+2Tb in anti-phase selection signal Ssb, and the 3rd the delayed selection culture signal Ssd3 producing after postponing is output in to an output terminal N15 of D type flip-flop 1044b.Note that the present invention does not limit the coupling mode of phase inverter 1046, in other words, as long as being serially connected with the 3rd delay cell 1042 and the 4th delay cell 1044 is category of the present invention place.For instance, phase inverter 1046 can also be coupled between the 4th delay cell 1044 and second control circuit 105.
In addition, the selection circuit 106 of the present embodiment includes one first triggering (toggle) circuit 1062, one second trigger circuit 1064 and a logic gate 1066.The first trigger circuit 1062 operate under the first input clock C1, are used for controlling signal Sc1 according to first and trigger one first triggering output signal St1.The second trigger circuit 1064 operate under the second input clock Sc2, are used for controlling signal Sc2 according to second and trigger one second triggering output signal St2.Logic gate 1066 is coupled to the first trigger circuit 1062 and the second trigger circuit 1064, is used for triggering output signal St2 according to the first triggering output signal St1 and second and produces selection signal Ss.In the present embodiment, logic gate 1066 is with in addition implementation of an XOR (ExclusiveOR) door.
Please refer to Fig. 2.Fig. 2 is the selection signal Ss of the embodiment of the present invention the first delay circuit 101, the first input clock C1, the second input clock C2, signal S1, signal S2, signal S3, signal S4, signal S5, signal S6, signal S7, signal S8, the sequential chart of signal S9, wherein signal S1 is and the signal of the output terminal N2 of door 101a, signal S2 is the signal of an output terminal N16 of D type flip-flop 101e, signal S3 is the signal of the output terminal N3 of D type flip-flop 101f, signal S4 is the signal of the reversed-phase output N17 of D type flip-flop 101f, signal S5 is and the signal of the output terminal N7 of door 101b, signal S6 is the signal of an output terminal N18 of D type flip-flop 101g, signal S7 is the signal of the output terminal N8 of D type flip-flop 101h, signal S8 is the signal of the reversed-phase output N19 of D type flip-flop 101h, signal S9 is the signal of the output terminal N5 of phase inverter 101j.
For side, more narrate spiritual place of the present invention, the present embodiment supposes that the first input clock C1 is synchronized with the second input clock C2.When selecting signal Ss to switch to a high voltage level in time T 1 from a low-voltage level, signal S9 and signal S5 also can switch to this low-voltage level from this high voltage level.Because D type flip-flop 101g is the D type flip-flop that trigger a rising edge, therefore the second input clock C2 can trigger D type flip-flop 101g to make signal S6 switch to this low-voltage level from this high voltage level in time T 2.Then,, because D type flip-flop 101h is the D type flip-flop of a decline edge-triggered, therefore the second input clock C2 can trigger D type flip-flop 101h to make signal S7 switch to this low-voltage level from this high voltage level in time T 3.Meanwhile, the signal S8 of D type flip-flop 101h can switch to this high voltage level from this low-voltage level, and then makes signal S1 switch to this high voltage level from this low-voltage level.In like manner, the first input clock C1 can trigger D type flip-flop 101e (D type flip-flop 101e is the D type flip-flop that trigger a rising edge) to make signal S2 switch to this high voltage level from this low-voltage level in time T 4.Then, the first input clock C1 can trigger D type flip-flop 101f (D type flip-flop 101f is the D type flip-flop of a decline edge-triggered) to make signal S3 switch to this high voltage level from this low-voltage level in time T 5.Therefore, after time T 5, with the output signal of door 101d will be this low-voltage level, and with the output signal of door 101c will be the first input clock C1.In other words, after time T 5, output clock Cout (even also door 101i output terminal) will switch to the first input clock C1 from the second input clock C2.
On the other hand, please refer again to Fig. 2, when selecting signal Ss to switch to this low-voltage level in time T 6 from this high voltage level (, wish switches to the second input clock C2 by output clock Cout from the first input clock C1), signal S1 also can switch to this low-voltage level from this high voltage level.Because D type flip-flop 101e is the D type flip-flop that trigger a rising edge, therefore the first input clock C1 can trigger D type flip-flop 101e to make signal S2 switch to this low-voltage level from this high voltage level in time T 7.Then,, because D type flip-flop 101f is the D type flip-flop of a decline edge-triggered, therefore the first input clock C1 can trigger D type flip-flop 101f to make signal S3 switch to this low-voltage level from this high voltage level in time T 8.Meanwhile, the signal S4 of D type flip-flop 101f can switch to this high voltage level from this low-voltage level, and then makes signal S5 switch to this high voltage level from this low-voltage level.In like manner, the second input clock C2 can trigger D type flip-flop 101g to make signal S6 switch to this high voltage level from this low-voltage level in time T 9.Then, the second input clock C2 can trigger D type flip-flop 101h to make signal S7 switch to this high voltage level from this low-voltage level in time T 10.Therefore, after time T 10, with the output signal of door 101c will be this low-voltage level, and with the output signal of door 101d will be the second input clock C2.In other words, after time T 10, output clock Cout (even also door 101i output terminal) will switch to the second input clock C2 from the first input clock C1.
Further, delay cell that D type flip-flop 101g and 101h form is the longest can postpone 1 to signal S5,5Tb, and the delay cell that D type flip-flop 101e and 101f form the longlyest can postpone 1 to signal S1,5Ta, therefore the first retardation D1 of the first delay circuit 101 the longlyest have 1, the time delay of 5Ta+1,5Tb.In other words, when selecting signal Ss to switch to this high voltage level from this low-voltage level, output clock Cout can not exceed 1 at most, will switch to the first input clock C1 the time delay of 5Ta+1,5Tb from the second input clock C2.Otherwise when selecting signal Ss to switch to this low-voltage level from this high voltage level, output clock Cout can not exceed 1 at most, will switch to the second input clock C2 the time delay of 5Ta+1,5Tb from the first input clock C1.Therefore, when selecting signal Ss to switch to this high voltage level from this low-voltage level, as long as first control circuit 103 can just carry out access to storage device 107 after the time delay that exceedes the first delay circuit 101 (1,5Ta+1,5Tb), storage device 107 (that is output terminal N12) just can be avoided because of the clock misoperation that the generation of signal (Glitch) causes that happens suddenly.Note that, those who are familiar with this art, under instruction of the present invention, when changing number, the type (flip-flop of D type flip-flop or other type) of flip-flop in the first delay circuit 101 and trigger aspect (trigger rising edge or trigger drop edge) to change the time delay of the first delay circuit 101.
Therefore, be directed to and select signal Ss, second delay circuit 102 of the present embodiment just provides the time delay of 2Ta+2Tb, produces the second the delayed selection culture signal Ssd2.And first control circuit 103 will carry out accessing storing device 107 according to the second the delayed selection culture signal Ssd2.From Fig. 1, can learn, D type flip-flop 1022a in the second delay circuit 102, the time delay that 1022b provides 2Tb, and D type flip- flop 1024a, 1024b provide the time delay of 2Ta, therefore the second delay circuit 102 provides the time delay of 2Ta+2Tb altogether.
On the other hand, be directed to and select signal Ss, the 3rd delay circuit 104 also provides the time delay of 2Ta+2Tb, produces the 3rd the delayed selection culture signal Ssd3, and its reason is as the second delay circuit 102, therefore separately do not repeat.Please note, the present invention is not limited to above-mentioned embodiment, as long as the time delay that provide the time delay that the second delay circuit 102 and the 3rd delay circuit 104 provide than the first delay circuit 101 long circuit combines and is category of the present invention place, that is, those who are familiar with this art, under instruction of the present invention, when must changing number, the type of flip-flop in the second delay circuit 102 or the 3rd delay circuit 104 and triggering aspect to change the time delay of the first delay circuit 101.Therefore, passed through the first retardation D1 (that is 2Ta+2Tb), the second the delayed selection culture signal Ssd2 will switch to this high voltage level to allow first control circuit 103 accessing storing devices 107 from this low-voltage level.Please note, this field has knows that the knowledgeable is reading after above-mentioned disclosed technology contents conventionally, should understand the running of control device 100 correspondences, that is the running when selecting signal Ss to switch to a low-voltage level from a high voltage level, it also has above-mentioned described advantage, therefore separately do not repeat at this.
Note that the second delay circuit 102, the 3rd delay circuit 104 of the present embodiment control device 100 and select circuit 106 for pure hardware circuit.In other words, in one embodiment, control device 100 can be not be controlled first control circuit 103 or second control circuit 105 with accessing storing device 107 by the mode of firmware (Firmware).Therefore,, when first control circuit 103 needs accessing storing device 107, first control circuit 103 will produce the first control signal Sc1 and select signal Ss to selecting circuit 106 to produce.In like manner, when second control circuit 105 needs accessing storing device 107, second control circuit 105 will produce the second control signal Sc2 and select signal Ss to selecting circuit 106 to produce.For instance, suppose when second control circuit 105 is just at accessing storing device 107, and first control circuit 103 is while wanting accessing storing device 107, first control circuit 103 will first produce the first control signal Sc1 to the first trigger circuit 1062, wherein the first control signal Sc1 is a pulse wave signal, as shown in Figure 3.
Fig. 3 is that first of embodiment of the present invention control device 100 is controlled signal Sc1, the second control signal Sc2, first triggers output signal St1, second and triggers output signal St2 and select a waveform sequential chart of signal Ss.When first control circuit 103 is when time T o produces the first control signal Sc1, the first trigger circuit 1062 will be triggered and in time T x, the first triggering output signal St1 be switched to a high voltage level from a low-voltage level by the first control signal Sc1.Then, logic gate 1066 (that is this XOR gate) will trigger output signal St2 according to the first triggering output signal St1 and second and produce selection signal Ss.Because the second voltage quasi position that triggers output signal St2 is now this low-voltage level, therefore logic gate 1066 will switch to this high voltage level by selection signal Ss from this low-voltage level in time T b.The person of connecing, the running that the first delay circuit 101 will be carried out as shown in Figure 2 switches to the first input clock C1 by output clock Cout from the second input clock C2.The person of connecing, through after the first retardation D1 (that is 2Ta+2Tb), first control circuit 103 has just been allowed to accessing storing device 107.
Otherwise, when first control circuit 103 is just at accessing storing device 107, and second control circuit 105 is while wanting accessing storing device 107, second control circuit 105 will first produce the second control signal Sc2 to the second trigger circuit 1064, wherein the second control signal Sc2 is also a pulse wave signal, as shown in Figure 3.When second control circuit 105 is when time T o ' produces the second control signal Sc2, the second trigger circuit 1064 will be triggered and in time T y, the second triggering output signal St2 be switched to a high voltage level from a low-voltage level by the second control signal Sc2.Owing to now first triggering output signal St1 and the second voltage quasi position that triggers output signal St2 is this high voltage level, therefore logic gate 1066 will switch to this low-voltage level by selection signal Ss from this high voltage level in time T y.In like manner, the running that the first delay circuit 101 will be carried out as shown in Figure 2 switches to the second input clock C2 by output clock Cout from the first input clock C1.The person of connecing, through after the first retardation D1 (that is 2Ta+2Tb), second control circuit 105 has just been allowed to accessing storing device 107.Therefore, by selecting the first trigger circuit 1062 in circuit 106, the second trigger circuit 1064 and logic gate 1066 running of collocation mutually, first control circuit 103 and second control circuit 105 just can not need to carry out optionally accessing storing device 107 according to the control of firmware.Therefore, compared to traditional storage device access system, control device 100 of the present invention not only has faster the reaction time (that is clock switching time), has also overcome the problem of clock burst signal simultaneously.
Please refer to Fig. 4.Another embodiment schematic diagram that Figure 4 shows that the first delay circuit 101 of control device 100 of the present invention, this another embodiment indicates with label 201.The first delay circuit 201 includes and door 201a, 201b, 201c, 201d, D type flip-flop 201e, 201f, one or door 201g and a phase inverter 201h.D type flip-flop 101e provides a retardation 0,5Ta ' according to one first input clock C1 ', and wherein Ta ' is the cycle of the first input clock C1 '.D type flip-flop 201f is used for providing a retardation 0,5Tb ' according to one second input clock C2 ', and wherein Tb ' is the cycle of the second input clock C2 '.Be used for receiving a selection signal Ss ' with an input end N1 ' of door 201a, an output terminal N2 ' is coupled to an input end of D type flip-flop 201e.A positive output end N3 ' of D type flip-flop 201e is coupled to the input end with door 201c, receives the first input clock C1 ' with another input end of door 201c N4 '.In addition, phase inverter 201h be coupled to input end N1 ' and and an input end N5 ' of door 201b between.Be coupled to a reversed-phase output of D type flip-flop 201e with another input end N6 ' of door 201b, be coupled to an input end of D type flip-flop 201f with an output terminal N7 ' of door 201b.A positive output end N8 ' of D type flip-flop 201f is coupled to the input end with door 201d.Receive the second input clock C2 ' with another input end N9 ' of door 201d.With door 201c with door 201d, respectively output terminal N10 ', N11 ' are respectively coupled to or two input ends of door 201g.Or the output terminal N12 ' of door 201g is used for exporting output clock Cout '.With reference to about the running of the first delay circuit 101, this field have conventionally know that the knowledgeable should understand the first delay circuit 201 and the longlyest has 0, the time delay of 5Ta '+0,5Tb '.In other words, when selecting signal Ss ' to switch to this high voltage level from this low-voltage level, output clock Cout ' can not exceed 0 at most, will switch to the first input clock C1 ' time delay of 5Ta '+0,5Tb ' from the second input clock C2 '.Otherwise when selecting signal Ss ' to switch to this low-voltage level from this high voltage level, output clock Cout ' can not exceed 0 at most, will switch to the second input clock C2 ' time delay of 5Ta '+0,5Tb ' from the first input clock C1 '.Therefore, to utilize the first delay circuit 201 to form the embodiment of control device 100, when selecting signal Ss ' to switch to this high voltage level from this low-voltage level, as long as first control circuit 103 can be exceeding 0, just storage device 107 is carried out to access after the time delay of 5Ta '+0,5Tb ', storage device 107 (that is output terminal N12) just can avoid clock to happen suddenly problem that signal (Glitch) causes.In other words, in this embodiment, if by the 3rd retardation D3 of the second retardation D2 of the second delay circuit 102 and the 3rd delay circuit 103 be set as than 0,5Ta '+0,5Tb ' carrys out longly the words of (for example 1Ta '+1Tb ') and just can avoid clock to happen suddenly the generation of signal.
Please refer to Fig. 5.Figure 5 shows that the embodiment process flow diagram according to a kind of control method 500 of the present invention.In order more to clearly demonstrate spiritual place of the present invention, control method 500 is carried out implementation in addition with the embodiment control device 100 of Fig. 1, but the scope that the embodiment providing is not contained in order to limit the present invention.In addition, if can reach substantially identical result, do not need necessarily according to the step order in the flow process shown in Fig. 5, to carry out, and the step shown in Fig. 5 not necessarily will carry out continuously, that is other step also can be inserted wherein.Control method 500 includes following step:
Step 501: produce first control signal Sc1 and second control signal Sc2 at least one of them;
Step 502: control signal Sc2 according to the first control signal Sc1 or second and trigger respectively the first triggering output signal St1 and the second triggering output signal St2;
Step 503: trigger output signal St2 according to the first triggering output signal St1 and second and produce selection signal Ss, skip to step 504;
Step 504: according to selecting signal Ss to postponing one first retardation D1 to produce output clock Cout to storage device 107 one of in the first input clock C1 and the second input clock C2;
Step 505: to selecting signal Ss to postpone the second retardation D2 to produce the second the delayed selection culture signal Ssd2;
Step 506: carry out optionally accessing storing device 107 according to the second the delayed selection culture signal Ssd2;
Step 507: to selecting signal Ss delay control three retardation D3 to produce the 3rd the delayed selection culture signal Ssd3;
Step 508: carry out optionally accessing storing device 107 according to the 3rd the delayed selection culture signal Ssd3.
In step 501, when a control circuit wish in first control circuit 103 and second control circuit 105 is carried out access to storage device 107, this control circuit will produce control signal to the first trigger circuit 1062 or the second trigger circuit 1064.For example, when first control circuit 103 wishs are carried out access to storage device 107, first control circuit 103 will produce control signal Sc1 to the first trigger circuit 1062.When second control circuit 105 wishs are carried out access to storage device 107, second control circuit 105 will produce control signal Sc2 to the second trigger circuit 1064.Then, be subject to the trigger circuit that this control signal triggers and the voltage quasi position of its output signal (first triggers output signal St1 or second triggers output signal St2) will be switched to (step 502).Then,, in step 503, logic gate 1066 will trigger output signal St2 according to the first triggering output signal St1 and second and produce selection signal Ss.Correspondingly, select signal Ss can express which circuit wish in first control circuit 103 or second control circuit 105 storage device 107 is carried out to access.With reference to the operation narration about control device 100, selection signal Ss can be through three delay circuits (that is the first delay circuit 101 (step 504), the second delay circuit 102 (step 505) and the 3rd delay circuit 104 (step 507)) produce respectively three output signals (that is output clock Cout, the second the delayed selection culture signal Ssd2 and the 3rd the delayed selection culture signal Ssd3), wherein (D2 time delay of the second delay circuit 102 and the 3rd delay circuit 104, D3) be greater than time delay (D1) of the first delay circuit 101.Then,, if output clock Cout is the first input clock C1, first control circuit 103 will, according to the indication of the second the delayed selection culture signal Ssd2, start accessing storing device 107 (step 506).Otherwise if output clock Cout is the second input clock C2, second control circuit 105 will, according to the indication of the 3rd the delayed selection culture signal Ssd3, start accessing storing device 107 (step 508).Note that, control device 100 is according to selecting signal Ss to produce three output signals (that is output clock Cout, the second the delayed selection culture signal Ssd2 and the 3rd the delayed selection culture signal Ssd3), wherein the second the delayed selection culture signal Ssd2 is used to refer to first control circuit 103 and when starts accessing storing device 107, the three the delayed selection culture signal Ssd3 and be used to refer to second control circuit 105 and when start accessing storing device 107.Under normal operation, when the second the delayed selection culture signal Ssd2 indication first control circuit 103 accessing storing device 107, the 3rd the delayed selection culture signal Ssd3 indicates second control circuit 105 storage device 107 not to be carried out to access, and vice versa.Due to when first control circuit 103 or second control circuit 105 start accessing storing device 107, corresponding input clock has been transferred into storage device 107 in early, therefore storage device 107 just can avoid clock to happen suddenly problem that signal causes.
In sum, compared to traditional storage device access system, control device 100 of the present invention with and control method 500 can pure hardware circuit and do not need to carry out implementation in addition by the mode of firmware, this measure not only has faster the reaction time (that is clock switching time), has also overcome the problem of clock burst signal simultaneously.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (11)
1. a control device, is characterized in that, includes:
One first delay circuit, has one first retardation, is used for selecting signal one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device according to one;
One second delay circuit, is coupled to this first delay circuit, is used for to this selection signal delay one second retardation to produce one second the delayed selection culture signal;
One first control circuit, operates in this first input clock and is coupled to this second delay circuit, is used for carrying out this storage device of optionally access according to this second the delayed selection culture signal;
One the 3rd delay circuit, is coupled to this first delay circuit, is used for to this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal; And
One second control circuit, operates in this second input clock and is coupled to the 3rd delay circuit, is used for carrying out this storage device of optionally access according to the 3rd the delayed selection culture signal;
Further, this second retardation, the 3rd retardation are greater than this first retardation; This first retardation, the second retardation and the 3rd retardation are all relevant with the clock period of the second input clock to the clock period of the first input clock.
2. control device according to claim 1, is characterized in that, wherein, when this second the delayed selection culture signal allows this this storage device of first control circuit access, the 3rd the delayed selection culture signal does not allow this this storage device of second control circuit access.
3. control device according to claim 1, is characterized in that, wherein this second delay circuit includes:
Multiple the first specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the first specific delays unit includes at least one the first delay cell and one second delay cell, wherein this first delay cell operates under this first input clock, and this second delay cell operates under this second input clock.
4. control device according to claim 3, is characterized in that, wherein the retardation summation of this first delay cell and this second delay cell equals this second retardation.
5. control device according to claim 1, is characterized in that, wherein the 3rd delay circuit includes:
Multiple the second specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the second specific delays unit includes at least one the 3rd delay cell and one the 4th delay cell, wherein the 3rd delay cell operates under this first input clock, and the 4th delay cell operates under this second input clock; And
One phase inverter, is serially connected with a delay cell in the plurality of the second specific delays unit.
6. control device according to claim 5, is characterized in that, wherein the retardation summation of the 3rd delay cell and the 4th delay cell equals the 3rd retardation.
7. control device according to claim 1, is characterized in that, separately includes:
One selects circuit, be coupled to this first delay circuit, this second delay circuit, the 3rd delay circuit, this first control circuit and this second control circuit, be used for being controlled the one second control signal that signal and this second control circuit produce and producing this selection signal to this first delay circuit, this second delay circuit and the 3rd delay circuit according to produce one first by this first control circuit.
8. control device according to claim 7, is characterized in that, wherein this second delay circuit, the 3rd delay circuit and this selection circuit are pure hardware circuit.
9. control device according to claim 7, is characterized in that, wherein this selection circuit includes:
One first trigger circuit, are controlled by this first input clock, are used for triggering one first according to this first control signal and trigger output signal;
One second trigger circuit, are controlled by this second input clock, are used for triggering one second according to this second control signal and trigger output signal; And
One logic gate, is coupled to these first trigger circuit and this second trigger circuit, is used for producing this selection signal according to this first triggering output signal and this second triggering output signal.
10. control device according to claim 9, is characterized in that, wherein this logic gate is an XOR gate.
11. 1 kinds of control methods, is characterized in that, include:
According to one, select signal and one first retardation one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device;
To this selection signal delay one second retardation to produce one second the delayed selection culture signal;
According to this second the delayed selection culture signal, operate in optionally this storage device of access of first control circuit of the first input clock;
To this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal; And
According to the 3rd the delayed selection culture signal, operate in optionally this storage device of access of second control circuit of the second input clock;
Further, this second retardation, the 3rd retardation are greater than this first retardation; This first retardation, the second retardation and the 3rd retardation are all relevant with the clock period of the second input clock to the clock period of the first input clock.
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| CN1106560A (en) * | 1992-09-29 | 1995-08-09 | 奇特尔公司 | Fault tolerant memory system |
| CN1487669A (en) * | 2002-10-05 | 2004-04-07 | ���ǵ�����ʽ���� | Time-delay locking loop circuit for internally correcting dutyratio and method for correcting duty cycle thereof |
| CN1941165A (en) * | 2005-09-29 | 2007-04-04 | 海力士半导体有限公司 | Delay locked loop circuit |
| US20070139085A1 (en) * | 2005-10-10 | 2007-06-21 | Stmicroelectronics (Research & Development) Limited | Fast buffer pointer across clock domains |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1106560A (en) * | 1992-09-29 | 1995-08-09 | 奇特尔公司 | Fault tolerant memory system |
| CN1487669A (en) * | 2002-10-05 | 2004-04-07 | ���ǵ�����ʽ���� | Time-delay locking loop circuit for internally correcting dutyratio and method for correcting duty cycle thereof |
| CN1941165A (en) * | 2005-09-29 | 2007-04-04 | 海力士半导体有限公司 | Delay locked loop circuit |
| US20070139085A1 (en) * | 2005-10-10 | 2007-06-21 | Stmicroelectronics (Research & Development) Limited | Fast buffer pointer across clock domains |
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