CN102142279A - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
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- CN102142279A CN102142279A CN2011100212196A CN201110021219A CN102142279A CN 102142279 A CN102142279 A CN 102142279A CN 2011100212196 A CN2011100212196 A CN 2011100212196A CN 201110021219 A CN201110021219 A CN 201110021219A CN 102142279 A CN102142279 A CN 102142279A
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Abstract
The present invention provides a semiconductor storage device, wherein the resolution for data readout does not reduce even in verification and a stable readout action can be performed even when the power supply voltage is reduced. The readout circuit (13) of the invention comprises: a current voltage transform circuit (20) for transforming cell current (Icell) of a memory cell (MC) into voltage data (Vdata), and a readout amplifier (30) for comparing the voltage data (Vdata) with a reference voltage (Vref). The current voltage transform circuit (20) is configured to comprise a variable load resistance connected with the memory cell (MC) through a bit line ( BLj). The variable load resistance is configured to comprise a P channel type MOS transistor (T11, T14, T17) used as a load resistance, and a P channel type MOS transistor (T13, T16, T19) forming a switch circuit.
Description
Technical field
The present invention relates to semiconductor storage, particularly relate to a kind ofly, carry out the semiconductor storage of reading the data of being stored in the memory cell by comparing with corresponding data voltage of the cell current of memory cell and given reference voltage.
Background technology
In recent years, electrically programmable erasable nonvolatile memory (EEPROM) has obtained using widely in electronic equipments such as mobile phone and digital still video camera.EEPROM is equipped with the memory cell with floating grid.So, according to whether having accumulated electric charge on the floating grid, the data that two values or two values are above are recorded in the memory cell, the variation of the electric current that whether flows through between source electrode and drain electrode according to the existence of the electric charge that depends on floating grid, sense data from memory cell.
In this case, the sensing circuit that is arranged among the EEPORM is transformed to data voltage by the cell current that will flow in the memory cell, this data voltage and given reference voltage are compared, carry out judgement the data (" 0 ", " 1 ") of being stored in the memory cell.
Fig. 9 is the circuit diagram of the sensing circuit of above-mentioned EEPORM.This sensing circuit is made of current-voltage conversion circuit 1 (pre-sensor amplifier) and sensor amplifier 2 (primary sense amplifier).Current-voltage conversion circuit 1 is by applying supply voltage Vdd and grid is formed with the P channel type MOS transistor T6 that drain electrode is connected (diode-type connection) jointly to source electrode, and the bit line BL on draining via this is connected with the drain electrode of memory cell MC.The cell current Icell of memory cell MC flows to bit line BL, and by current-voltage conversion circuit 1 it is transformed to data voltage Vdata.
The common differential amplifier that the difference of sensor amplifier 2 pairs of data voltage Vdata and reference voltage V ref is amplified.Sensor amplifier 2 is by forming differential right N channel type MOS transistor T1, T2; Be connected in series respectively with MOS transistor T1, T2 and form P channel type MOS transistor T3, the T4 of current mirror; And the N channel type MOS transistor T5 that is connected with the common source of MOS transistor T1, T2 constitutes.
On the common source of MOS transistor T3, T4, apply supply voltage Vdd.On the grid of MOS transistor T1, apply data voltage Vdata from current-voltage conversion circuit 1.On the grid of MOS transistor T2, apply reference voltage V ref.On the grid of MOS transistor T5, apply to read and enable signal SEN.
Below the action of this sensing circuit will be described based on Fig. 9 and Figure 10.In this case, with source electrode line SL ground connection, and on bit line BL, apply read-out voltage.So, if the voltage of word line (word line) WL rise to high level (for example, Vdd), then with storer MC in the corresponding cell current Icell of data that stored can flow.Usually, cell current Icell is the value of 0～tens μ A level.For memory cell MC is the situation of data " 0 " (write state), cell current Icell is smaller value (near the value of minimum value), for memory cell MC is the situation of data " 1 " (erase status), and cell current Icell is big in comparison value (near peaked value).Current-voltage conversion circuit 1 is transformed to voltage data Vdata with this cell current Icell.
Afterwards, if read enable signal SEN rise to high level (for example, Vdd), then MOS transistor T5 conducting, sensor amplifier 2 becomes state of activation.Thus, sensor amplifier 2 is carried out the judgement to the data (" 0 ", " 1 ") of being stored among the memory cell MC by voltage data Vdata and reference voltage V ref are compared.
Figure 10 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.With Vdata-Icell curve and reference voltage V ref (the cell current Icell that=Vref1-3) intersection point is corresponding (=Iref1-3) be the cell current threshold value.That is, if the cell current Icell of memory cell MC is littler than the cell current threshold value that sets, be " 0 " then with data judging, if bigger than cell current threshold value, would be " 1 " then with data judging.
In addition, the input action voltage range of sensor amplifier 2 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax.
In this case, be expressed as: Vmin=Vt (T1)+Vds (T5), Vmax=Vdd-Vds (T3)+Vt (T1).Vt (T1) is the threshold value of MOS transistor T1, T2, and Vds (T5) is a voltage between the source drain of MOS transistor T5, and Vds (T3) is a voltage (the voltage sloping portion of diode) between the source drain of MOS transistor T3.
Therefore, reference voltage V ref needs to fall in this input action voltage range at least.As shown in figure 10, under the situation of reading usually, be Iref1 with the cell current threshold setting, corresponding therewith, reference voltage V ref is set at the center of input action voltage range or near the Vref1 it.
Usually, in EEPROM, has the decision-making function that writes data that is called as checking (verify).In checking, there are these two kinds of erase verification (ERASE checking) and program verifications.In erase verification, judge the data of whether having wiped memory cell MC, that is, whether the data of being stored among the determine memory unit MC are 1.In this case, be for the strict condition of data " 1 " with the cell current threshold setting, that is, be set at the Iref2 bigger than Iref1.Follow therewith, reference voltage V ref is changed to the Vref2 lower than Vref1.This is for considering the discrete of cell current Icell and over time, and the action of EEPROM is compensated.
On the other hand, in program verification, judge in memory cell MC, whether correctly to have write data " 0 ".In this case, be for the strict condition of data " 0 " with the cell current threshold setting, that is, be set at the Iref3 littler than Iref1.Follow therewith, reference voltage V ref is changed to the Vref3 higher than Vref1.
Patent documentation 1: TOHKEMY 2008-140431 communique
Summary of the invention
As above-mentioned, in existing sensing circuit, the cell current threshold value when verifying in order to change, ref changes to reference voltage V.Thus, the reference voltage V ref3 of program verification approaches the upper voltage limit Vmax of the input action voltage range of sensor amplifier 2, and the reference voltage V ref2 of erase verification approaches the lower limit Vmin of input action voltage range.Because the setting of cell current threshold value, the reference voltage V ref2 in the time of may verifying, Vref3 are not included into the situation of input action voltage range.Thus, the resolution characteristic that data are read might reduce, and the misoperation of perhaps reading might produce.
Especially, if supply voltage Vdd step-down is the degree such as 1.8V, then because the input action voltage range of sensor amplifier 2 becomes the degree of 0.8V-1.6V very narrowly, reference voltage V ref2, Vref3 during with checking include this input action voltage range in and will become more and more difficult.
Therefore, semiconductor storage of the present invention has: bit line; Memory cell, it is connected with described bit line, can carry out writing and reading of data in the mode of electricity, and makes with the corresponding cell current of these data mobile on described bit line; Current-voltage conversion circuit, it is connected with described memory cell via described bit line, and the described cell current that is used for flowing on described bit line is transformed to voltage data; And sensor amplifier, it is used for described voltage data and reference voltage are compared, and wherein, constituting of described current-voltage conversion circuit comprises: the variable load resistance that is connected with described memory cell via described bit line.
(invention effect)
According to semiconductor storage of the present invention, because constituting of described current-voltage conversion circuit comprises variable resistor, when the cell current threshold value is changed, by variable-resistance resistance value is changed, roughly the center change reference voltage from the input action voltage range of sensor amplifier becomes unnecessary.Thus, even when checking, the resolution characteristic that data are read can step-down yet.
Especially, even, also can carry out the stable action of reading owing to the reduction of supply voltage makes the input action voltage range of sensor amplifier narrow down.
Description of drawings
Fig. 1 is the whole skeleton diagram of the semiconductor storage of first embodiment of the present invention.
Fig. 2 is the sectional view of memory cell of the semiconductor storage of first embodiment of the present invention.
Fig. 3 is the circuit diagram of sensing circuit of the semiconductor storage of first embodiment of the present invention.
Fig. 4 is the circuit diagram of another sensing circuit of the semiconductor storage of first embodiment of the present invention.
Fig. 5 is the action timing diagram of the semiconductor storage of first embodiment of the present invention.
Fig. 6 is the figure of characteristic of sensing circuit of the semiconductor storage of explanation first embodiment of the present invention.
Fig. 7 is the circuit diagram of sensing circuit of the semiconductor storage of second embodiment of the present invention.
Fig. 8 is the figure of characteristic of sensing circuit of the semiconductor storage of explanation second embodiment of the present invention.
Fig. 9 is the circuit diagram of the sensing circuit of conventional semiconductor memory storage.
Figure 10 is the figure that is used to illustrate the sensing circuit of conventional semiconductor memory storage.
(symbol description)
10 memory areas
11 column decoders
12 row decoders
13 sensing circuits
14 write circuits
15 control circuits
20,20A current-voltage conversion circuit
30 sensor amplifiers
100 semiconductor storages
101 semiconductor substrates
105 gate insulating films
109 floating grids
The 109a jut
110 tunnel insulator films
112 control grids
113 drain electrodes
114 source electrodes
115 raceway grooves
Embodiment
The semiconductor storage 100 of first embodiment of the present invention will be described based on accompanying drawing.According to present embodiment, the EEPROM as serial input and output type describes with semiconductor storage 100.
(integral body of semiconductor storage constitutes)
Fig. 1 is the skeleton diagram of semiconductor storage 100.As shown in the figure, in memory array area 10, a plurality of bit line BL0～BLn extend on the Y direction, and a plurality of word line WL0～WLm, multiple source polar curve SL0～SLm extend on the directions X vertical with the Y direction.Be provided with a plurality of memory cell MC accordingly with each point of crossing of a plurality of bit line BL0～BLn and a plurality of word line WL0～WLm.
In addition, be adjacent to be provided with based on column address signal with memory array area 10 and from a plurality of bit line BL0～BLn, select the column decoder 11 of a bit line and the row decoder 12 of from a plurality of word line WL0～WLm, selecting a word line based on row address signal.By determining column address signal and row address signal, select a memory cell MC.
And, be provided with the sensing circuit 13 that reads out the data of the memory cell MC that in column decoder 11 selected bit line BLj, occurs via data line DL.In this case, sensing circuit 13 by will be stable benchmark voltage Vref compare with the data voltage Vdata that the cell current Icell that is flowed among the selected memory cell MC is carried out behind the voltage transformation, carry out the judgement of data " 0 ", " 1 ".
In addition, be provided with the write circuit 14 that selected memory cell MC execution data is write via column decoder 11 selected bit line BLj.In addition, be provided with the control circuit 15 that comes each sequence that writes, reads, wipes of control store unit MC based on various control signals.
(formation of memory cell)
The concrete formation example of memory cell MC is described with reference to Fig. 2.This memory cell MC is the splitting bar polar form, and is formed with raceway groove 115 between drain electrode 113 that forms separating predetermined distance on the semiconductor substrate 101 and the source electrode 114.Be formed with the floating grid of expanding to the part of source electrode 114 on the part of raceway groove 115 by gate insulating film 105 109.Cover the top and the sidepiece of floating grid 109 by tunnel insulator film 110, and be formed with the control grid of on the part of drain electrode 113, expanding 112.
Next the action of the memory cell MC of splitting bar polar form will be described.At first, when writing data " 0 ", on control grid 112 and source electrode 114, (for example apply high voltage, on control grid 112 is 2V, be 12V on source region 114) because electric current flows in raceway groove 115, inject thermoelectron and make its accumulation to floating grid 109.
In addition, when wiping the data " 0 " that write (, when data " 0 " are rewritten as " 1 "), by draining 113 and source electrode 114 ground connection and apply high voltage (for example 15V) on the grid 112, the electronics of being accumulated in the floating grid 109 is retracted to control grid 112 as Fowler-Nordheim tunnel current (hereinafter referred to as the FN tunnel current) in control.Owing to be formed with jut 109a on the top of floating grid 109, electric field is concentrated here, can flow through the FN tunnel current under low voltage.
In addition, when the data that readout memory unit MC is stored, in control grid 112 and drain electrode 113, apply the voltage (for example, being 3V, is 1V) of regulation on control grid 112 in drain electrode 113.So, with the quantity of electric charge of the electronics of being accumulated in the floating grid 109 accordingly, between source drain, flow through cell current Icell.Under the situation that writes data " 0 ", the threshold value of memory cell MC uprises, and cell current Icell diminishes, and under the situation that writes data " 1 " (when wiping), the threshold value step-down of memory cell MC, cell current Icell become big.
(formation of sensing circuit)
Next, based on Fig. 3 formation as the sensing circuit 13 of feature of the present invention is described.Constituting of sensing circuit 13 comprises: the N channel type MOS transistor T20 that current-voltage conversion circuit 20 (pre-sensor amplifier), sensor amplifier 30 (primary sense amplifier) and circuitry cuts are used.
Constituting of current-voltage conversion circuit 20 comprises: as P channel type MOS transistor T11, T14, the T17 of pull-up resistor and P channel type MOS transistor T13, T16, the T19 that constitutes on-off circuit.
In this case, on the source electrode of MOS transistor T11, apply supply voltage Vdd.MOS transistor T11 is connected with voltage data line 21 via MOS transistor T13.The grid of MOS transistor T11 is connected with voltage data line 21.On the grid of MOS transistor T13, apply pull-up resistor and select signal LOADSEL0.Pull-up resistor select signal LOADSEL0 be " 1 " (under the situation of high level=Vdd) because MOS transistor T13 ends, with MOS transistor T11 from 21 cut-outs of voltage data line.Selecting signal LOADSEL0 at pull-up resistor be that " 0 " (under the situation of low level=0V), owing to MOS transistor T13 conducting, is connected according to the diode-type ways of connecting MOS transistor T11 with voltage data line 21.
Similarly, on the source electrode of MOS transistor T14, apply supply voltage Vdd.MOS transistor T14 is connected with voltage data line 21 via MOS transistor T16.The grid of MOS transistor T14 is connected with voltage data line 21.On the grid of MOS transistor T16, apply pull-up resistor and select signal LOADSEL1.Pull-up resistor select signal LOADSEL1 be " 1 " (under the situation of high level=Vdd), with MOS transistor T14 from 21 cut-outs of voltage data line.Selecting signal LOADSEL1 at pull-up resistor is that " 0 " (under the situation of low level=0V), is connected according to the diode-type ways of connecting MOS transistor T14 with voltage data line 21.
In addition, similarly, on the source electrode of MOS transistor T17, apply supply voltage Vdd.MOS transistor T17 is connected with voltage data line 21 via MOS transistor T19.The grid of MOS transistor T17 is connected with voltage data line 21.On the grid of MOS transistor T19, apply pull-up resistor and select signal LOADSEL2.Pull-up resistor select signal LOADSEL2 be " 1 " (under the situation of high level=Vdd), with MOS transistor T17 from 21 cut-outs of voltage data line.Selecting signal LOADSEL2 at pull-up resistor is that " 0 " (under the situation of low level=0V), is connected according to the diode-type ways of connecting MOS transistor T17 with voltage data line 21.
Just, because MOS transistor T11, the T14 of current-voltage conversion circuit 20, T17 select signal LOADSEL0-2 to be connected with voltage data line 21 according to pull-up resistor, current-voltage conversion circuit 20 becomes variable load resistance.For the variable range that makes pull-up resistor becomes big, preferably the ratio with the resistance value of MOS transistor T11, T14, T17 is weighted in the mode such as 1: 1/2: 1/4.
The resistance value of MOS transistor T11, T14, T17 is inversely proportional with the ratio W/L of channel length L with channel width W.The channel width W that supposes MOS transistor T11 is W/L with the ratio of channel length L, then becomes 2W/L for MOS transistor T14, and becomes 4W/L for MOS transistor T17.So, can make the resistance value of current-voltage conversion circuit 20 select signal LOADSEL0-2 to be changed to 7 kinds according to pull-up resistor.
Just, the total channel width of the MOS transistor T11 of current-voltage conversion circuit 20, T14, T17 is as shown in table 1.For example, in LOADSEL0-2=＜0,1,1〉situation under, the total channel width is W, and as the resistance value maximum.On the other hand, in LOADSEL0-2=＜0,0,0〉situation under, the total channel width is 7W, and as the resistance value minimum.At this, establish the resistance value of MOS transistor T13, T16, T19 and compare little to negligible degree with corresponding MOS transistor T11, T14, the resistance value of T17.
Table 1
| LOADSEL0-2 | The total of channel width |
| <0，1，1> | W |
| <1，0，1> | 2W |
| <0，0，1> | 3W |
| <1，1，0> | 4W |
| <0，1，0> | 5W |
| <1，0，0> | 6W |
| <0，0，0> | 7W |
In addition, as shown in Figure 4, in the circuit of Fig. 3, can append P channel type MOS transistor T12, T15, T18.In this case, MOS transistor T12 is connected between the grid and voltage data line 21 of MOS transistor T11, and on this grid, applies pull-up resistor selection signal LOADSEL0.
Similarly, MOS transistor T15 is connected between the grid and voltage data line 21 of MOS transistor T14, and on this grid, applies pull-up resistor selection signal LOADSEL1.Similarly, MOS transistor T18 is connected between the grid and voltage data line 21 of MOS transistor T17, and on this grid, applies pull-up resistor selection signal LOADSEL2.MOS transistor 12,15,18 is carried out switch in the same manner like that with MOS transistor 13,16,19 respectively.
Like this, by MOS transistor 12 is set, make MOS transistor 13 by and with MOS transistor 11 when data line 21 cuts off, the grid capacitance of MOS transistor 11 is connected as the load capacitance of bit line BLj, can prevent that the data reading speed of memory cell MC from descending.That is, end by making MOS transistor 12, can the grid capacitance of MOS transistor 11 is disconnected from bit line BLj TURP.The reason that MOS transistor 15,18 is set is identical therewith.
The MOS transistor T20 that circuitry cuts is used is connected between voltage data line 21 and the data line DL, and applies read output signal SEN on this grid.Data line DL is connected with selected bit line BLj via the column decoder of Fig. 1.Be connected with selected memory cell MC on the bit line BLj.
When reading of sensing circuit 13 moved, MOS transistor T20 became conducting state owing to read output signal SEN rises to high level, thereby sensing circuit 13 is connected to data line DL.On the other hand, when the write activity of write circuit 14, read output signal SEN is a low level.MOS transistor T20 is in cut-off state, thereby sensing circuit 13 cuts off from data line DL.
Thus, in when action of reading of sensing circuit 13, MOS transistor T11, T14, T17 select signal LOADSEL0-2 according to pull-up resistor, optionally connect as the pull-up resistor of memory cell MC via data line DL, bit line BLj.And the cell current Icell of memory cell MC is transformed to voltage data Vdata by current-voltage conversion circuit 20.
For sensor amplifier 30, omitted detailed description thereof owing to having same formation, and on grid, applied voltage data Vdata from current-voltage conversion circuit 20 as a differential right side's MOS transistor T1 via voltage data line 21 with existing sensor amplifier 2.On grid, apply reference voltage V ref as differential right the opposing party's MOS transistor T2.Obtain output voltage V out from the connected node of MOS transistor T2, T4.That is, when Vdata＞Vref, output voltage V out is a high level, and when Vdata＜Vref, output voltage V out is a low level.
(action of sensing circuit)
Next, the action example of sensing circuit 13 is described based on Fig. 5 and Fig. 6.
At first, if sense command determines that then based on this sense command, pull-up resistor selects signal LOADSEL0-2 to be fixed.Afterwards, if row address signal, column address signal determine, then determined by row-address decoder 12, column address decoder 11 selected addresses.Just, bit line BLj is connected with data line DL, and word line WLi is set at high level (read-out voltage level).
Next, if read output signal SEN rises to high level, then the current-voltage conversion circuit 20 of sensing circuit 13 is connected with data line DL, and because MOS transistor T5 conducting, sensor amplifier 30 becomes operating state.Sensor amplifier 30 by with reference voltage V ref with compare from the voltage data Vdata of current-voltage conversion circuit 20, the data of storing among the determine memory unit MC are " 0 " or " 1 ".
Fig. 6 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.Article three, Vdata-Icell curve (i), (ii), (iii) corresponding with the resistance value of current-voltage conversion circuit 20 (resistance is little, in the resistance, resistance is big).With three Vdata-Icell curves (i), (ii), (iii) be threshold current Iref1, Iref2, Iref3 with the corresponding cell current Icell of the intersection point of reference voltage V ref.
Vdata-Icell curve (i) is whether the data of being stored with determine memory unit MC are the corresponding curve of erase verification of " 1 ", and with the cell current threshold setting is condition strict for data " 1 ", that is, be set at the Iref2 bigger than Iref1.Thus, the resistance value with current-voltage conversion circuit 20 is set at " little ".In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 1＜0,0,0, and the channel width that adds up to is 7W.So, if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref2 that sets, then because Vdata＞Vref is " 0 " with data judging.If Iref2 is big than (Vout=H) cell current threshold value, then because Vdata＜Vref is " 1 " with data judging.(Vout＝L)
The Vdata-Icell curve (ii) is at the curve of reading usually, and is Iref1 with the cell current threshold setting.The resistance value of current-voltage conversion circuit 20 is set at " in ".In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 1＜0,0,1, and the channel width that adds up to is 3W.So,, be " 0 " then with data judging if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref1 that sets.If Iref1 is big than the cell current threshold value, be " 1 " then with data judging.
The Vdata-Icell curve (iii) is and judges the corresponding curve of program verification that whether has correctly write data " 0 " in memory cell MC, and with the cell current threshold setting is condition strict for data " 0 ", that is, be set at the Iref3 littler than Iref1.In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 1＜1,0,1, and the channel width that adds up to is 2W.So,, be " 0 " then with data judging if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref3 that sets.If Iref3 is big than the cell current threshold value, be " 1 " then with data judging.
In addition, the input action voltage range of sensor amplifier 30 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax as previously mentioned.In this case, reference voltage V ref is set at the center of input action voltage range or this center near.
Like this, according to present embodiment, under the situation that checking the time is changed the cell current threshold value, change reference voltage V ref before not resembling, and the resistance value of current-voltage conversion circuit 20 is changed.Thus, reference voltage V ref can be included in the input action voltage range of sensor amplifier 2 regular events, even when checking, the resolution characteristic that data are read can not reduce yet.Especially, even, also can carry out the stable action of reading owing to the reduction of supply voltage Vdd makes the input action voltage range of sensor amplifier 30 narrow down.
Next, the semiconductor storage 100 of second embodiment of the present invention will be described based on accompanying drawing.The formation of the current-voltage conversion circuit 20A of the sensing circuit 13 of this semiconductor storage 100 is different with first embodiment, and other formation is identical.
Fig. 7 is the circuit diagram of sensing circuit 13.Constituting of this current-voltage conversion circuit 20A comprises: as resistance R 0, R1, R2, analog switch ASW0, ASW1, ASW2 and phase inverter INV0, the INV1 of formation on-off circuit, the INV2 of pull-up resistor.Other of sensing circuit 13 constitute owing to identical explanation of having omitted it with first embodiment.
Resistance R 0, R1, R2 have linear preferably resistive element (diffusion resistance outside the transistor etc.) and form by voltage is applied, and are connected with voltage data line 21 via analog switch ASW0, ASW1, ASW2 respectively.These analog switches ASW0～ASW2 constitutes by P channel type MOS transistor and N channel type MOS transistor are connected in parallel, and the voltage of voltage data line 21 is had good linearity.
On the grid of the N of analog switch ASW0 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL0, select signal * LOADSEL0 at the counter-rotating pull-up resistor that applies on the grid of its P channel type MOS transistor after by phase inverter INV0 pull-up resistor being selected signal LOADSEL0 counter-rotating.
Similarly, on the grid of the N of analog switch ASW1 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL1, select signal * LOADSEL1 at the counter-rotating pull-up resistor that applies on the grid of its P channel type MOS transistor after by phase inverter INV1 pull-up resistor being selected signal LOADSEL1 counter-rotating.
Similarly, on the grid of the N of analog switch ASW2 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL2, select signal * LOADSEL2 at the counter-rotating pull-up resistor that applies on the grid of its P channel type MOS transistor after by phase inverter INV2 pull-up resistor being selected signal LOADSEL2 counter-rotating.
Just, because the resistance R 0 of current-voltage conversion circuit 20A, R1, R2 are selected signal LOADSEL0-2 according to pull-up resistor and be connected with voltage data line 21, current-voltage conversion circuit 20A becomes variable load resistance.For the variable range that makes pull-up resistor becomes big, preferably the ratio with the resistance value of resistance R 0, R1, R2 is weighted in the mode such as 1: 1/2: 1/4.Just, the resistance value of supposing resistance R 0 is R, and then the resistance value of resistance R 1 is 1/2R, and the resistance value of resistance R 2 is 1/4R.
So, can make that the resistance value of current-voltage conversion circuit 20A is as shown in table 2 selects signal LOADSEL0-2 to be changed to 7 kinds according to pull-up resistor.At this, establish the connection resistance value of analog switch ASW0, ASW1, ASW2 and compare little to negligible degree with corresponding resistance R 0, the resistance value of R1, R2.
Table 2
| LOADSEL0-2 | Resistance value |
| <1，0，0> | R |
| <0，1，0> | R/2 |
| <1，1，0> | R/3 |
| <0，0，1> | R/4 |
| <1，0，1> | R/5 |
| <0，1，1> | R/6 |
| <1，1，1> | R/7 |
Fig. 8 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.In this case, identical with first embodiment, three Vdata-Icell curves (iv), (v), (vi) corresponding with the resistance value of current-voltage conversion circuit 20A (resistance is little, in the resistance, resistance is big).Because pull-up resistor R0, R1, R2 constitute by having better linear resistive element, three Vdata-Icell curves (iv), (v), (vi) can be approximate by straight line.
With three Vdata-Icell curves (iv), ((be threshold current Iref1, Iref2, Iref3 vi) v), with the corresponding cell current Icell of the intersection point of reference voltage V ref.
The Vdata-Icell curve (iv) is whether the data of being stored with determine memory unit MC are the corresponding curve of erase verification of " 1 ", and with the cell current threshold setting is condition strict for data " 1 ", that is, be set at the Iref2 bigger than Iref1.Thus, the resistance value with current-voltage conversion circuit 20A is set at " little ".In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 2＜1,1,1, and resistance value is 1/7R.So, if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref2 that sets, then because Vdata＞Vref is " 0 " with data judging.If Iref2 is big than the cell current threshold value, then because Vdata＜Vref is " 1 " with data judging.
The Vdata-Icell curve (v) is at the curve of reading usually, and is Iref1 with the cell current threshold setting.The resistance value of current-voltage conversion circuit 20A is set at " in ".In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 2＜1,1,0, and resistance value is 1/3R.So,, be " 0 " then with data judging if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref1 that sets.If Iref1 is big than the cell current threshold value, be " 1 " then with data judging.
The Vdata-Icell curve (vi) is and judges the corresponding curve of program verification whether correctly write data " 0 " in memory cell MC, and with the cell current threshold setting is condition strict for data " 0 ", that is, be set at the Iref3 littler than Iref1.The resistance value of current-voltage conversion circuit 20A is set at " greatly ".In this case, with pull-up resistor select signal LOADSEL0-2 be set at such as table 2＜0,1,0, and resistance value is 1/2R.
So,, be " 0 " then with data judging if the cell current Icell of memory cell MC is littler than the cell current threshold value Iref3 that sets.If Iref3 is big than the cell current threshold value, be " 1 " then with data judging.
In addition, the input action voltage range of sensor amplifier 30 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax as previously mentioned.In this case, reference voltage V ref is set at the center of input action voltage range or this center near.
Like this, identical according to present embodiment with first embodiment, even can obtain when checking the data resolution characteristic of reading effect such as can not reduce yet.In addition, according to present embodiment, because the Vdata-Icell curve is linear good, compare with first embodiment, it is big that near the inclination of the Vdata-Icell curve cell current threshold value Iref1-3 becomes.Just, for the variation of the cell current Icell in this zone, it is big that the variation of data voltage Vdata becomes.Thus, existence is near the advantage of the resolution characteristic raising of the cell current Icell it.
In addition, the present invention is not limited to above-mentioned embodiment, needless to say, can change in the scope that does not break away from these main points.For example, the number of pull-up resistor (resistance R 0 etc.) that becomes number, the current-voltage conversion circuit 20A of the MOS transistor (MOS transistor T11 etc.) of the pull-up resistor of current-voltage conversion circuit 20 is not limited to 3, and can suitably change.
In addition, although in first and second embodiments, with serial input and output type EEPROM is that example is illustrated, but the present invention is owing to is characterized in that sensing circuit 13, can be widely applicable for parallel input and output type EEPROM, possess the storer that can carry out the memory cell that writes and read of data in the mode of electricity is arranged.
Claims (8)
1. semiconductor storage is characterized in that having:
Bit line;
Memory cell, it is connected with described bit line, can carry out writing and reading of data in the mode of electricity, and makes with the corresponding cell current of these data mobile on described bit line;
Current-voltage conversion circuit, it is connected with described memory cell via described bit line, and the described cell current that is used for flowing on the described bit line is transformed to voltage data; And
Sensor amplifier, it is used for described voltage data and reference voltage are compared,
And described current-voltage conversion circuit constitutes and comprises the variable load resistance that is connected with described memory cell via described bit line.
2. semiconductor storage according to claim 1 is characterized in that,
Described variable load resistance has a plurality of MOS transistor and is used for the on-off circuit that the described memory cell of each transistor AND gate with described a plurality of MOS transistor optionally connects.
3. semiconductor storage according to claim 2 is characterized in that,
Described on-off circuit has first on-off element between the drain electrode that is connected described bit line and described MOS transistor.
4. semiconductor storage according to claim 3 is characterized in that,
Described on-off circuit has the second switch element between the grid that is connected described bit line and described MOS transistor.
5. semiconductor storage according to claim 1 is characterized in that,
The on-off circuit that described variable load resistance has a plurality of resistance and each resistance of described a plurality of resistance and described memory cell optionally are connected.
6. semiconductor storage according to claim 5 is characterized in that,
Described on-off circuit is formed by the analog switch that is connected in series with described resistance.
7. according to each described semiconductor storage in the claim 1～6, it is characterized in that,
Described reference voltage is set near the center or this center of input action voltage range of described sensor amplifier.
8. according to each described semiconductor storage in the claim 1～7, it is characterized in that,
When common reading, the resistance value of described variable load resistance is set at first resistance value, and when judging that the checking whether normally write data in described memory cell is read, the resistance value of described variable load resistance is set at second resistance value different with described first resistance value.
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| JP2010-020215 | 2010-02-01 | ||
| JP2010020215A JP2011159355A (en) | 2010-02-01 | 2010-02-01 | Semiconductor memory device |
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Cited By (3)
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| CN106128501A (en) * | 2015-05-08 | 2016-11-16 | 爱思开海力士有限公司 | For reading the semiconductor device of the information stored in resistor or unit |
| US9570173B2 (en) | 2013-09-11 | 2017-02-14 | Kabushiki Kaisha Toshiba | Semiconductor storage device and memory system |
| CN108140405A (en) * | 2015-08-14 | 2018-06-08 | 斯平转换技术公司 | For the method and apparatus of bipolar memory write verification |
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| US9073428B2 (en) | 2011-07-20 | 2015-07-07 | Honda Motor Co., Ltd. | Supporting structure for vehicle control unit |
| US9042190B2 (en) * | 2013-02-25 | 2015-05-26 | Micron Technology, Inc. | Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase |
| JP2021012752A (en) * | 2019-07-08 | 2021-02-04 | キオクシア株式会社 | Semiconductor storage device |
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| Publication number | Publication date |
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| CN102142279B (en) | 2014-07-02 |
| JP2011159355A (en) | 2011-08-18 |
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