CN102142279B - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
- Publication number
- CN102142279B CN102142279B CN201110021219.6A CN201110021219A CN102142279B CN 102142279 B CN102142279 B CN 102142279B CN 201110021219 A CN201110021219 A CN 201110021219A CN 102142279 B CN102142279 B CN 102142279B
- Authority
- CN
- China
- Prior art keywords
- voltage
- mos transistor
- data
- memory cell
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention provides a semiconductor storage device, wherein the resolution for data readout does not reduce even in verification and a stable readout action can be performed even when the power supply voltage is reduced. The readout circuit (13) of the invention comprises: a current voltage transform circuit (20) for transforming cell current (Icell) of a memory cell (MC) into voltage data (Vdata), and a readout amplifier (30) for comparing the voltage data (Vdata) with a reference voltage (Vref). The current voltage transform circuit (20) is configured to comprise a variable load resistance connected with the memory cell (MC) through a bit line ( BLj). The variable load resistance is configured to comprise a P channel type MOS transistor (T11, T14, T17) used as a load resistance, and a P channel type MOS transistor (T13, T16, T19) forming a switch circuit.
Description
Technical field
The present invention relates to semiconductor storage, particularly relate to a kind ofly by the data voltage corresponding with the cell current of memory cell and given reference voltage are compared, carry out the semiconductor storage of reading of the data to storing in memory cell.
Background technology
In recent years, electrically programmable erasable nonvolatile memory (EEPROM) is widely used in the electronic equipments such as mobile phone and digital still video camera.EEPROM is equipped with the memory cell with floating grid.So, according to whether having accumulated electric charge on floating grid, the data that two values or two values are above are recorded in memory cell, the variation of the electric current whether flowing through between source electrode and drain electrode according to the existence of electric charge of depending on floating grid, sense data from memory cell.
In this case, be arranged on sensing circuit in EEPORM by cell current mobile in memory cell is transformed to data voltage, this data voltage and given reference voltage are compared, carry out the judgement of the data (" 0 ", " 1 ") to storing in memory cell.
Fig. 9 is the circuit diagram of the sensing circuit of above-mentioned EEPORM.This sensing circuit is made up of current-voltage conversion circuit 1 (pre-sensor amplifier) and sensor amplifier 2 (primary sense amplifier).Current-voltage conversion circuit 1 is by applying supply voltage Vdd to source electrode and grid being formed with the P channel type MOS transistor T6 that drain electrode is connected (diode-type connection) jointly, and is connected with the drain electrode of memory cell MC via the bit line BL in this drain electrode.The cell current Icell of memory cell MC flows to bit line BL, and is transformed to data voltage Vdata by current-voltage conversion circuit 1.
The common differential amplifier that sensor amplifier 2 amplifies the difference of data voltage Vdata and reference voltage V ref.Sensor amplifier 2 is by forming differential right N channel type MOS transistor T1, T2; Be connected in series respectively and form P channel type MOS transistor T3, the T4 of current mirror with MOS transistor T1, T2; And the N channel type MOS transistor T5 being connected with the common source of MOS transistor T1, T2 forms.
On the common source of MOS transistor T3, T4, apply supply voltage Vdd.On the grid of MOS transistor T1, apply the data voltage Vdata from current-voltage conversion circuit 1.On the grid of MOS transistor T2, apply reference voltage V ref.On the grid of MOS transistor T5, apply to read and enable signal SEN.
To the action of this sensing circuit be described based on Fig. 9 and Figure 10 below.In this case, by source electrode line SL ground connection, and apply read-out voltage on bit line BL.So for example, if the voltage of word line (word line) WL rises to high level (, Vdd), the cell current Icell corresponding with the data of storing in storer MC can flow.Conventionally, cell current Icell is the value of 0～tens μ A level.It is the situation of data " 0 " (write state) for memory cell MC, cell current Icell is smaller value (approaching the value of minimum value), be the situation of data " 1 " (erase status) for memory cell MC, cell current Icell is large in comparison value (approaching peaked value).This cell current Icell is transformed to voltage data Vdata by current-voltage conversion circuit 1.
Afterwards, enable signal SEN and rise to high level (for example, Vdd) if read, MOS transistor T5 conducting, sensor amplifier 2 becomes state of activation.Thus, sensor amplifier 2, by voltage data Vdata and reference voltage V ref are compared, is carried out the judgement of the data (" 0 ", " 1 ") to storing in memory cell MC.
Figure 10 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.The cell current Icell (=Iref1-3) corresponding with the intersection point of reference voltage V ref (=Vref1-3) with Vdata-Icell curve is cell current threshold value.That is, if the cell current Icell of memory cell MC is less than the cell current threshold value setting, be " 0 " by data judging, if larger than cell current threshold value, would be " 1 " by data judging.
In addition, the input action voltage range of sensor amplifier 2 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax.
In this case, be expressed as: Vmin=Vt (T1)+Vds (T5), Vmax=Vdd-Vds (T3)+Vt (T1).Vt (T1) is the threshold value of MOS transistor T1, T2, Vds (T5) is voltage between the source drain of MOS transistor T5, and Vds (T3) is voltage (the voltage drop part of diode) between the source drain of MOS transistor T3.
Therefore, reference voltage V ref at least needs to fall in this input action voltage range.As shown in figure 10, in the situation that conventionally reading, be Iref1 by cell current Threshold, correspondingly, reference voltage V ref is set as to the center of input action voltage range or near the Vref1 it.
Usually, in EEPROM, there is the decision-making function of the data writing that is called as checking (verify).In checking, there is these two kinds of erase verification (ERASE checking) and program verifications.In erase verification, determine whether the data of having wiped memory cell MC, that is, whether the data of storing in determine memory unit MC are 1.In this case, cell current Threshold for for the strict condition of data " 1 ", that is, is set as to the Iref2 larger than Iref1.Follow therewith, reference voltage V ref is changed to the Vref2 lower than Vref1.This is for considering the discrete of cell current Icell and over time, the action of EEPROM being compensated.
On the other hand, in program verification, judge and in memory cell MC, whether correctly write data " 0 ".In this case, cell current Threshold for for the strict condition of data " 0 ", that is, is set as to the Iref3 less than Iref1.Follow therewith, reference voltage V ref is changed to the Vref3 higher than Vref1.
Patent documentation 1: TOHKEMY 2008-140431 communique
Summary of the invention
Described above, in existing sensing circuit, the cell current threshold value while checking in order to change, to reference voltage V, ref changes.Thus, the reference voltage V ref3 of program verification is close to the upper voltage limit Vmax of the input action voltage range of sensor amplifier 2, and the reference voltage V ref2 of erase verification is close to the lower limit Vmin of input action voltage range.Due to the setting of cell current threshold value, reference voltage V ref2, the Vref3 may verify time is not included into the situation of input action voltage range.Thus, the resolution characteristic of data reading likely can reduce, or the misoperation of reading likely can produce.
Especially, if supply voltage Vdd step-down is the degree such as 1.8V, due to the input action voltage range of sensor amplifier 2 very narrow become the degree of 0.8V-1.6V, reference voltage V ref2, Vref3 during by checking include this input action voltage range in and will become more and more difficult.
Therefore, semiconductor storage of the present invention has: bit line; Memory cell, it is connected with described bit line, can carry out writing and reading of data in electric mode, and the cell current corresponding with these data flowed on described bit line; Current-voltage conversion circuit, it is connected with described memory cell via described bit line, for the described cell current flowing on described bit line is transformed to voltage data; And sensor amplifier, it is for comparing described voltage data and reference voltage, and wherein, the formation of described current-voltage conversion circuit is to comprise: the variable load resistance being connected with described memory cell via described bit line.
(invention effect)
According to semiconductor storage of the present invention, because the formation of described current-voltage conversion circuit is for comprising variable resistor, in the time that cell current threshold value is changed, by variable-resistance resistance value is changed, roughly change reference voltage from the center of the input action voltage range of sensor amplifier and become unnecessary.Thus, even in the time of checking, the resolution characteristic of data reading can step-down yet.
Especially, even narrow because the reduction of supply voltage makes the input action voltage range of sensor amplifier, also can carry out the stable action of reading.
Brief description of the drawings
Fig. 1 is the overall skeleton diagram of the semiconductor storage of the first embodiment of the present invention.
Fig. 2 is the sectional view of the memory cell of the semiconductor storage of the first embodiment of the present invention.
Fig. 3 is the circuit diagram of the sensing circuit of the semiconductor storage of the first embodiment of the present invention.
Fig. 4 is the circuit diagram of another sensing circuit of the semiconductor storage of the first embodiment of the present invention.
Fig. 5 is the action timing diagram of the semiconductor storage of the first embodiment of the present invention.
Fig. 6 is the figure of the characteristic of the sensing circuit of the semiconductor storage of explanation the first embodiment of the present invention.
Fig. 7 is the circuit diagram of the sensing circuit of the semiconductor storage of the second embodiment of the present invention.
Fig. 8 is the figure of the characteristic of the sensing circuit of the semiconductor storage of explanation the second embodiment of the present invention.
Fig. 9 is the circuit diagram of the sensing circuit of existing semiconductor storage.
Figure 10 is the figure of the sensing circuit for existing semiconductor storage is described.
(symbol description)
10 memory areas
11 column decoders
12 row decoders
13 sensing circuits
14 write circuits
15 control circuits
20,20A current-voltage conversion circuit
30 sensor amplifiers
100 semiconductor storages
101 semiconductor substrates
105 gate insulating films
109 floating grids
109a jut
110 tunnel insulator films
112 control grid
113 drain electrodes
114 source electrodes
115 raceway grooves
Embodiment
To the semiconductor storage 100 of the first embodiment of the present invention be described based on accompanying drawing.According to present embodiment, semiconductor storage 100 is described as the EEPROM of serial input output type.
(entirety of semiconductor storage forms)
Fig. 1 is the skeleton diagram of semiconductor storage 100.As shown in the figure, in memory array area 10, multiple bit line BL0～BLn extend in the Y direction, and multiple word line WL0～WLm, multiple source electrode line SL0～SLm extend on the directions X vertical with Y-direction.Be provided with accordingly multiple memory cell MC with each point of crossing of multiple bit line BL0～BLn and multiple word line WL0～WLm.
In addition, be adjacent to be provided with memory array area 10 row decoder 12 of selecting the column decoder 11 of a bit line based on column address signal and select a word line based on row address signal from multiple bit line BL0～BLn from multiple word line WL0～WLm.By determining column address signal and row address signal, select a memory cell MC.
And, be provided with the sensing circuit 13 that reads out the data of the memory cell MC occurring via data line DL in the selected bit line BLj of column decoder 11.In this case, sensing circuit 13, by stable reference voltage V ref and the data voltage Vdata that cell current Icell mobile in selected memory cell MC is carried out after voltage transformation are compared, carrys out the judgement of executing data " 0 ", " 1 ".
In addition, be provided with the write circuit 14 selected memory cell MC executing data being write via the selected bit line BLj of column decoder 11.In addition, be provided with the control circuit 15 that carrys out each sequence that writes, reads, wipes of control store unit MC based on various control signals.
(formation of memory cell)
The concrete formation example of memory cell MC is described with reference to Fig. 2.This memory cell MC is splitting bar polar form, and on semiconductor substrate 101, separates predetermined distance and be formed with raceway groove 115 between the drain electrode 113 that forms and source electrode 114.Be formed with the floating grid 109 of expanding to a part for source electrode 114 by gate insulating film 105 part for raceway groove 115.Covered top and the sidepiece of floating grid 109 by tunnel insulator film 110, and be formed with the control grid 112 of expanding in a part for drain electrode 113.
Next by the action of the memory cell MC of description splitting bar polar form.First,, when data writing " 0 ", on control grid 112 and source electrode 114, (for example apply high voltage, be 2V controlling on grid 112, on source region 114, be 12V), because electric current flows in raceway groove 115, inject thermoelectron and make its accumulation to floating grid 109.
In addition, in the time wiping the data " 0 " that write (, when data " 0 " are rewritten as to " 1 "), for example, by applying high voltage (15V) by drain electrode 113 and source electrode 114 ground connection and controlling on grid 112, using the electronics of accumulating in floating grid 109 as Fowler-Nordheim tunnel current, (hereinafter referred to as FN tunnel current) is retracted to and controls grid 112.Owing to being formed with jut 109a on the top of floating grid 109, electric field is concentrated here, under low voltage, can flow through FN tunnel current.
In addition, when the data of storing at readout memory unit MC, controlling the voltage that applies regulation in grid 112 and drain electrode 113 (for example, be 3V controlling on grid 112, drain on 113 be 1V).So, with the quantity of electric charge of the electronics of accumulating in floating grid 109 accordingly, between source drain, flow through cell current Icell.Data writing " 0 " in the situation that, the threshold value of memory cell MC uprises, and cell current Icell diminishes, and data writing " 1 " in the situation that (while wiping), the threshold value step-down of memory cell MC, it is large that cell current Icell becomes.
(formation of sensing circuit)
Next, based on Fig. 3, the formation as the sensing circuit 13 of feature of the present invention is described.The formation of sensing circuit 13 is to comprise: the N channel type MOS transistor T20 that current-voltage conversion circuit 20 (pre-sensor amplifier), sensor amplifier 30 (primary sense amplifier) and circuitry cuts are used.
The formation of current-voltage conversion circuit 20 is to comprise: as the P channel type MOS transistor T11 of pull-up resistor, T14, T17 and form P channel type MOS transistor T13, T16, the T19 of on-off circuit.
In this case, on the source electrode of MOS transistor T11, apply supply voltage Vdd.MOS transistor T11 is connected with voltage data line 21 via MOS transistor T13.The grid of MOS transistor T11 is connected with voltage data line 21.On the grid of MOS transistor T13, apply pull-up resistor and select signal LOADSEL0.In the situation that pull-up resistor selects signal LOADSEL0 to be " 1 " (high level=Vdd), due to MOS transistor T13 cut-off, MOS transistor T11 is cut off from voltage data line 21.In the situation that pull-up resistor selects signal LOADSEL0 to be " 0 " (low level=0V), due to MOS transistor T13 conducting, the mode that MOS transistor T11 is connected according to diode-type is connected with voltage data line 21.
Similarly, on the source electrode of MOS transistor T14, apply supply voltage Vdd.MOS transistor T14 is connected with voltage data line 21 via MOS transistor T16.The grid of MOS transistor T14 is connected with voltage data line 21.On the grid of MOS transistor T16, apply pull-up resistor and select signal LOADSEL1.In the situation that pull-up resistor selects signal LOADSEL1 to be " 1 " (high level=Vdd), MOS transistor T14 is cut off from voltage data line 21.In the situation that pull-up resistor selects signal LOADSEL1 to be " 0 " (low level=0V), the mode that MOS transistor T14 is connected according to diode-type is connected with voltage data line 21.
In addition, similarly, on the source electrode of MOS transistor T17, apply supply voltage Vdd.MOS transistor T17 is connected with voltage data line 21 via MOS transistor T19.The grid of MOS transistor T17 is connected with voltage data line 21.On the grid of MOS transistor T19, apply pull-up resistor and select signal LOADSEL2.In the situation that pull-up resistor selects signal LOADSEL2 to be " 1 " (high level=Vdd), MOS transistor T17 is cut off from voltage data line 21.In the situation that pull-up resistor selects signal LOADSEL2 to be " 0 " (low level=0V), the mode that MOS transistor T17 is connected according to diode-type is connected with voltage data line 21.
Namely, because MOS transistor T11, T14, the T17 of current-voltage conversion circuit 20 select signal LOADSEL0-2 to be connected with voltage data line 21 according to pull-up resistor, current-voltage conversion circuit 20 becomes variable load resistance.In order to make the variable range of pull-up resistor become large, preferably the ratio of the resistance value of MOS transistor T11, T14, T17 is weighted in the mode such as 1: 1/2: 1/4.
The resistance value of MOS transistor T11, T14, T17 is inversely proportional with the ratio W/L of channel length L with channel width W.Suppose that the channel width W of MOS transistor T11 and the ratio of channel length L are W/L, become 2W/L for MOS transistor T14, and become 4W/L for MOS transistor T17.So, can make the resistance value of current-voltage conversion circuit 20 select signal LOADSEL0-2 to be changed to 7 kinds according to pull-up resistor.
Namely, the total channel width of the MOS transistor T11 of current-voltage conversion circuit 20, T14, T17 is as shown in table 1.For example, at LOADSEL0-2=<0, in the situation of 1,1>, total channel width is W, and as resistance value maximum.On the other hand, at LOADSEL0-2=<0, in the situation of 0,0>, total channel width is 7W, and as resistance value minimum.At this, establish the resistance value of MOS transistor T13, T16, T19 and compare little of negligible degree with corresponding MOS transistor T11, T14, the resistance value of T17.
Table 1
| LOADSEL0-2 | The total of channel width |
| <0，1，1> | W |
| <1，0，1> | 2W |
| <0，0，1> | 3W |
| <1，1，0> | 4W |
| <0，1，0> | 5W |
| <1，0，0> | 6W |
| <0，0，0> | 7W |
In addition, as shown in Figure 4, in the circuit of Fig. 3, can append P channel type MOS transistor T12, T15, T18.In this case, MOS transistor T12 is connected between the grid and voltage data line 21 of MOS transistor T11, and on this grid, applies pull-up resistor selection signal LOADSEL0.
Similarly, MOS transistor T15 is connected between the grid and voltage data line 21 of MOS transistor T14, and on this grid, applies pull-up resistor selection signal LOADSEL1.Similarly, MOS transistor T18 is connected between the grid and voltage data line 21 of MOS transistor T17, and on this grid, applies pull-up resistor selection signal LOADSEL2.MOS transistor 12,15,18 is carried out switch in the same manner like that with MOS transistor 13,16,19 respectively.
Like this, by MOS transistor 12 is set, when MOS transistor 11 cut-out from data line 21 MOS transistor 13 is ended, connect the grid capacitance of MOS transistor 11 as the load capacitance of bit line BLj, can prevent that the data reading speed of memory cell MC from declining.That is, by MOS transistor 12 is ended, can the grid capacitance of MOS transistor 11 is disconnected from bit line BLj TURP.The reason that MOS transistor 15,18 is set is identical therewith.
The MOS transistor T20 that circuitry cuts is used is connected between voltage data line 21 and data line DL, and on this grid, applies read output signal SEN.Data line DL is connected with selected bit line BLj via the column decoder of Fig. 1.On bit line BLj, be connected with selected memory cell MC.
In the time that reading of sensing circuit 13 moved, MOS transistor T20 becomes conducting state because read output signal SEN rises to high level, thereby sensing circuit 13 is connected to data line DL.On the other hand, in the time of the write activity of write circuit 14, read output signal SEN is low level.MOS transistor T20 is in cut-off state, thereby sensing circuit 13 cuts off from data line DL.
Thus, in the time that reading of sensing circuit 13 moved, MOS transistor T11, T14, T17 select signal LOADSEL0-2 according to pull-up resistor, optionally connect as the pull-up resistor of memory cell MC via data line DL, bit line BLj.And the cell current Icell of memory cell MC is transformed to voltage data Vdata by current-voltage conversion circuit 20.
For sensor amplifier 30, omit detailed description thereof owing to thering is same formation with existing sensor amplifier 2, and on the grid of the MOS transistor T1 as a differential right side, applied the voltage data Vdata from current-voltage conversion circuit 20 via voltage data line 21.On the grid of the MOS transistor T2 as differential right the opposing party, apply reference voltage V ref.Obtain output voltage V out from the connected node of MOS transistor T2, T4.That is, in the time of Vdata > Vref, output voltage V out is high level, and in the time of Vdata < Vref, output voltage V out is low level.
(action of sensing circuit)
Next, the action example of sensing circuit 13 is described based on Fig. 5 and Fig. 6.
First,, if sense command is definite, based on this sense command, pull-up resistor selects signal LOADSEL0-2 to be fixed.Afterwards, if row address signal, column address signal determine, determined by row-address decoder 12, the selected address of column address decoder 11.Namely, bit line BLj is connected with data line DL, and word line WLi is set as to high level (read-out voltage level).
Next, if read output signal SEN rises to high level, the current-voltage conversion circuit 20 of sensing circuit 13 is connected with data line DL, and due to MOS transistor T5 conducting, sensor amplifier 30 becomes operating state.Sensor amplifier 30 by by reference voltage V ref with compare from the voltage data Vdata of current-voltage conversion circuit 20, the data of coming to store in determine memory unit MC are " 0 " or " 1 ".
Fig. 6 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.Article three, the resistance value of Vdata-Icell curve (i), (ii), (iii) and current-voltage conversion circuit 20 (resistance is little, in resistance, resistance is large) is corresponding.The cell current Icell corresponding with the intersection point of reference voltage V ref with three Vdata-Icell curves (i), (ii), (iii) is threshold current Iref1, Iref2, Iref3.
Vdata-Icell curve (i) is whether the data of storing with determine memory unit MC are the corresponding curve of erase verification of " 1 ", and be strict condition for data " 1 " by cell current Threshold,, be set as the Iref2 larger than Iref1.Thus, the resistance value of current-voltage conversion circuit 20 is set as to " little ".In this case, select signal LOADSEL0-2 to be set as the <0 such as table 1 pull-up resistor, 0,0>, and the channel width adding up to is 7W.So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref2 setting, due to Vdata > Vref, be " 0 " by data judging.If Iref2 is large than (Vout=H) cell current threshold value, due to Vdata < Vref, be " 1 " by data judging.(Vout＝L)
Vdata-Icell curve (ii) is for the curve of conventionally reading, and is Iref1 by cell current Threshold.The resistance value of current-voltage conversion circuit 20 is set as " in ".In this case, select signal LOADSEL0-2 to be set as the <0 such as table 1 pull-up resistor, 0,1>, and the channel width adding up to is 3W.So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref1 setting, be " 0 " by data judging.If Iref1 is large than cell current threshold value, be " 1 " by data judging.
Vdata-Icell curve (iii) is and judges in memory cell MC, whether correctly to have write the corresponding curve of the program verification of data " 0 ", and be strict condition for data " 0 " by cell current Threshold,, be set as the Iref3 less than Iref1.In this case, select signal LOADSEL0-2 to be set as the <1 such as table 1 pull-up resistor, 0,1>, and the channel width adding up to is 2W.So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref3 setting, be " 0 " by data judging.If Iref3 is large than cell current threshold value, be " 1 " by data judging.
In addition, the input action voltage range of sensor amplifier 30 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax as previously mentioned.In this case, reference voltage V ref is set as to the center of input action voltage range or near at this center.
Like this, according to present embodiment, the in the situation that of cell current threshold value change in when checking, change reference voltage V ref before not resembling, and the resistance value of current-voltage conversion circuit 20 is changed.Thus, reference voltage V ref can be included in to the input action voltage range of sensor amplifier 2 regular events, even in the time of checking, the resolution characteristic of data reading also can not reduce.Especially, even narrow because the reduction of supply voltage Vdd makes the input action voltage range of sensor amplifier 30, also can carry out the stable action of reading.
Next, will the semiconductor storage 100 of the second embodiment of the present invention be described based on accompanying drawing.The formation of the current-voltage conversion circuit 20A of the sensing circuit 13 of this semiconductor storage 100 is different from the first embodiment, and other formation is identical.
Fig. 7 is the circuit diagram of sensing circuit 13.The formation of this current-voltage conversion circuit 20A is to comprise: as resistance R 0, R1, R2, analog switch ASW0, ASW1, ASW2 and phase inverter INV0, the INV1 of formation on-off circuit, the INV2 of pull-up resistor.Other of sensing circuit 13 form due to omitted its description identical with the first embodiment.
Resistance R 0, R1, R2 have good linear resistive element (diffusion resistance outside transistor etc.) and form by voltage is applied, and are connected with voltage data line 21 via analog switch ASW0, ASW1, ASW2 respectively.These analog switches ASW0～ASW2 is by P channel type MOS transistor and N channel type MOS transistor are connected in parallel and are formed, and the voltage of voltage data line 21 is had to good linearity.
On the grid of the N of analog switch ASW0 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL0, on the grid of its P channel type MOS transistor, apply by phase inverter INV0 and select the reversion pull-up resistor after signal LOADSEL0 reversion to select signal * LOADSEL0 to pull-up resistor.
Similarly, on the grid of the N of analog switch ASW1 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL1, on the grid of its P channel type MOS transistor, apply by phase inverter INV1 and select the reversion pull-up resistor after signal LOADSEL1 reversion to select signal * LOADSEL1 to pull-up resistor.
Similarly, on the grid of the N of analog switch ASW2 channel type MOS transistor, apply pull-up resistor and select signal LOADSEL2, on the grid of its P channel type MOS transistor, apply by phase inverter INV2 and select the reversion pull-up resistor after signal LOADSEL2 reversion to select signal * LOADSEL2 to pull-up resistor.
Namely, because resistance R 0, R1, the R2 of current-voltage conversion circuit 20A select signal LOADSEL0-2 according to pull-up resistor and be connected with voltage data line 21, current-voltage conversion circuit 20A becomes variable load resistance.In order to make the variable range of pull-up resistor become large, preferably the ratio of the resistance value of resistance R 0, R1, R2 is weighted in the mode such as 1: 1/2: 1/4.Namely, the resistance value of supposing resistance R 0 is R, and the resistance value of resistance R 1 is 1/2R, and the resistance value of resistance R 2 is 1/4R.
So, can make that the resistance value of current-voltage conversion circuit 20A is as shown in table 2 selects signal LOADSEL0-2 to be changed to 7 kinds according to pull-up resistor.At this, establish the connection resistance value of analog switch ASW0, ASW1, ASW2 and compare little of negligible degree with corresponding resistance R 0, the resistance value of R1, R2.
Table 2
| LOADSEL0-2 | Resistance value |
| <1，0，0> | R |
| <0，1，0> | R/2 |
| <1，1，0> | R/3 |
| <0，0，1> | R/4 |
| <1，0，1> | R/5 |
| <0，1，1> | R/6 |
| <1，1，1> | R/7 |
Fig. 8 shows the figure of the relation of voltage data Vdata, cell current Icell and reference voltage V ref.In this case, identical with the first embodiment, the resistance value of three Vdata-Icell curves (iv), (v), (vi) and current-voltage conversion circuit 20A (resistance is little, in resistance, resistance is large) is corresponding.Because pull-up resistor R0, R1, R2 form by having better linear resistive element, three Vdata-Icell curves (iv), (v), (vi) can be similar to by straight line.
The cell current Icell corresponding with the intersection point of reference voltage V ref with three Vdata-Icell curves (iv), (v), (vi) is threshold current Iref1, Iref2, Iref3.
Vdata-Icell curve (iv) is whether the data of storing with determine memory unit MC are the corresponding curve of erase verification of " 1 ", and be strict condition for data " 1 " by cell current Threshold,, be set as the Iref2 larger than Iref1.Thus, the resistance value of current-voltage conversion circuit 20A is set as to " little ".In this case, select signal LOADSEL0-2 to be set as the <1 such as table 2 pull-up resistor, 1,1>, and resistance value is 1/7R.So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref2 setting, due to Vdata > Vref, be " 0 " by data judging.If Iref2 is large than cell current threshold value, due to Vdata < Vref, be " 1 " by data judging.
Vdata-Icell curve (v) is for the curve of conventionally reading, and is Iref1 by cell current Threshold.The resistance value of current-voltage conversion circuit 20A is set as " in ".In this case, select signal LOADSEL0-2 to be set as the <1 such as table 2 pull-up resistor, 1,0>, and resistance value is 1/3R.So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref1 setting, be " 0 " by data judging.If Iref1 is large than cell current threshold value, be " 1 " by data judging.
Vdata-Icell curve (vi) is and judges in memory cell MC, whether correctly to have write the corresponding curve of the program verification of data " 0 ", and be strict condition for data " 0 " by cell current Threshold,, be set as the Iref3 less than Iref1.The resistance value of current-voltage conversion circuit 20A is set as to " greatly ".In this case, select signal LOADSEL0-2 to be set as the <0 such as table 2 pull-up resistor, 1,0>, and resistance value is 1/2R.
So, if the cell current Icell of memory cell MC is less than the cell current threshold value Iref3 setting, be " 0 " by data judging.If Iref3 is large than cell current threshold value, be " 1 " by data judging.
In addition, the input action voltage range of sensor amplifier 30 regular events (the grid voltage scope of MOS transistor T1, T2) is lower voltage limit Vmin～upper voltage limit Vmax as previously mentioned.In this case, reference voltage V ref is set as to the center of input action voltage range or near at this center.
Like this, according to present embodiment, identical with the first embodiment, can not reduce texts even if can obtain the resolution characteristic of data reading in the time of checking yet.In addition, according to present embodiment, because the linearity of Vdata-Icell curve is good, compared with the first embodiment, it is large that near the inclination of Vdata-Icell curve cell current threshold value Iref1-3 becomes.Namely, for the variation of the cell current Icell in this region, it is large that the variation of data voltage Vdata becomes.Thus, there is the advantage improving for the resolution characteristic of the cell current Icell it near.
In addition, the present invention is not limited to above-mentioned embodiment, needless to say, can in the scope that does not depart from these main points, change.For example, the number that becomes the pull-up resistor (resistance R 0 etc.) of number, the current-voltage conversion circuit 20A of the MOS transistor (MOS transistor T11 etc.) of the pull-up resistor of current-voltage conversion circuit 20 is not limited to 3, and can suitably change.
In addition, although in the first and second embodiments, be illustrated as an example of serial input output type EEPROM example, but the present invention is owing to is characterized in that sensing circuit 13, can be widely applicable for parallel input and output type EEPROM, possesses and have the storer that can carry out in electric mode the memory cell that writes and read of data.
Claims (3)
1. a semiconductor storage, is characterized in that having:
Bit line;
Memory cell, it is connected with described bit line, can carry out writing and reading of data in electric mode, and the cell current corresponding with these data flowed on described bit line;
Current-voltage conversion circuit, it is connected with described memory cell via described bit line, for the described cell current flowing on described bit line is transformed to voltage data; And
Sensor amplifier, it is for described voltage data and reference voltage are compared,
And described current-voltage conversion circuit is configured to and comprises the variable load resistance being connected with described memory cell via described bit line,
Described variable load resistance has multiple MOS transistor and the on-off circuit for memory cell described in each transistor AND gate of described multiple MOS transistor is optionally connected,
Wherein, described on-off circuit have be connected to the first on-off element between described bit line and the drain electrode of described MOS transistor and be connected to described bit line and the grid of described MOS transistor between second switch element.
2. semiconductor storage according to claim 1, is characterized in that,
Described reference voltage is set near the center or this center of input action voltage range of described sensor amplifier.
3. semiconductor storage according to claim 1, is characterized in that,
In the time of common reading, the resistance value of described variable load resistance is set as to the first resistance value, and in the time determining whether that the checking that has normally write data in described memory cell is read, the resistance value of described variable load resistance is set as to second resistance value different from described the first resistance value.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-020215 | 2010-02-01 | ||
| JP2010020215A JP2011159355A (en) | 2010-02-01 | 2010-02-01 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102142279A CN102142279A (en) | 2011-08-03 |
| CN102142279B true CN102142279B (en) | 2014-07-02 |
Family
ID=44409722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110021219.6A Expired - Fee Related CN102142279B (en) | 2010-02-01 | 2011-01-14 | Semiconductor storage device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2011159355A (en) |
| CN (1) | CN102142279B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9073428B2 (en) | 2011-07-20 | 2015-07-07 | Honda Motor Co., Ltd. | Supporting structure for vehicle control unit |
| US9042190B2 (en) * | 2013-02-25 | 2015-05-26 | Micron Technology, Inc. | Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase |
| WO2015037088A1 (en) * | 2013-09-11 | 2015-03-19 | 株式会社 東芝 | Semiconductor storage device and memory system |
| KR102341230B1 (en) * | 2015-05-08 | 2021-12-21 | 에스케이하이닉스 주식회사 | Semiconductor apparatus for reading stored information of resistor or cell |
| US10163479B2 (en) * | 2015-08-14 | 2018-12-25 | Spin Transfer Technologies, Inc. | Method and apparatus for bipolar memory write-verify |
| JP2021012752A (en) * | 2019-07-08 | 2021-02-04 | キオクシア株式会社 | Semiconductor storage device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142495A (en) * | 1989-03-10 | 1992-08-25 | Intel Corporation | Variable load for margin mode |
| US6930922B2 (en) * | 2002-07-30 | 2005-08-16 | Sharp Kabushiki Kaisha | Reading circuit, reference circuit, and semiconductor memory device |
| CN1998053A (en) * | 2004-02-19 | 2007-07-11 | 斯班逊有限公司 | Current and voltage conversion circuit and its controlling method |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61222093A (en) * | 1985-03-28 | 1986-10-02 | Toshiba Corp | Nonvolatile semiconductor memory device |
| JPH0196897A (en) * | 1987-10-08 | 1989-04-14 | Toshiba Corp | Non-volatile semiconductor memory device |
| JPH01279499A (en) * | 1988-05-06 | 1989-11-09 | Hitachi Ltd | Nonvolatile storage and its verification method |
| JPH05282881A (en) * | 1992-03-31 | 1993-10-29 | Toshiba Corp | Semiconductor memory |
| JPH06203585A (en) * | 1992-12-28 | 1994-07-22 | Kawasaki Steel Corp | Non-volatile semiconductor memory capable of electrical writing and erasing |
| EP0753859B1 (en) * | 1995-07-14 | 2000-01-26 | STMicroelectronics S.r.l. | Method for setting the threshold voltage of a reference memory cell |
| JP3114620B2 (en) * | 1996-05-30 | 2000-12-04 | 日本電気株式会社 | Semiconductor storage device |
| JPH11126490A (en) * | 1997-10-22 | 1999-05-11 | Toshiba Microelectronics Corp | Non-volatile semiconductor memory |
| JPH11346127A (en) * | 1998-06-02 | 1999-12-14 | Hitachi Ltd | Constant current circuit and semiconductor integrated circuit |
| JP2001028193A (en) * | 1999-07-13 | 2001-01-30 | Sanyo Electric Co Ltd | Semiconductor memory |
| JP3596808B2 (en) * | 2000-08-10 | 2004-12-02 | 沖電気工業株式会社 | Nonvolatile semiconductor memory device |
| US7551503B2 (en) * | 2005-06-24 | 2009-06-23 | Macronix International Co., Ltd. | Method for refreshing a flash memory |
| JP4262227B2 (en) * | 2005-07-22 | 2009-05-13 | シャープ株式会社 | Read circuit for semiconductor memory device |
| JP5022681B2 (en) * | 2006-11-30 | 2012-09-12 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor memory device |
-
2010
- 2010-02-01 JP JP2010020215A patent/JP2011159355A/en active Pending
-
2011
- 2011-01-14 CN CN201110021219.6A patent/CN102142279B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142495A (en) * | 1989-03-10 | 1992-08-25 | Intel Corporation | Variable load for margin mode |
| US6930922B2 (en) * | 2002-07-30 | 2005-08-16 | Sharp Kabushiki Kaisha | Reading circuit, reference circuit, and semiconductor memory device |
| CN1998053A (en) * | 2004-02-19 | 2007-07-11 | 斯班逊有限公司 | Current and voltage conversion circuit and its controlling method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011159355A (en) | 2011-08-18 |
| CN102142279A (en) | 2011-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9830987B2 (en) | Sense amplifier local feedback to control bit line voltage | |
| KR0184093B1 (en) | Non-volatile semiconductor memory device and data erasing method therefor | |
| US8885428B2 (en) | Smart read scheme for memory array sensing | |
| KR101196936B1 (en) | Nonvolatile semiconductor memory device | |
| CN102142279B (en) | Semiconductor storage device | |
| US9653126B2 (en) | Digital ramp rate control for charge pumps | |
| JP5193701B2 (en) | Semiconductor memory device | |
| US9939831B2 (en) | Fast settling low dropout voltage regulator | |
| US7359246B2 (en) | Memory device with a ramp-like voltage biasing structure based on a current generator | |
| KR20110094240A (en) | Nonvolatile semiconductor memory device | |
| US8274842B1 (en) | Variable impedance memory device having simultaneous program and erase, and corresponding methods and circuits | |
| US9224466B1 (en) | Dual capacitor sense amplifier and methods therefor | |
| US9361976B2 (en) | Sense amplifier including a single-transistor amplifier and level shifter and methods therefor | |
| US8467245B2 (en) | Non-volatile memory device with program current clamp and related method | |
| CN104937718B (en) | High speed detection technology for advanced nanometer flash memory device | |
| JPH10112195A (en) | Nonvolatile memory device | |
| US20160372205A1 (en) | Sense amplifier design for ramp sensing | |
| US20110188316A1 (en) | Semiconductor memory device | |
| US8681567B2 (en) | Voltage regulator for biasing a NAND memory device | |
| EP0698889B1 (en) | Memory device | |
| JP2020532040A (en) | Improved sensing amplifier circuit for reading data in flash memory cells | |
| CN100456388C (en) | Method and apparatus for soft program verification in a memory device | |
| KR100840562B1 (en) | Nonvolatile semiconductor memory device and its writing method | |
| JP2010027162A (en) | Nonvolatile semiconductor memory and method for writing data into nonvolatile semiconductor memory | |
| KR100933845B1 (en) | Voltage generation circuit and nonvolatile memory device having same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140702 Termination date: 20220114 |