CN102145874B - Micro-electro-mechanical device and manufacturing method thereof - Google Patents
Micro-electro-mechanical device and manufacturing method thereof Download PDFInfo
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- CN102145874B CN102145874B CN201010117019.6A CN201010117019A CN102145874B CN 102145874 B CN102145874 B CN 102145874B CN 201010117019 A CN201010117019 A CN 201010117019A CN 102145874 B CN102145874 B CN 102145874B
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Abstract
The invention discloses a micro-electro-mechanical device and a manufacturing method thereof, and the manufacturing method comprises the following steps: providing a semiconductor substrate comprising a semiconductor layer and an interconnection structure; then forming a protecting layer and a photoresist layer on the interconnection structure, forming a plurality of openings for exposing one part of the protecting layer in the photoresist layer, and removing the protecting layer exposed through the openings and the interconnection structure below the protecting layer so as to form a plurality of first trenches; partially removing the semiconductor layer exposed through the first trenches so as to form a plurality of second trenches in the semiconductor layer; attaching an upper cover substrate on the protecting layer for forming a compound substrate, thinning the semiconductor layer in the compound substrate, and retaining the thinned semiconductor layer; and finally partially removing the thinned semiconductor layer and forming a third trench so as to form a suspended micro-processing structure in a region among the first trenches, the second trenches and the third trench.
Description
Technical field
The present invention relates to microelectromechanicdevices devices (microelectromechanical system device, MEMS device) making, and the manufacture method that particularly relates to a kind of microelectromechanicdevices devices, to guarantee the damage of dielectric film layer or the metallic diaphragm of the micro-processing structure in it.
Background technology
Microelectromechanicdevices devices is widely applied to the aspects such as inertia measurement, pressure-sensing, temperature survey, microjet (micro-fluidics), optics and radio-frequency communication at present, and the further expansion and extension gradually of its range of application.As generally included micro-processing structure (suspended micromachined structure) of suspension in the existing microelectromechanicdevices devices of accelerometer (accelerometer), pressure sensor, sensing flux device and homologue etc., it generally includes release portion (released portion) and adheres to the trunk portion on substrate, has space or space between above-mentioned release portion and substrate.
Generally speaking, when making micro-processing structure, the pattern metal rete that employing is positioned at the superiors is as etching mask and apply suitable etching program, to remove the rete part that pattern metal rete is not covered for this reason, and for completing the preparation of micro-processing structure.
Yet, in aforementioned etching program, the anti-etching ability of the etching mask of playing the part of due to the metallic diaphragm of patterning is still limited, therefore the profile of prepared micro-processing structure is feared the non-form for expection, in the micro-processing structure finally obtaining part rete probably in used etching program, partly or be even fully removed, thereby affected the function of the microelectromechanicdevices devices finally obtaining.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of microelectromechanicdevices devices and manufacture method thereof, to guarantee the structure rete integrality of micro-processing structure included in microelectromechanicdevices devices, and then guaranteed the functional of prepared microelectromechanicdevices devices.
According to an embodiment, the invention provides a kind of manufacture method of microelectromechanicdevices devices, comprising:
Semiconductor substrate is provided, comprises semi-conductor layer and be positioned at the interconnect structure on this semiconductor layer; Sequentially form a protective layer and a photoresist layer on this interconnect structure; In this photoresist layer, form a plurality of openings, those openings expose respectively a part for this protective layer; Implement one first etching program, take this photoresist layer is etching mask, removes this protective layer of exposing for those openings and this interconnect structure of below thereof, to form a plurality of the first grooves of a part of exposing this semiconductor layer; Remove this photoresist layer and expose this protective layer; Implement one second etching program, using this protective layer as etching mask, part is removed this semiconductor layer exposing for those first grooves, to form a plurality of the second grooves in this semiconductor layer; One upper cover substrate is provided, is attached at this protective layer to form one first composite base plate; One surface of this semiconductor layer that is not provided with those the second grooves in this first composite base plate of thinning, leaves the semiconductor layer once thinning; And implement one the 3rd etching program, part is removed this semiconductor layer through thinning to form one the 3rd groove within it, wherein the 3rd groove exposes and has connected those the second grooves, and in the region between those first grooves, those second grooves and the 3rd groove, definition has formed a micro-processing structure suspending.
According to another embodiment, the invention provides a kind of microelectromechanicdevices devices, comprising:
Semiconductor substrate, comprise semi-conductor layer and be positioned at the interconnect structure on this semiconductor layer, wherein this semiconductor layer has the first relative side and the second side, and this interconnect structure is arranged on the surface of this first side of this semiconductor layer, wherein in this interconnect structure, form a plurality of the first grooves, in this semiconductor layer, form a plurality of the second grooves, connect those the first grooves; One protective layer, is arranged on this interconnect structure; One upper cover substrate, is arranged on this protective layer; One the 3rd groove, be arranged in the part of the second side for this semiconductor layer, wherein the 3rd groove exposes and has connected those the second grooves, and this protective layer, this interconnect structure and this semiconductor layer in a region of those first grooves, those second grooves and the 3rd formation that groove defines formed a micro-processing structure suspending; And a hypophragm layer, be attached on the surface of this second side of this semiconductor layer, wherein those first grooves and those the second grooves and the 3rd groove have formed a confined air chamber between this upper cover substrate, this semiconductor substrate and this lower cover rete.
For above and other object of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate appended diagram, be described in detail below:
Accompanying drawing explanation
Fig. 1～Fig. 7 is a series of cutaway views, has shown the manufacture method according to the microelectromechanicdevices devices of one embodiment of the invention.
Main element symbol description
10～semiconductor substrate;
100～semiconductor layer;
100 '～through the semiconductor layer of thinning;
101～interconnect structure;
102～dielectric layer;
104～conductive layer;
106～weld pad;
110～protective layer;
112～photoresist layer;
112 '～through the photoresist layer of thinning;
120～opening;
130～etching program;
132～groove;
140～etching program;
142～groove;
150～upper cover substrate;
152～adhesion coating;
160～etching program;
162～wide groove;
The region of 164～micro-processing structure;
170～cutting process;
180～lower cover rete;
182～confined air chamber;
20O～composite base plate;
300～microelectromechanicdevices devices;
The angle of θ～dielectric layer and semiconductor layer;
D
1, D
2～the degree of depth.
The specific embodiment
Fig. 1～Fig. 7 is a series of cutaway views, shown the manufacture method according to the microelectromechanicdevices devices of one embodiment of the invention, for microelectromechanicdevices devices functional of guaranteeing the structure rete integrality of prepared micro-processing structure and guaranteeing to comprise this micro-processing structure.
Please refer to Fig. 1, first semiconductor substrate 10 is provided.As shown in Figure 1, semiconductor substrate 10 is not yet through the semiconductor wafer of over-segmentation, has been formed with and has substantially prepared but do not completed several integrated circuits region (not shown) of cutting apart on it.Object based on simplicity of illustration, in this making situation of micro-processing structure of the microelectromechanicdevices devices of partial display in an integrated circuit region only in Fig. 1.As shown in Figure 1, in the ic core panel region on semiconductor substrate 10, mainly comprise semi-conductor layer 100 and the interconnect structure 101 being located thereon.At this, the several conductive layers 104 and the weld pad 106 that in interconnect structure 101, mainly comprise dielectric layer 102 and be arranged at dielectric layer 102 interior zoness of different, and within conductive layer 104 is arranged at the same area substantially from the bottom to top and stackingly.And semiconductor layer 100 is for example a bulk silicon (bulk silicon), within the semiconductor layer 100 of in position locating and/or on be formed with as resistance, electric capacity, the passive device of inductance and/or fuse, as P channel fet (PFET), N channel fet (NFET), metal oxide semiconductor field effect is answered transistor (MOSFETs), CMOS complementary metal-oxide-semiconductor (CMOSs) transistor, high voltage transistor, and/or the combination of the active member of high frequency transistor and other elements and/or said elements, dielectric layer 102 can comprise as dielectric materials such as silica or silicon nitrides and have the thickness that is about 8～9 microns.
Based on simplifying accompanying drawing object, semiconductor element in integrated circuit region in Fig. 1 is shows in detail and only representing with a smooth semiconductor layer 100 not, and though interconnect structure 101 has only illustrated the structure of a plurality of conductive layers 104 of being arranged in dielectric layer 102 and weld pad 106 at this, in dielectric layer 102, can more arrange a plurality of as the conductive member (not shown) of conductive layer, conduction interlayer thing formed in connect thing, for as these a little conductive layers 104 and weld pad 106 and within being arranged at semiconductor layer 100 and/or on semiconductor element between electrically connect.Be positioned at semiconductor layer 100 and interconnect structure 101 and/or on aforementioned rete and the element CMOS complementary metal-oxide-semiconductor manufacture craft (standard CMOS process) that can adopt standard form, therefore be not described in detail in this its manufacturing process.
Then, on dielectric layer 102, smooth covering forms a protective layer 110 and a photoresist layer 112.At this, protective layer 110 adopts the dielectric material of silica, and its thickness is about 0.8～1.0 micron.Protective layer 110 is preferably used the material of same type with dielectric layer 102, thereby can have comparatively approaching etching selectivity.In addition, photoresist layer 112 is such as being to wait to be common in applied photo anti-corrosion agent material in microelectromechanicdevices devices making, and its thickness is about 5～15 microns.
Please refer to Fig. 2, then implement a lithographic procedures (not shown), with at the several openings 120 of the interior formation of photoresist layer 112.These a little openings 120 lay respectively at the surface that in a part for the dielectric layer 102 between these a little conductive layers 104, also part has been exposed protective layer 110.Then implement an etching program 130; as an anisotropic etching program of reactive ion etching (RIE) program; to remove protective layer 110 and the part dielectric layer 102 under it that a little openings 120 are exposed and to stop on semiconductor layer 100 for this reason; and then formed several grooves 132 dielectric layer 102 is interior, below also claim the first groove.At this; the etch reactants of using in etching program 130 (etchants) is except having removed dielectric layer 102; it has also partly removed a part for photoresist layer 112, thereby on the surface of protective layer 110, has left the photoresist layer 112 ' through thinning.132 of formed grooves have exposed a part for semiconductor layer 100, and between the dielectric layer 102 of adjacent trenches 132 and semiconductor layer 100, preferably there is the angle theta that is greater than 85 °, for guaranteeing that each groove 132 can have for the profile of cardinal principle perpendicular to semiconductor layer 100.
Please refer to Fig. 3; then to be positioned at protective layer 110 lip-deep after the photoresist layer 112 ' of thinning to remove to implement an etching program (not shown); then implement an etching program 140; if one of deep reactive ion etch (DRIE) the program property such as non-is to etching program; take and remove semiconductor layer 100 parts of being exposed as groove 132 (seeing Fig. 2); and formed several grooves 142 semiconductor layer 100 is interior, below also claim the second groove.In etching program 140, the effect that protective layer 110 also has etch stop layer at this, take and avoid the dielectric layer 102 as protective layer 102 is covered further to be removed in etching program 140.The groove 142 being formed in semiconductor layer 100 has apart from the depth D 1 on approximately 20～50 microns, semiconductor layer 100 surface.
Please refer to Fig. 4, then on protective layer 110 surfaces of part, form an adhesion coating 152, it can comprise as melted the sticky material of piece (frit).One upper cover substrate 150 is then provided and on semiconductor substrate 10 and by adhesion coating 152, adheres mutually with semiconductor substrate 10, to form a composite base plate 200 as shown in Figure 4.At this, upper cover substrate 150 is for example a wafer of silicon or glass material.
Please refer to Fig. 5, after composite base plate shown in Fig. 4 200 is inverted up and down, then adopting upper cover substrate 150 is that a thinning program (not shown) is not implemented to be provided with a surface of groove 142 for semiconductor layer 100 in a grip part, be for example a cmp program, and then obtain the semiconductor layer 100 ' through thinning.Then implement an etching program 160, as an anisotropic etching program of dark reactive ion etching (DRIE) program, with in the formation one wide groove 162 through the semiconductor layer 100 ' of thinning in of part, below also claim the 3rd groove.As shown in Figure 5, this wide groove 162 has substantially exposed to be previously formed at the several grooves 142 in semiconductor layer and to be attached thereto and has connect.So, after wide groove 162 forms, just produce the micro-processing structure suspending as shown in region 164.At this, micro-processing structure shown in region 164 has mainly comprised semiconductor layer 100 ', dielectric layer 102 and the several conductive layers 104 that are positioned at dielectric layer 102, because these a little conductive layers 104 substantially arrange abreast and be that dielectric layer 102 is separated mutually, therefore micro-processing structure of the suspension of region 164 shown in interior can be used as the use of a capacitor sensor.Also it is not limited with above-mentioned enforcement situation the enforcement situation of micro-processing structure that one shown in this region 164 suspends.Micro-processing structure in region 164 also can be different from Fig. 5 shown in situation and there is other members, to show other different functionalities.
Please refer to Fig. 6, after structure is inverted up and down as shown in Figure 5, then implement a cutting process 170, to expose, form the weld pad 106 that is positioned at dielectric layer 102.At this, cutting process 170 is for example laser cutting or machine cuts supervisor, in cutting process 170 part removed the upper cover substrate 150 that is positioned at above weld pad 106, protective layer 110 with a part for dielectric layer 102 until exposed the surface of weld pad 106.
Please refer to Fig. 7, then in structure as shown in Figure 6 contiguous wide groove 162 places through the upper hypophragm layer 180 that attaches in the semiconductor layer 100 ' surface of thinning, it is for example a chip attach film (die attached film, DAF).The material of lower cover rete 180 is such as a dry type film that is the insulation such as PUR (hot melt adhesive) material, so with composite base plate 200 in conjunction with forming another composite base plate (not shown)s.After lower cover rete 180 forms, then for this composite base plate, implement a cutting process (not shown), be for example wafer cutting process, forming several independently microelectromechanicdevices devices 300 by structure cuts that member was combined to form such as upper cover substrate, semiconductor substrate and lower cover retes.As shown in Figure 7, after cutting is formed at microelectromechanicdevices devices 300, through semiconductor layer 100 ' of thinning, just defines and formed a confined air chamber 182 with being arranged between upper cover substrate 150 on its two apparent surface and lower cover rete 180 in it.This confined air chamber 182 has approximately one atmospheric pressure, and it provides the appropriate mobile space of micro-processing structure of the suspension that is positioned at region 164, thereby guarantees the sensing function of this micro-processing structure.And microelectromechanicdevices devices 300 as shown in Figure 7 can be more depending on the demand of follow-up manufacture craft and it is arranged on a base plate for packaging (not shown), and by the juncture engaging as routing, connect a bonding wire (not shown) in base plate for packaging with and the weld pad 106 that exposes between, and then formed the electrical connection between microelectromechanicdevices devices 300 and base plate for packaging.
Please refer to Fig. 7, shown the microelectromechanicdevices devices according to one embodiment of the invention, it comprises:
Semiconductor substrate, comprise semi-conductor layer (through the semiconductor layer 100 ' of thinning) and be positioned at the interconnect structure (interconnect structure 101) on this semiconductor layer, wherein this semiconductor layer has the first relative side and the second side, and this interconnect structure is arranged on the surface of this first side of this semiconductor layer; One protective layer (protective layer 110), is arranged on this interconnect structure; A plurality of the first grooves 132 and a plurality of the second grooves 142 that are connected the first groove 132, be arranged in a part for this protective layer, this interconnect structure 101 and this semiconductor layer 100 ' separatedly; One upper cover substrate (upper cover substrate 150), is arranged on this protective layer; One the 3rd groove 162, be arranged in the part of the second side for this semiconductor layer, wherein the 3rd groove 162 exposes and has connected those the second grooves 142, and has formed the micro-processing structure (member region 164 in) that suspend with this protective layer, this interconnect structure 101 that the 3rd groove 162 defines in the region forming with this semiconductor layer 100 ' at those first grooves 132, those second grooves 142; An and hypophragm layer (180), be attached on the surface of this second side of this semiconductor layer, wherein those first grooves 132, those second grooves 142 and those the 3rd grooves 162 have formed a confined air chamber (confined air chamber 182) between upper cover substrate 150, this semiconductor substrate and this lower cover substrate 180.
Known with reference to the manufacture method of the microelectromechanicdevices devices shown in Fig. 1～Fig. 7 and prepared microelectromechanicdevices devices; manufacture method provided by the present invention is the use as etching mask by the protective layer of extra setting and photoresist layer, to guarantee the integrality of its theca interna and profile in micro-processing structure is made.Therefore contribute to promote the reliability of the prepared microelectromechanicdevices devices that comprises micro-processing structure like this.
Moreover, because the making of microelectromechanicdevices devices of the present invention can be passed through the making of wafer level and the enforcement of encapsulation technology, thereby can complete making and the encapsulation for micro-machine component and its application integrated circuit element of microelectromechanicdevices devices, therefore do not need to implement extra component encapsulation step simultaneously.Therefore, the required most of manufacture craft of microelectromechanicdevices devices of the present invention can complete in advance in wafer foundries, and only needs to deliver to encapsulation factory and carry out final wafer and cut apart manufacture craft, so contributes to the reduction of the manufacturing cost of microelectromechanicdevices devices.
Although disclosed the present invention in conjunction with above preferred embodiment; yet it is not in order to limit the present invention; anyly be familiar with this operator; without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (13)
1. a manufacture method for microelectromechanicdevices devices, comprising:
Semiconductor substrate is provided, comprises semi-conductor layer and be positioned at the interconnect structure on this semiconductor layer;
Sequentially form a protective layer and a photoresist layer on this interconnect structure;
In this photoresist layer, form a plurality of openings, those openings expose respectively a part for this protective layer;
Implement one first etching program, take this photoresist layer is etching mask, removes this protective layer of exposing for those openings and this interconnect structure of below thereof, to form a plurality of the first grooves of a part of exposing this semiconductor layer;
Remove this photoresist layer and expose this protective layer;
Implement one second etching program, using this protective layer as etching mask, part is removed this semiconductor layer exposing for those first grooves, to form a plurality of the second grooves in this semiconductor layer;
One upper cover substrate is provided, is attached at this protective layer to form one first composite base plate;
One surface of this semiconductor layer that is not provided with those the second grooves in this first composite base plate of thinning, leaves the semiconductor layer once thinning; And
Implement one the 3rd etching program, part is removed this semiconductor layer through thinning to form in the inner one the 3rd groove, wherein the 3rd groove exposes and has connected those the second grooves, and in the region between those first grooves, those second grooves and the 3rd groove, definition has formed a micro-processing structure suspending.
2. the manufacture method of microelectromechanicdevices devices as claimed in claim 1, also comprises:
Implement one first cutting process, part is removed a part for the dielectric layer of this upper cover substrate, this protective layer and this interconnect structure, to expose the weld pad in this interconnect structure;
One hypophragm layer is provided, be attached at be provided with the 3rd groove this through the surface of the semiconductor layer of thinning, to form one second composite base plate; And
Implement one second cutting process, to cut this second composite base plate and to form, comprise micro-processing structure of this suspension and a microelectromechanicdevices devices of this weld pad.
3. the manufacture method of microelectromechanicdevices devices as claimed in claim 1, wherein this interconnect structure comprises a dielectric layer and a plurality of conductive layer, and this protective layer and this dielectric layer have close etching selectivity.
4. the manufacture method of microelectromechanicdevices devices as claimed in claim 3, wherein micro-processing structure of this suspension comprises the capacitor sensor being comprised of this dielectric layer and those conductive layers.
5. the manufacture method of microelectromechanicdevices devices as claimed in claim 1, wherein this first etching program is reactive ion etching program, and this second etching program is deep reactive ion etch program, and the 3rd etching program is deep reactive ion etch program.
6. the manufacture method of microelectromechanicdevices devices as claimed in claim 2, wherein this upper cover substrate comprises silicon or glass, this lower cover rete is a chip attach film.
7. the manufacture method of microelectromechanicdevices devices as claimed in claim 2, wherein this first cutting process is laser cutting program or machine cuts program, this second cutting process is a wafer cutting process.
8. the manufacture method of microelectromechanicdevices devices as claimed in claim 2, has wherein formed a confined air chamber between this upper cover substrate, this semiconductor substrate and this lower cover rete.
9. a microelectromechanicdevices devices, comprising:
Semiconductor substrate, comprise semi-conductor layer and be positioned at the interconnect structure on this semiconductor layer, wherein this semiconductor layer has the first relative side and the second side, and this interconnect structure is arranged on the surface of this first side of this semiconductor layer, wherein in this interconnect structure, form a plurality of the first grooves, in this semiconductor layer, form a plurality of the second grooves, connect those the first grooves;
Protective layer, is arranged on this interconnect structure;
Upper cover substrate, is arranged on this protective layer;
The 3rd groove, be arranged in the part of the second side for this semiconductor layer, wherein the 3rd groove exposes and has connected those the first grooves, and this protective layer, this interconnect structure and this semiconductor layer in a region of those first grooves, those second grooves and the 3rd formation that groove defines formed a micro-processing structure suspending; And
Lower cover rete, is attached on the surface of this second side of this semiconductor layer, and wherein those first grooves, those second grooves and the 3rd groove have formed a confined air chamber between this upper cover substrate, this semiconductor substrate and this lower cover rete.
10. microelectromechanicdevices devices as claimed in claim 9, wherein this interconnect structure comprises a weld pad, and this upper cover substrate and this protective layer partly cover this interconnect structure but do not cover this weld pad.
11. microelectromechanicdevices devices as claimed in claim 9, wherein this upper cover substrate comprises glass or silicon, this lower cover rete is a chip attach film.
12. microelectromechanicdevices devices as claimed in claim 11, wherein this chip attach film is a dry type film.
13. microelectromechanicdevices devices as claimed in claim 9, several conductive layers that wherein this interconnect structure comprises a dielectric layer and is positioned at this dielectric layer, using as a capacitor sensor.
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| CN103575260B (en) * | 2012-07-19 | 2017-06-16 | 水木智芯科技（北京）有限公司 | A kind of gyroscope and its machining manufacture |
| CN103342338B (en) * | 2013-07-22 | 2016-08-10 | 苏州晶方半导体科技股份有限公司 | The wafer-level packaging method of Micro Electronic Mechanical System die and encapsulating structure |
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