CN102157553A - Structure of asymmetrical semi-conductor and forming method thereof - Google Patents
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Abstract
The invention discloses a structure of an asymmetrical semi-conductor. The structure comprises a substrate, a grid stack, a side wall, a source electrode and a drain electrode, wherein the grid stack is formed on the substrate, and comprises one or a plurality of grid dielectric layers and grid electrode layers; the side wall is formed at the side wall of the grid stack; the source electrode and the drain electrode are formed in the substrate and are positioned at the side wall of the grid stack; and the thickness of an equivalent oxide layer at one side of the source electrode layer for the grid dielectric layer is relatively lower, and the thickness of the equivalent oxide layer at one side of the drain electrode is relatively higher. Relative dielectric constants at two ends of the grid dielectric layer are different due to ion implantation of the semi-conductor structure, thus capacitance per area of the source electrode/drain electrode is different, EOTs (equivalent oxide thickness) are different, the working requirements of the drain electrode and the source electrode can be satisfied according to the invention, and the efficiency of the drain electrode and the source electrode can be played maximally, thus the working property of the semi-conductor device can be improved on the whole.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly structure of a kind of asymmetrical semiconductor and forming method thereof.
Background technology
At present, FET (Field Effect Transistor, field-effect transistor) is one of the most widely used assembly in the integrated circuit, because field effect transistor circuitry can be carried out multiple different function, and the manufacturing of field-effect transistor has the reproducibility and the predictability of height, its another advantage is that this structure can be made very for a short time, and can is closely aligned and install.
Typical field-effect transistor is made up of substrate, source electrode, drain electrode and the grid that can conduct electricity.Wherein, source electrode and drain electrode are positioned at the both sides of channel region, and grid is then separated by grid oxic horizon and channel region.Field-effect transistor grows in the surface of silicon or other Semiconductor substrate, has the doping of first conductivity type.Generate one deck gate oxide level at substrate surface, normally utilize thermal oxidation technology to generate evenly oxide skin(coating) closely of one deck, it has the thickness that can preset and can preset and the fixed charge of low degree, follow the deposit spathic silicon layer and be etched with the formation grid, can utilize in deposition process and to mix or use diffusion technology, or after deposition, carry out ion and inject, give this polysilicon layer conductivity.Usually, can generate one deck conductive materials above polysilicon layer, for example metal or metal silicide are to reduce the resistivity of grid.Be protective layer with the grid again, utilize the admixture of second conductivity type that substrate is carried out the ion injection, to make source electrode and drain electrode, this source electrode, drain electrode and channel region are self-aligned to grid.
At present, typical MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor, metal-oxide layer-semiconductor-field-effect transistor) all is made as the device of grid oxic horizon symmetry, but consider that the function of source electrode and drain electrode is different in AC and DC device, so wish to form in the practical operation source electrode and the asymmetric MOSFET structure of drain electrode, therefore how making asymmetric MOSFET structure is a problem demanding prompt solution.
Summary of the invention
At the deficiencies in the prior art, the objective of the invention is to provide a kind of structure and forming method thereof of asymmetrical semiconductor of favorable working performance.
To achieve these goals, the invention provides a kind of asymmetrical semiconductor structure, comprising: substrate; The grid that are formed on the described substrate pile up, and described grid pile up and comprise one or more gate dielectric layers and gate electrode layer; Be formed on one or more side walls that described grid pile up sidewall; And be formed in the described substrate, be positioned at source electrode and drain electrode that described grid pile up sidewall; Wherein said gate dielectric layer is relatively low at the equivalent oxide thickness of source area one side, and the equivalent oxide thickness of one side is higher relatively in the drain region.
The invention has the beneficial effects as follows, this semiconductor device adopts asymmetrical structure, corresponding with the actual functional capability of drain electrode and source electrode, can bring into play the function of drain electrode and source electrode better, thereby greatly improve the service behaviour of semiconductor device on the whole, the electric capacity that can reduce to drain not only, but also can help to improve the carrier density of source electrode, and the drive current that improves MOSFET, thereby the DC and the AC performance of raising device.
Correspondingly, the present invention also provides a kind of formation method of asymmetrical semiconductor structure, may further comprise the steps: a. forms substrate; B. on described substrate, form one or more side walls and source electrode and the drain electrode that pseudo-grid pile up, described grid pile up sidewall; C. remove described pseudo-grid and pile up, to form opening; D. form one or more gate dielectric layers in described opening, described gate dielectric layer is relatively low at the equivalent oxide thickness of source area one side, and the equivalent oxide thickness of one side is higher relatively in the drain region; E. forming new grid on described gate dielectric layer piles up.
Adopt the ion implantation concentration that changes gate dielectric layer to change the EOT at gate dielectric layer two ends according to formation method of the present invention, thereby make that the EOT at gate dielectric layer two ends is inequality, the different operating needs that can adapt to drain electrode and source electrode, therefore, can greatly improve the service behaviour of this semiconductor device, the electric capacity that can reduce to drain not only, but also can help to improve the carrier density of source electrode, and the drive current that improves MOSFET, thereby the DC and the AC performance of raising device.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1-the 4th is according to the schematic diagram in each stage of the asymmetrical semiconductor device of first embodiment of the invention;
Fig. 5-the 7th is according to the schematic diagram in each stage of the asymmetrical semiconductor device of second embodiment of the invention;
Fig. 8-the 10th is according to the schematic diagram in each stage of the asymmetrical semiconductor device of third embodiment of the invention; And
Figure 11 is the flow chart according to the manufacture method of embodiments of the invention asymmetrical semiconductor device.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
The present invention mainly is by forming the different gate dielectric layer of equivalent oxide thickness (EOT, Equivalent OxideThick) to reach the purpose that forms asymmetric MOSFET structure.In addition, in the present invention, can select the high relatively side of EOT as drain electrode, select the low relatively side of EOT as source electrode, the electric capacity that can reduce to drain so not only, but also can help to improve the carrier density of source electrode, and and the drive current that improves MOSFET, thus the DC and the AC performance of device improved.
Asymmetrical semiconductor structure proposed by the invention comprises substrate 101, and the grid that are formed on the described substrate pile up 118, and described grid pile up and comprise one or more gate dielectric layers 111,112 and gate electrode layer 114; Be formed on one or more side walls 106 that described grid pile up sidewall; And be formed in the described substrate, be positioned at source electrode 104 and drain electrode 102 that described grid pile up both sides; Wherein said gate dielectric layer 111,112 is relatively low at the equivalent oxide thickness of source area 104 1 sides, and the equivalent oxide thickness of 102 1 sides is higher relatively in the drain region.
Utilize the grid alternative techniques to carry out the manufacturing of semiconductor device according to the formation method of asymmetrical semiconductor structure of the present invention, may further comprise the steps: form substrate; On described substrate, form one or more side walls and source electrode and the drain electrode that pseudo-grid pile up, described grid pile up sidewall; Remove described pseudo-grid and pile up, to form opening; Form one or more gate dielectric layers in described opening, described gate dielectric layer is relatively low at the equivalent oxide thickness of source area one side, and the equivalent oxide thickness of one side is higher relatively in the drain region; Forming new grid on described gate dielectric layer piles up.
Described gate dielectric layer can be one deck or multilayer, and in first and second embodiment, gate dielectric layer is one deck, and it can be the boundary layer on substrate 111, and described boundary layer 111 can be an oxide skin(coating).In the 3rd embodiment, gate dielectric layer can be a multilayer, for example can be boundary layer 111 and high K medium layer 112, and this will be described in detail hereinafter.
First embodiment
In the present embodiment, can make asymmetrical semiconductor structure of the present invention by the following method.The present invention adopts the grid alternative techniques, as shown in figure 11, at first makes semiconductor device according to traditional grid alternative techniques flow process, in step 101, forms substrate 100.In the present embodiment, substrate 100 comprises the silicon substrate (for example wafer) that is arranged in crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 100 can comprise various doping configurations.The substrate 100 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.
In step 102, the pseudo-grid of formation pile up (not shown) on described substrate 100, described pseudo-grid pile up the one or more side walls 106 and the source electrode 104 of sidewall and drain 102.
Pseudo-grid are stacked as sacrifice layer, can comprise pseudo-gate dielectric layer and dummy gate layer.Described pseudo-gate dielectric layer can be thermal oxide layer, comprises silica, silicon nitride, for example silicon dioxide.Dummy gate layer can for example be a polysilicon.In one embodiment, dummy gate layer comprises amorphous silicon.Pseudo-gate dielectric layer and dummy gate layer can be by the MOS technical matters, and for example deposition, photoetching, etching and/or other suitable methods form.
Source/drain region 104,102 can be injected p type or n type alloy or impurity and form to substrate 100 by the transistor arrangement according to expectation.Source/drain region 104,102 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 104,102, thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out.
Cover described pseudo-grid and pile up formation side wall 106.Side wall 106 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof, and/or other suitable materials form.Side wall 106 can have sandwich construction, and side wall has double-decker in the present embodiment, i.e. side wall 106-1 and 106-2.Side wall 106 can form by the method that comprises the dielectric substance that deposition is suitable.Side wall 106 can have one section to cover pseudo-grid and pile up, and this structure can obtain with the technology that those skilled in the art knew.In other embodiments, side wall 106 also can not cover pseudo-grid and piles up.
Especially, can also on described substrate, deposit and form interlayer dielectric layer (ILD) 108, the described silica (as Pyrex, boron-phosphorosilicate glass etc.) and the silicon nitride (Si3N4) that can be but be not limited to for example unadulterated silica (SiO2), mix.Described interlayer dielectric layer 108 for example can use, and chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD) and/or other suitable methods such as technology form.Interlayer dielectric layer 108 can have sandwich construction.In one embodiment, the thickness range of interlayer dielectric layer 108 is about 30 to 90 nanometers.
Then, to described interlayer dielectric layer 108 and described side wall 106 planarization to expose the upper surface of described dummy grid.For example can remove described interlayer dielectric layer 108, until the upper surface that exposes described side wall 106 by chemico-mechanical polishing (CMP) method.Then more described side wall 106 is carried out chemico-mechanical polishing or reactive ion etching, thereby remove the upper surface of described side wall 106, thereby expose described dummy gate layer.
Above step is all made according to traditional grid alternative techniques flow process, therefore in order to simplify description of the invention, not shown in figures, but those skilled in the art will be appreciated that, foregoing description also is not intended to restriction the present invention, the present invention can adopt other technologies that are different from above-mentioned technological process to make, as long as it can be applied in the grid alternative techniques.
Then,, remove described pseudo-grid and pile up, to form opening 120 in step 103.
In step 104, in described opening 120, form one or more gate dielectric layers, described gate dielectric layer is relatively low at the equivalent oxide thickness of source area 104 1 sides, and the equivalent oxide thickness of 102 1 sides is higher relatively in the drain region.In the present embodiment, described gate dielectric layer is one deck, and specifically, described gate dielectric layer is a boundary layer 111, and it can be oxide skin(coating).Can form described boundary layer 111 as follows.As shown in Figure 1, carrying out ion from 120 pairs of substrates of described opening injects to form ion implanted region 110, described ion is infused in source area 104 1 sides and has higher relatively ion implantation concentration, 102 1 sides have relatively low ion implantation concentration in the drain region, the change in concentration of in Fig. 1, representing ion implanted region 110 by progressive greyscale pattern, the higher relatively ion implantation concentration of dark expression, the ion implantation concentration that the light color expression is relatively low.This can inject and realize by carry out angled ion from opening, for example can carry out ion to the substrate below the opening with the angle that becomes about 20-60 degree with vertical direction injects, preferably described ion is injected to low energy ion and injects, and the degree of depth that described ion injects is preferably less than about 5nm.The element that ion injects comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element that injects should have to compare with the material of substrate and has higher relative dielectric constant, and substrate is a silicon substrate in the present embodiment.Then, as shown in Figure 2, carry out the heat growth, to form boundary layer 111.Owing to have higher relatively ion implantation concentration at source area 104,102 have relatively low ion implantation concentration in the drain region, therefore in the oxygen environment, carry out in the process of heat growth, having higher ion implantation concentration is that the higher side of relative dielectric constant will have higher unit-area capacitance, and formed equivalent oxide thickness also can be less relatively; And have low ion implantation concentration is that the lower side of relative dielectric constant will have lower unit-area capacitance, and formed equivalent oxide thickness also can be relatively large.The equivalent oxide thickness that is source area 104 1 sides will be less than the equivalent oxide thickness of drain region 102 1 sides.
Then, as shown in Figure 3, Figure 4, on described boundary layer 111, form new grid and pile up 118, for example can form high K medium layer 112 and metal gate layers 114 in step 105.
High K medium layer 112 is high-k (high k) material.In one embodiment, high k material comprises hafnium oxide (HfO
2).The high k material of other examples comprises HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and combination thereof, and/or other suitable materials.High K medium layer 112 can comprise that about 12 dusts are to the thickness between the 35 dust scopes.High K medium layer 112 can form by the technology of for example chemical vapor deposition (CVD) or ald (ALD).High K medium layer 112 can also have sandwich construction, comprises the more than one layer with above-mentioned material.
Form metal gate layers 114 afterwards on described high K medium layer 112, metal gate material can comprise one or more material layers, and lining for example provides material, gate material and/or other suitable materials of appropriate work function number to grid.Can from the group that comprises following column element, select one or more elements to deposit for the N type semiconductor device: TiN, TiAlN, TaAlN, TaN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xAnd the combination of these materials; Can from the group that comprises following column element, select one or more elements to deposit for the P type semiconductor device: TiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xAnd the combination of these materials.
Carry out chemico-mechanical polishing (CMP) technology at last, pile up 118 to form grid.
Like this, high EOT end can help to reduce the electric capacity of drain electrode as draining, and low EOT holds the carrier density that can help to increase source electrode as source electrode, also can increase drive current simultaneously.Therefore, this set can increase the DC (Direct Current, direct current) and AC (the Alternating Current exchanges) performance of this semiconductor device.
Second embodiment
The aspect that below will be only be different from first embodiment with regard to second embodiment is set forth.The part of Miao Shuing not will be understood that with first embodiment and has adopted identical step, method or technology to carry out, and therefore repeats no more once more.In according to a second embodiment of the present invention, described gate dielectric layer is one deck, and specifically, described gate dielectric layer is a boundary layer 111, and it can be oxide skin(coating).Can form described boundary layer 111 by following alternative steps.Step 101-103 is the step identical with first embodiment, as shown in Figure 5, at first device is carried out the heat growth after step 103, to form boundary layer 111 in the substrate below opening 100.Then in step 104, as shown in Figure 6, carrying out ion from 120 pairs of boundary layers of described opening 111 injects dopant is injected boundary layer 111, described ion is infused in source area 104 1 sides and has higher relatively ion implantation concentration, 102 1 sides have relatively low ion implantation concentration in the drain region, the change in concentration of in Fig. 6, representing boundary layer 111 by progressive greyscale pattern, the higher relatively ion implantation concentration of dark expression, the ion implantation concentration that the light color expression is relatively low.This can inject and realize by carry out angled ion from opening, for example can carry out ion to the boundary layer 111 of opening below with the angle that becomes about 20-60 degree with vertical direction and inject, and preferably described ion is injected to low energy ion and injects.The element that ion injects comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element that injects should have to compare with the material of substrate 100 and has higher relative dielectric constant, and boundary layer is an oxide skin(coating) in the present embodiment.Then, can selectively the anneal dopant that injects with active ions and repair ion and inject the defective that is caused.Owing to have higher relatively ion implantation concentration at source area 104,102 have relatively low ion implantation concentration in the drain region, therefore, having higher ion implantation concentration is that the higher side of relative dielectric constant will have higher unit-area capacitance, and formed equivalent oxide thickness also can be less relatively; And have low ion implantation concentration is that the lower side of relative dielectric constant will have lower unit-area capacitance, and formed equivalent oxide thickness also can be relatively large.The equivalent oxide thickness that is source area 104 1 sides will be less than the equivalent oxide thickness of drain region 102 1 sides.
Then with first embodiment in the same manner, in step 105, as shown in Figure 7, on described boundary layer 111, form new high K medium layer 112 and metal gate layers 114, pile up 118 to form grid.
The 3rd embodiment
The aspect that below will be only be different from first embodiment with regard to the 3rd embodiment is set forth.The part of Miao Shuing not will be understood that with first embodiment and has adopted identical step, method or technology to carry out, and therefore repeats no more once more.In a third embodiment in accordance with the invention, described gate dielectric layer is two-layer, and specifically, described gate dielectric layer is boundary layer 111 and high K medium layer 112.Can form gate dielectric layer by following alternative steps.Step 101-103 is the step identical with first embodiment, as shown in Figure 8, at first device is carried out the heat growth after step 103, to form boundary layer 111 in the substrate below opening 100.And on described boundary layer 111, depositing high K medium layer 112, high K medium layer 112 is high-k (high k) material.In one embodiment, high k material comprises hafnium oxide (HfO
2).The high k material of other examples comprises HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and combination thereof, and/or other suitable materials.High K medium layer 112 can form by the technology of for example chemical vapor deposition (CVD) or ald (ALD).Then in step 104, as shown in Figure 9, carrying out ion from 120 pairs of high K medium layers of described opening 112 injects dopant is injected the boundary layer 111 of high K medium layer 112 below, described ion is infused in source area 104 1 sides and has higher relatively ion implantation concentration, 102 1 sides have relatively low ion implantation concentration in the drain region, the change in concentration of in Fig. 9, representing boundary layer 111 by progressive greyscale pattern, the higher relatively ion implantation concentration of dark expression, the ion implantation concentration that the light color expression is relatively low.This can inject and realize by carry out angled ion from opening, for example can carry out ion to the substrate of opening below with the angle that becomes about 20-60 degree with vertical direction and inject, and preferably described ion is injected to low energy ion and injects.The element that ion injects comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element that injects should have to compare with the material of substrate 100 and has higher relative dielectric constant.Then, can selectively the anneal dopant that injects with active ions and repair ion and inject the defective that is caused.Owing to have higher relatively ion implantation concentration at source area 104,102 have relatively low ion implantation concentration in the drain region, therefore, having higher ion implantation concentration is that the higher side of relative dielectric constant will have higher unit-area capacitance, and formed equivalent oxide thickness also can be less relatively; And have low ion implantation concentration is that the lower side of relative dielectric constant will have lower unit-area capacitance, and formed equivalent oxide thickness also can be relatively large.The equivalent oxide thickness that is source area 104 1 sides will be less than the equivalent oxide thickness of drain region 102 1 sides.
Then with first embodiment in the same manner, in step 105, as shown in figure 10, on described high K medium layer 112, form new metal gate layers 114, pile up 118 to form grid.
Therefore, gate dielectric layer can be the common sandwich construction of forming of oxide skin(coating), high K dielectric layer or two media layer.For the gate dielectric layer that EOT from one end to the other side gradually changes, can select the high relatively end of EOT as drain electrode, and select the low relatively end of EOT as source electrode.Like this, high EOT end can help to reduce the electric capacity of drain electrode as draining, and low EOT holds the carrier density that can help to increase source electrode as source electrode, also can increase drive current simultaneously.Therefore, this set can increase the DC (Direct Current, direct current) and AC (AlternatingCurrent exchanges) performance of this semiconductor device.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, claims of the present invention are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (16)
1. asymmetrical semiconductor structure comprises:
Substrate;
The grid that are formed on the described substrate pile up, and described grid pile up and comprise one or more gate dielectric layers and gate electrode layer;
Be formed on one or more side walls that described grid pile up sidewall; And
Be formed in the described substrate, be positioned at source electrode and drain electrode that described grid pile up sidewall; Wherein
Described gate dielectric layer is relatively low at the equivalent oxide thickness of source area one side, and the equivalent oxide thickness of one side is higher relatively in the drain region.
2. asymmetrical semiconductor structure as claimed in claim 1 is characterized in that, described gate dielectric layer is boundary layer and/or high K medium layer.
3. asymmetrical semiconductor structure as claimed in claim 2, it is characterized in that the ion that described equivalent oxide layer is injected by the ion that gate dielectric layer is carried out relative higher concentration in source area one side and one side is carried out relatively low concentration to gate dielectric layer in the drain region injects and forms.
4. asymmetrical semiconductor structure as claimed in claim 3 is characterized in that, described ion is injected to angled ion and injects.
5. asymmetrical semiconductor structure as claimed in claim 3, the element that ion injects comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.
6. as each described asymmetrical semiconductor structure of claim 3-5, it is characterized in that the degree of depth that described ion injects is less than about 5nm.
7. asymmetrical semiconductor structure as claimed in claim 2 is characterized in that, described boundary layer is an oxide skin(coating).
8. asymmetrical semiconductor structure as claimed in claim 7 is characterized in that, described oxide skin(coating) forms by substrate being carried out carry out the heat growth after angled ion injects.
9. the formation method of an asymmetrical semiconductor structure is characterized in that, may further comprise the steps:
A. form substrate;
B. on described substrate, form one or more side walls and source electrode and the drain electrode that pseudo-grid pile up, described grid pile up sidewall;
C. remove described pseudo-grid and pile up, to form opening;
D. form one or more gate dielectric layers in described opening, described gate dielectric layer is relatively low at the equivalent oxide thickness of source area one side, and the equivalent oxide thickness of one side is higher relatively in the drain region;
E. forming new grid on described gate dielectric layer piles up.
10. the formation method of asymmetrical semiconductor structure as claimed in claim 9 is characterized in that, described gate dielectric layer is boundary layer and/or high K medium layer.
11. the formation method of asymmetrical semiconductor structure as claimed in claim 10 is characterized in that,
Described steps d comprises: from described opening substrate is carried out ion and inject, described ion is infused in source area one side and has higher relatively ion implantation concentration, and one side has relatively low ion implantation concentration in the drain region;
Carry out the heat growth to form boundary layer;
Described step e comprises: deposition high K medium layer and gate electrode on described boundary layer.
12. the formation method of asymmetrical semiconductor structure as claimed in claim 10 is characterized in that, also comprises described device is carried out the heat growth to form the step of boundary layer in the substrate below described opening after described step c;
Described steps d comprises: from described opening boundary layer is carried out ion and inject, described ion is infused in source area one side and has higher relatively ion implantation concentration, and one side has relatively low ion implantation concentration in the drain region;
Described step e comprises: deposition high-k gate dielectric layer and gate electrode on described boundary layer.
13. the formation method of asymmetrical semiconductor structure as claimed in claim 10, it is characterized in that, after described step c, also comprise described device carried out heat growth forming boundary layer in the substrate below described opening, and on described boundary layer deposition high K medium layer;
Described steps d comprises: from described opening the high K medium layer is carried out ion and inject dopant is injected the boundary layer of high K medium layer below, described ion is infused in source area one side and has higher relatively ion implantation concentration, and one side has relatively low ion implantation concentration in the drain region;
Described step e comprises: deposit gate electrode on described high K medium layer.
14. the formation method as each described asymmetrical semiconductor structure of claim 11-13 is characterized in that, described ion is injected to angled ion and injects.
15. the formation method as each described asymmetrical semiconductor structure of claim 11-13 is characterized in that, the element that ion injects comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.
16. the formation method of asymmetrical semiconductor structure as claimed in claim 11 is characterized in that, the degree of depth that described ion injects is less than about 5nm.
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| CN106876274A (en) * | 2015-12-11 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN108122760A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN115084245A (en) * | 2022-07-25 | 2022-09-20 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method thereof and chip |
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| US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
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| CN103187278A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Manufacturing method of MOS field effect transistor and MOS field effect transistor |
| CN103187278B (en) * | 2011-12-28 | 2016-04-27 | 北大方正集团有限公司 | A kind of manufacture method of metal-oxide-semiconductor and a kind of metal-oxide-semiconductor |
| CN106876274A (en) * | 2015-12-11 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN108122760A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108122760B (en) * | 2016-11-30 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN115084245A (en) * | 2022-07-25 | 2022-09-20 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method thereof and chip |
| CN115084245B (en) * | 2022-07-25 | 2023-01-17 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method thereof and chip |
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