CN102201437A - Trench insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Trench insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN102201437A CN102201437A CN2010101495130A CN201010149513A CN102201437A CN 102201437 A CN102201437 A CN 102201437A CN 2010101495130 A CN2010101495130 A CN 2010101495130A CN 201010149513 A CN201010149513 A CN 201010149513A CN 102201437 A CN102201437 A CN 102201437A
- Authority
- CN
- China
- Prior art keywords
- emitter region
- base
- trench
- base contact
- trench gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a trench insulated gate bipolar transistor (IGBT) device. According to the invention, an emitter region-base region contact doping zone with a P<+> type is included. The doping zone is in a P-type base and at least encompasses the lowest part of an emitter region-base region contact trench. The concentration of the majority carriers in the emitter region-base region contact doping zone is higher than that of the P-type base, and the emitter region-base region contact doping zone keeps a predetermined distance from a channel region nearby trench gates, so that it can be guaranteed that an emitter electrode-base electrode resistor can be reduced under the condition that a grid electrode- emitter electrode threshold voltage is not improved.
Description
Technical field
The present invention relates to the device architecture and the manufacture method of insulated gate bipolar transistor (IGBT).Be particularly related to a kind of device architecture and manufacture method with trench IGBT of improved emitter region-base contact performance and metal line.
Background technology
Semiconductor power device is used to as in the power electronic systems such as mixing, electric power or fuel cell locomotive as widely used power electronic device.In the last few years, day by day increased the demand of high performance semiconductor power device in market, particularly to particularly outstanding as the demand of high pressure semiconductor power devices such as IGBT.But, still be faced with the technical difficulty that the increase owing to the saturation voltage between collector electrode-emitter causes at present as the high-voltage semi-conductor power device of these quasi-traditions such as IGBT.Particularly when more and more miniaturization and when making the cell density of semiconductor power device increasing of the manufacturing of IGBT, above-mentioned collector-emitter saturation voltage increases and the difficulty that causes is just more obvious.
At U.S. Patent number 6,894, in 347, people such as Hattori have disclosed the IGBT semiconductor power device shown in Figure 1A.The base 43 of the basic unit 42 of a N+ resilient coating that the upper surface that this IGBT device is included in P+ current collection layer 40 forms successively 41, a N-high impedance, a heavily doped base 51 of P+ and a P type.In addition, n+ emitter region 44 optionally is formed at certain zone of described P-base upper surface.This IGBT device also comprises groove 45, and this groove passes described emitter region 44, described P type base 43 and described P+ base 51 from the upper surface of described emitter region 44, extends down into described N-basic unit 42.The inner surface of described groove 45 forms gate insulation layer 46, and forms gate electrode 47 (trench gate electrode) on this gate insulation layer 46.Emitter region 44 in this IGBT power device is viewed as much for example banded structure from vertical view, and described groove 45 is formed between per two adjacent emitter regions 44.Emitter electrode 48 is made of the metal aluminum steel, covers described emitter region 44 and described P type base 43.Electrical insulation between these emitter electrode 48 one side and the described gate electrode 47 forms short circuit on the other hand between described emitter region 44 and described P type base 43.This IGBT device also comprises insulating barrier 49, and this insulating barrier is formed on described P type base 43 and the described trench gate electrode 47.The contact hole of the emitter-base stage of described emitter electrode 48 by being arranged in described insulating barrier 49 links to each other with described P type base 43 with described emitter region 44.This IGBT device also comprises collector electrode 50, and this collector electrode is formed at the lower surface of described P+ collector region 40.Groove 52 is formed between two adjacent described grooves 45, and passes described P type base 43 and extend down into described P+ base 51, these groove 52 inner fillings with emitter electrode 48.
The IGBT device that prior art shown in Figure 1A discloses has strengthened the ability of Short Circuit withstand under low on-state voltage.Yet the shortcoming of this IGBT device is to form between described P+ base 51 and the channel region and contacts, thereby this can cause that grid-emitter threshold voltage increases collector emitter saturation voltage is increased.
At U.S. Patent number 6,437, in 399, people such as Huang have disclosed the trench IGBT semiconductor power device shown in Figure 1B.This trench IGBT device comprises trench gate 26 and extends into the emitter metal 36 of contact trench that described contact trench passes BPSG (boron-phosphorosilicate glass) layer 30 and P type base 14 and extends down into P+ base 35.Wherein said P+ base 35 is formed at the inside at the N-resilient coating 10 of P type substrate top surface.This trench IGBT device that people such as Huang disclose also exists the deficiency of self, because the degree of depth of described P+ base 35 is greater than the degree of depth of described P type base 14, cause between two adjacent described contact trench to have higher JFET resistance, and increasing of JFET resistance can cause increasing of collector-emitter saturation voltage.
Therefore, in the design of power semiconductor and in making in the field, the manufacture method of new semiconductor power device is proposed and device architecture solves above-mentioned problem and limitation is very important.
Summary of the invention
The present invention has overcome some shortcomings that exist in the prior art, and a kind of improved insulated gate bipolar transistor (IGBT) power device is provided, and strengthens the resistivity to latch phenomenon when not increasing grid-emitter threshold voltage.
According to embodiments of the invention, a kind of insulated trench gate electrode bipolar type transistor (IGBT) is provided, comprising:
(a) epitaxial loayer of first conduction type, this epitaxial loayer comprises first epitaxial loayer of first conduction type and second epitaxial loayer of first conduction type, described first epitaxial loayer is positioned at the top of described second epitaxial loayer, and the majority carrier concentration of described first epitaxial loayer is lower than described second epitaxial loayer;
(b) current collection layer of second conduction type is positioned at the below of described epitaxial loayer;
(c) a plurality of trench gate, this trench gate is surrounded by the base of the emitter region of first conduction type and second conduction type simultaneously, and extend down in the described epitaxial loayer, wherein said base is positioned at the top of described epitaxial loayer, and described emitter region is positioned at the top of described base;
(d) first insulating barrier, this insulating barrier covers the upper surface of described trench gate and described emitter region;
(e) emitter region-base contact trench between two adjacent described trench gate, and passes described first insulating barrier and described emitter region, extends down into described base, and the inner metal plug of filling of described emitter region-base contact trench;
(f) emitter region of second conduction type-base contact doping district, be positioned at described base, and surround the bottom of described emitter region-base contact trench at least, the concentration of majority carrier is higher than described base in this emitter region-base contact doping district, and near the channel region described emitter region-base contact doping district and the described trench gate keeps a preset distance.
According to embodiments of the invention, another kind of insulated trench gate electrode bipolar type transistor (IGBT) power device is provided, comprising:
(a) substrate of first conduction type;
(b) current collection layer of second conduction type is positioned at the below of described substrate;
(c) a plurality of trench gate, this trench gate is surrounded by the base of the emitter region of first conduction type and second conduction type simultaneously, and extends down in the described substrate, and wherein said base is positioned at the top of described substrate, and described emitter region is positioned at the top of described base;
(d) first insulating barrier, this insulating barrier covers the upper surface of described trench gate and described emitter region;
(e) emitter region-base contact trench between two adjacent described trench gate, and passes described first insulating barrier and described emitter region, extends down into described base, and the inner metal plug of filling of described emitter region-base contact trench;
(f) emitter region of second conduction type-base contact doping district, be positioned at described base, and surround the bottom of described emitter region-base contact trench at least, the concentration of majority carrier is higher than described base in this emitter region-base contact doping district, and near the channel region described emitter region-base contact doping district and the described trench gate keeps a preset distance.
In some preferred embodiments, the doping content scope of the majority carrier in described emitter region-base contact doping district is 1E18-1E20cm
-3, be higher than the doping content of the base of described second conduction type.
In some preferred embodiments, the distance between near the channel region described emitter region-base contact doping district and the described trench gate is 0.2 μ m.
In some preferred embodiments, described emitter region-base contact trench also comprises barrier layer, this barrier layer covers the sidewall and the bottom surface of described emitter region-base contact trench, and near the described metal plug that is filled in described emitter region-base contact trench.More preferably, described barrier layer is Ti/TiN or Co/TiN.
In some preferred embodiments, the described metal plug in described emitter region-base contact trench is a tungsten plug.
In some preferred embodiments, also comprise the metal level that is positioned at described first insulating barrier top, this metal level fill simultaneously with described emitter region-base contact trench in, form metal plug.
In some preferred embodiments, described first conduction type is the N type, and described second conduction type is the P type.
In some preferred embodiments, each sidewall of described emitter region-base contact trench is straight line.More preferably, the vertical upper surface with described substrate of this sidewall.
In some preferred embodiments, each sidewall of described emitter region-base contact trench is an oblique line.More preferably, present the inclination of a predetermined angular between the upper surface of this sidewall and described substrate.
In some preferred embodiments, the top of each sidewall of described emitter region-base contact trench is straight line, and the lower part is an oblique line.More preferably, the vertical upper surface with described substrate in its top, the oblique line of its underpart and the top of each sidewall crossing and and the upper surface of described substrate between present the inclination of a predetermined angular.
In some preferred embodiments, described emitter region-base contact trench also comprises an open top of widening that is positioned at described first insulating barrier, and this open-topped width of widening is greater than the width between the sidewall of described emitter region-base contact trench.
An advantage of the invention is, improve the contact performance between IGBT emitter region-base, reduce the contact resistance of base by below emitter region-base contact trench, introducing emitter region-base contact doping district.
Another advantage of the present invention is, in some preferred embodiments, the sidewall of described emitter region-base contact trench in the emitter region perpendicular to the upper surface of substrate, and in the base and present the inclination of a predetermined angular between the upper surface of described substrate.The advantage of this angled side walls structure is, carrying out the zero degree ion when inject forming described emitter region-base contact doping district, dopant ion still can pass described angled side walls and diffuse near the base that is positioned at described emitter region-base contact trench bottom.Formed emitter region-base contact doping district not only surrounds the bottom of described emitter region-base contact trench, and surround the described angled side walls that described emitter region-base contact trench is positioned at the base, therefore can reduce the resistance of contact zone significantly and make IGBT increase the resistivity that strengthens effectively under the unconspicuous situation latch phenomenon at emitter-threshold voltage of the grid.
According to another aspect of the present invention, provide the method for a kind of making insulated trench gate bipolar transistor (IGBT) power device, comprised the operation that forms trench gate, emitter region and base, also comprised:
Upper surface in described base covers first insulating barrier and provide mask plate on this first insulating barrier, etching forms the operation of a plurality of emitter regions-base contact trench subsequently, wherein, described emitter region-base contact trench passes described first insulating barrier and extends into described base; The operation of described etching emitter region-base contact trench comprises that also the method with unidirectional etching forms the operation of vertical trenched side-wall and the operation that forms the trenched side-wall that tilts with the lithographic method of gradual change angle in described base in described emitter region; Intersect the bottom surface of the trenched side-wall of wherein said inclination and described emitter region-base contact trench.
In some preferred embodiments, method by providing the zero degree ion to inject in described emitter region-base contact trench also is provided described method, form the operation in emitter region-base contact doping district, this emitter region-base contact doping district is positioned at described base and surrounds the bottom of described emitter region-base contact trench.
Description of drawings
For further specifying technology contents of the present invention, below in conjunction with drawings and Examples describe in detail as after, wherein:
The cutaway view of the conventional groove IGBT that the two kinds of prior aries that show Figure 1A to Figure 1B disclose.
Fig. 2 A to Fig. 5 D shows the cutaway view of the trench IGBT of different embodiment according to the subject invention.
Fig. 6 shows and makes the cutaway view of emitter region-base contact trench according to an embodiment of the invention, wherein the side wall upper part of emitter region-base contact trench is divided the upper surface perpendicular to substrate, presents the inclination of a predetermined angular between the upper surface of lower part and described substrate.
Embodiment
Fig. 2 A illustrates the cutaway view of insulated trench gate electrode bipolar type transistor according to an embodiment of the invention (IGBT) device 100, and this trench IGBT device is the vertical power device that forms on P+ substrate 105.Referring to Fig. 2 A, this trench IGBT device is punch (PT) device.Described P+ substrate 105 is used as collector region, and is formed with collector electrode metal 101 at its lower surface.At the upper surface of described P+ substrate 105, growth has N+ epitaxial loayer 110 and N-epitaxial loayer 115 successively.This trench IGBT device also comprises trench gate 120, and these trench gate 120 inner surfaces are lined with grid oxic horizon 125 and fill with polysilicon.Described trench gate 120 is surrounded by P type base 130, and comprises N+ emitter 135 in the part near P type base 130 upper surfaces.Insulating barrier 140 covers the upper surface of described substrate, and on the insulating barrier 125 ' that forms simultaneously of covering and described grid oxic horizon 125.
This trench IGBT device also comprises emitter region-base contact trench, this emitter region-base contact trench passes described insulating barrier 140, be lined with the barrier layer 155 that Ti/TiN or Co/TiN form, and filling contacts with described base 130 formation electricity with described emitter region 135 with tungsten plug 160 on this barrier layer.Each described emitter region-base contact trench all extends down into described base 130 and is surrounded by p+ emitter region-base contact doping district 165 in the bottom and contacts with the electricity that reduces contact resistance and strengthen between emitter region-base.What can cover at the top of described insulating barrier 140 that one deck is made up of Ti or Ti/TiN falls resistance layer 145 to increase contact area between emitter metal 150 and the emitter region-base tungsten plug 160 to reduce contact resistance.
Described p+ emitter region-base contact doping district 165 is formed at the bottom of described emitter region-base contact trench, and keeps a distance of being scheduled to reach the purpose of reduction device to the sensitivity of latch phenomenon to reduce base-emitter resistance with channel region.The size of base-emitter resistance is relevant to the doping content of distance between the trench gate 120 and described P type base 130 with doping content, the emitter region-base contact trench in described p+ emitter region-base doping district 165.With reference to the equivalent electric circuit of the IGBT shown in the figure 2A-1, as can be known, this IGBT device comprises a MOSFET and by a NPN and the thyristor that the PNP transistor is formed, resistance R b represents the resistance between base stage and emitter among the figure.The voltage drop that if electric current flows through Rb and produce 0.7V on Rb, described thyristor is unlocked, and this IGBT device is lost turn-off capacity thereupon, and this is so-called latch phenomenon.Thereby latch phenomenon can cause the excessive components from being damaged that causes of electric current.In described emitter region-the described p+ emitter region-base contact doping district 165 and the distance of the optimum between the channel region of base contact trench bottom be about 0.2 μ m, wherein, the optimum distance is defined as the square root of [(contact width tolerance) 2+ (groove width tolerance) 2+ (deviation between contact and groove) 2], can guarantee in manufacturing process that with this described p+ emitter region-base contact doping district 165 very still can never touch channel region near channel region and then strengthen the ability of opposing latch-up.According to trench IGBT device of the present invention not needs consider compromise problem between grid-emitter threshold voltage and the opposing latch-up.Thus, thus avoided having caused the problem of higher grid-emitter threshold voltage because of p+ doped region contact channel region among the conventional groove IGBT.
Fig. 2 B shows according to another embodiment of the invention.Structural similarity shown in trench IGBT device 100-1 and Fig. 2 A among Fig. 2 B is wherein filled in emitter region-base contact trench with the angle between the upper surface of tungsten plug 260 and its sidewall and substrate less than 85 degree.This angled side walls structure has strengthened the contact performance between p+ emitter region-base contact doping district 265 and the tungsten plug 260.The formation in described p+ emitter region-base contact doping district 265 is to form by the method for directly carrying out the ion injection to described angled side walls, but not injects by carrying out ion to the bottom of groove earlier, is then realized by the method that diffuses to form the p+ doped region.The advantage of this method is, makes that the dopant ion concentration around contact trench 260 sidewalls is more even, thereby reduces the base resistance between channel region and the emitter region.And the further ability that improves opposing latch-up or short circuit.According to embodiments of the invention, in described emitter region-base contact trench, the angle between sloped sidewall and the channel bottom in described P type base is less than 85 degree.Along with the increase of contact area between described P type base and the described p+ emitter region-base contact doping district, base resistance reduces, thereby has further lowered the sensitivity of IGBT device to latch-up.In the process of the described emitter region of etching-base contact trench, described angled side walls can realize by adjusting methods such as dry etching, gas pressure intensity and power.
Fig. 2 C shows according to another embodiment of the invention.Structural similarity shown in trench IGBT device 100-2 and Fig. 2 A among Fig. 2 C, wherein comprise a polygonal tungsten plug 360 in emitter region-base contact trench, promptly be filled in the metal plug in the contact trench, described emitter region-the part of base contact trench sidewall in the N+ emitter region is perpendicular to the upper surface of substrate, and presenting the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, intersect the bottom of this angled side walls and contact trench.Shown in Fig. 2 C, emitter region-base contact trench has vertical sidewall in N+ emitter region 335, and has angled side walls in P type base 330, and the angle between the upper surface of this angled side walls and substrate is less than 85 degree.Contact performance between this angled side walls structure and p+ emitter region-base contact doping district 365 is better, reason is that p+ doped region 365 can be by the method for zero degree ion injection, P+ impurity is directly injected P type base by described angled side walls, thereby obtain Impurity Distribution more uniformly.When p+ doped region 365 forms by diffusion process, the doping content of majority carrier can reduce to some extent near the trenched side-wall some zones, this situation then can not take place when adopting above-mentioned ion injection method, and then can obtain lower emitter contact resistance.When carrying out the zero degree ion injection method (energy is from 20KeV to 100KeV) with P+ ion injection contact trench, the p+ foreign ion only injects the below of the sloped sidewall that is arranged in P type base 330 and channel bottom and can not inject N+ emitter region 335 by the vertical sidewall of contact trench, and therefore this contact trench of bottom angled sidewall that has is for the invention provides preferred construction.Injecting the angle that the condition use usually is included between emitter region in the p type island region-sidewall of base contact trench and the upper surface of substrate at the p+ ion is that the foreign ion type of 20-100KeV, doping is boron and BF2 less than 85 degree, injection energy.
Fig. 2 D shows according to another embodiment of the invention.Structural similarity shown in trench IGBT device 100-3 and Fig. 2 C among Fig. 2 C, wherein comprise a polygonal tungsten plug 460 in emitter region-base contact trench, promptly be filled in the metal plug in the contact trench, the upper surface of the vertical and substrate of the part of sidewall in the N+ emitter region of described emitter region-base contact trench, and present the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, and intersect the bottom of this angled side walls and contact trench.This trench IGBT device has similar structure to IGBT100-2 among Fig. 2 C, the trench IGBT device that different is among Fig. 2 D in the emitter region-a wideer opening is arranged at the top of base contact trench, the insulating barrier that is positioned at described substrate top surface simultaneously is made up of SRO layer 440-1 and the PSG (phosphorosilicate glass) or BPSG (boron-phosphorosilicate glass) 440-2 that are positioned on the described SRO, and is positioned at the A/F of the open-topped width of widening of described PSG or BPSG greater than described SRO.Therefore, this preferred construction makes the width of the upper surface be packed into the described tungsten plug in described emitter region-base contact trench greater than the width that is packed into the base part, improved and emitter metal between the interface contact performance.Because the contact area between the upper surface of described tungsten plug and the described emitter metal increases, make contact resistance further reduce.
Fig. 3 A shows channel insulation gate transistor (IGBT) device 200 according to another embodiment of the invention.This trench IGBT device is punch (PT) vertical power device that is formed on the P+ substrate 505.Wherein, described P+ substrate 505 is used as collector electrode, and is deposited with collector electrode metal 501 at its lower surface.N+ epitaxial loayer 510 and N-epitaxial loayer 515 are formed at the upper surface of described P+ substrate 505 successively.This trench IGBT device also comprises trench gate 520, and these trench gate 520 interior fillings are with polysilicon and be lined with grid oxic horizon 525.Described trench gate 520 is surrounded by P type base 530, and in described P type base 530 parts near its upper surfaces, include N+ emitter 535.Insulating barrier 540 covers the upper surface of described substrate, and covers on the insulating barrier 525 ' that forms simultaneously with described grid oxic horizon 525.
This trench IGBT device 200 also comprises emitter region-base contact trench, this emitter region-base contact trench passes described insulating barrier 540, and be lined with the barrier layer 555 that Ti/TiN or Co/TiN or Ta/TiN form, and filling contacts with described base 530 formation electricity with described emitter region 535 with emitter metal 550 on this barrier layer.Each described emitter region-base contact trench all extends down into P type base 530, and is formed with p+ emitter region-base contact doping district 565 to reduce contact resistance and to strengthen electricity contact performance between emitter region-base below contact trench bottom.
The effect in described p+ emitter region-base contact doping district 565 is the electricity contact performances that strengthen between emitter metal and emitter region and the base.Thereby avoided having caused the problem of higher grid-emitter threshold voltage because of p+ doped region contact channel region in the conventional groove IGBT device.
Fig. 3 B shows trench IGBT device 200-1 according to another embodiment of the invention, and this device has similar structure to the trench IGBT device shown in Fig. 3 A.Wherein be filled with emitter metal 650 in emitter region-base contact trench and groove has the angled side walls structure.
Fig. 3 C shows trench IGBT device 200-2 according to another embodiment of the invention, and this device has similar structure to the trench IGBT device shown in Fig. 3 A.Wherein, be filled with metal plug 750 in emitter region-base contact trench.The sidewall of contact trench is positioned at the upper surface of the vertical and substrate of the part of N+ emitter region, is located at the part of P type base, and presents the inclination of a predetermined angular between the upper surface of described substrate.
Fig. 3 D shows trench IGBT device 200-3 according to another embodiment of the invention, and this device has similar structure to the trench IGBT device shown in Fig. 3 C.Wherein, be filled with metal plug 850 in described emitter region-base contact trench.The upper surface of the vertical and substrate of the part of sidewall in the N+ emitter region of described emitter region-base contact trench, and present the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, and intersect the bottom of this angled side walls and contact trench.This trench IGBT device has similar structure to IGBT device 200-2 among Fig. 3 C, the trench IGBT that different is among Fig. 3 D in the emitter region-a wideer opening is arranged at the top of base contact trench, the insulating barrier that is positioned at described base upper surface simultaneously is made up of SR0840-1 and the PSG (phosphorosilicate glass) or BPSG (boron-phosphorosilicate glass) 840-2 that are positioned on the described SRO, and is positioned at the A/F of the open-topped width of widening of described PSG or BPSG greater than described SRO.
Fig. 4 A shows insulated trench gate electrode bipolar type transistor (IGBT) device 300 cutaway views according to another embodiment of the invention.This trench IGBT device is to go up the vertical power device that forms at FZ (zone-melting process) N type substrate 115-2.Referring to Fig. 4 A, this trench IGBT device is non-punch (NPT) device.At the lower surface of described N type substrate 115-2, the method growth of injecting with ion after grinding has P+ collector region 105-2.Below this P+ collector region 105-2, be deposited with collector electrode metal 101-2.This trench IGBT device also comprises trench gate 120-2, and this trench gate 120-2 inner surface is lined with grid oxic horizon 125-2 and fills with polysilicon.Described trench gate 120-2 is surrounded by P type base 130-2, and comprises N+ emitter region 135-2 in the part near P type base 130-2 upper surface.Insulating barrier 140-2 covers the upper surface of described substrate, and on the insulating barrier 125-2 ' that forms simultaneously of covering and described grid oxic horizon 125-2.This trench IGBT device also comprises emitter region-base contact trench, this emitter region-base contact trench passes described insulating barrier 140-2, and be lined with the barrier layer 155-2 that forms by Ti/TiN or Co/TiN or Ta/TiN, and on this barrier layer, fill with tungsten plug 160-2 and contact with described emitter region 135-2 and described base 130-2 formation electricity.Each described emitter region-base contact trench all extend down into described base 130-2 and be surrounded by in the bottom P+ emitter region-base contact doping district 165-2 with reduce contact resistance and strengthen between emitter region-base the electricity contact performance.What can cover at the top of described insulating barrier 140-2 that one deck is made up of Ti or Ti/TiN falls resistance layer 145-2 to increase contact area between emitter metal 150-2 and the emitter region-base tungsten plug 160-2 to reduce contact resistance.
Described p+ emitter region-base contact doping district 165-2 is formed at the bottom of described emitter region-base contact trench, and the distance that keeps with channel region-be scheduled to reaches the purpose of reduction device to the sensitivity of latch phenomenon to reduce base-emitter resistance.Thus, thus avoided having caused the problem of higher grid-emitter threshold voltage because of p+ doped region contact channel region among the conventional groove IGBT.
Fig. 4 B shows trench IGBT device 300-1 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 4 A.Wherein, be filled with tungsten plug 260-2 in emitter region-base contact trench and have the angled side walls structure.
Fig. 4 C shows trench IGBT device 300-2 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 4 A.Wherein, groove emitter region-contact zone, base comprises a polygonal tungsten plug 360-2, promptly be filled in the metal plug in the contact trench, described emitter region-the part of base contact trench in the N+ emitter region is perpendicular to the upper surface of substrate, and presenting the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, intersect the bottom of this angled side walls and contact trench.
Fig. 4 D shows trench IGBT device 300-3 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 4 C.Wherein, emitter region-base touches and comprises a polygonal tungsten plug 460-2 in the groove, promptly be filled in the metal plug in emitter region-base contact trench, the part of sidewall in the N+ emitter region of described emitter region-base contact trench is perpendicular to the upper surface of substrate, and present the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, and intersect the bottom of this angled side walls and contact trench.The difference of structure is shown in Fig. 4 D and Fig. 4 C, a wideer opening is arranged at the contact trench top among Fig. 4 D, the insulating barrier that is positioned at described substrate top surface simultaneously is made up of SRO layer 440-12 and the PSG (phosphorosilicate glass) or BPSG (boron-phosphorosilicate glass) 440-22 that are positioned on the described SRO, and is positioned at the A/F of the open-topped width of widening of described PSG or BPSG greater than described SRO.
Fig. 5 A shows the cutaway view of insulated trench gate electrode bipolar type transistor (IGBT) device 400 according to another embodiment of the invention.The vertical power device of this trench IGBT device on FZ N type substrate 515-2, forming.Referring to Fig. 5 A, this trench IGBT device is non-punch (NPT) device.At the lower surface of described N type substrate 515-2, the method growth of injecting with ion after grinding has P+ collector region 505-2.Below this P+ collector region 505-2, be deposited with collector electrode metal 501-2.This trench IGBT device also comprises trench gate 520-2, and the interior filling of this trench gate 520-2 is lined with grid oxic horizon 525-2 and fills with polysilicon.Described trench gate 520-2 is surrounded by P type base 530-2, and comprises N+ emitter region 535-2 in the part near P type base 530-2 upper surface.Insulating barrier 540-2 covers the upper surface of described substrate, and on the insulating barrier 525-2 ' that forms simultaneously of covering and described grid oxic horizon 525-2.
This trench IGBT device also comprises emitter region-base contact trench, this emitter region-base contact trench passes described insulating barrier 540-2, and be lined with the barrier layer 555-2 that is made up of Ti/TiN or Co/TiN, and filling contacts with described emitter region 535-2 and described base 530-2 formation electricity with emitter metal 550-2 on this barrier layer.Each described emitter region-base contact trench all extend down into described base 530-2 and be surrounded by in the bottom p+ emitter region-base contact doping district 565-2 with reduce contact resistance and strengthen between emitter region-base the electricity contact performance.
Described p+ emitter region-base contact doping district 565-2 is formed at the bottom of described emitter region-base contact trench, and keeps a distance of being scheduled to reach the purpose of reduction device to the sensitivity of latch phenomenon to reduce base-emitter resistance with channel region.Thus, thus avoided having caused the problem of higher grid-emitter threshold voltage because of p+ doped region contact channel region among the conventional groove IGBT.
Fig. 5 B shows trench IGBT device 400-1 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 5 A.Wherein, emitter region-base contact trench has the angled side walls structure.
Fig. 5 C shows trench IGBT device 400-2 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 5 A.Wherein, described emitter region-the part of base contact trench in the N+ emitter region is perpendicular to the upper surface of substrate, and presenting the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, intersect the bottom of this angled side walls and contact trench.
Fig. 5 D shows trench IGBT device 400-3 according to another embodiment of the invention, and this trench IGBT device has similar structure to the trench IGBT shown in Fig. 5 C.Wherein, the part of the sidewall of described contact trench in the N+ emitter region be perpendicular to the upper surface of substrate, and present the inclination of a predetermined angular between the upper surface of part in P type base and described substrate, and intersect the bottom of this angled side walls and contact trench.The difference of structure is shown in Fig. 5 D and Fig. 5 C, a wideer opening is arranged at the contact trench top among Fig. 5 D, the insulating barrier that is positioned at described substrate top surface simultaneously is made up of SRO layer 840-12 and the PSG (phosphorosilicate glass) or BPSG (boron-phosphorosilicate glass) 840-22 that are positioned on the described SRO, and is positioned at the A/F of the open-topped width of widening of described PSG or BPSG greater than described SRO.
Fig. 6 is the manufacture method of polygonal emitter region-base contact trench in the structure according to the embodiment of the invention.The mask plate (not shown) of emitter region-base contact trench at first is provided, remove partial oxidation layer 340 with the method for dried oxygen etching subsequently and leave the window of groove, after this open groove with the method for dry method silicon etching, wherein the part and the angle between the upper surface of substrate of the sidewall of groove in emitter region 335 is 90 ± 3 degree.Continue to use the dry method silicon etching to form emitter region-base contact trench then and be positioned at the angled side walls of P type base, the angle between the upper surface of this angled side walls and substrate is less than 85 degree.Because the etch rate and the side wall profile of groove and the doping content of silicon chip have relation, so use the method for unidirectional dry etching can make needed side wall profile easily.
Although above described embodiments of the invention, but be understandable that after reading present embodiment, those skilled in the art can derive many other variation and embodiment by present embodiment fully, and falls within the spirit and scope of principle of present disclosure.
Claims (22)
1. an insulated trench gate electrode bipolar type transistor is characterized in that, comprising:
The epitaxial loayer of first conduction type, this epitaxial loayer comprises first epitaxial loayer of first conduction type and second epitaxial loayer of first conduction type, described first epitaxial loayer is positioned at the top of described second epitaxial loayer, and the majority carrier concentration of described first epitaxial loayer is lower than described second epitaxial loayer;
The current collection layer of second conduction type is positioned at the below of described epitaxial loayer;
A plurality of trench gate, this trench gate is surrounded by the base of the emitter region of first conduction type and second conduction type simultaneously, and extends down in the described epitaxial loayer, and wherein said base is positioned at the top of described epitaxial loayer, and described emitter region is positioned at the top of described base;
First insulating barrier, this insulating barrier covers the upper surface of described trench gate and described emitter region;
Described first insulating barrier and described emitter region between two adjacent described trench gate, and are passed in emitter region-base contact trench, extend down into described base, and the inner metal plug of filling of described emitter region-base contact trench;
The emitter region of second conduction type-base contact doping district, be positioned at described base, and surround the bottom of described emitter region-base contact trench at least, the concentration of majority carrier is higher than described base in this emitter region-base contact doping district, and near the channel region described emitter region-base contact doping district and the described trench gate keeps a preset distance.
2. an insulated trench gate electrode bipolar type transistor is characterized in that, comprising:
The substrate of first conduction type;
The current collection layer of second conduction type is positioned at the below of described substrate;
A plurality of trench gate, this trench gate is surrounded by the base of the emitter region of first conduction type and second conduction type simultaneously, and extends down in the described substrate, and wherein said base is positioned at the top of described substrate, and described emitter region is positioned at the top of described base;
First insulating barrier, this insulating barrier covers the upper surface of described trench gate and described emitter region;
Described first insulating barrier and described emitter region between two adjacent described trench gate, and are passed in emitter region-base contact trench, extend down into described base, and the inner metal plug of filling of described emitter region-base contact trench;
The emitter region of second conduction type-base contact doping district, be positioned at described base, and surround the bottom of described emitter region-base contact trench at least, the concentration of majority carrier is higher than described base in this emitter region-base contact doping district, and near the channel region described emitter region-base contact doping district and the described trench gate keeps a preset distance.
3. according to the described insulated trench gate electrode bipolar type transistor of claim 1, it is characterized in that described insulated trench gate electrode bipolar type transistor is the punch insulated trench gate electrode bipolar type transistor.
4. according to the described insulated trench gate electrode bipolar type transistor of claim 2, it is characterized in that described insulated trench gate electrode bipolar type transistor is non-punch insulated trench gate electrode bipolar type transistor.
5. according to the described insulated trench gate electrode bipolar type transistor of claim 2, it is characterized in that also comprise the basic unit of first conduction type, this basic unit is positioned at the below of described substrate, and be positioned at the top of described current collection layer.
6. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that the doping content scope of majority carrier is 1E18-1E20cm in described emitter region-base contact doping district
-3, be higher than the doping content of majority carrier of the base of described second conduction type.
7. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that the distance between near the channel region described emitter region-base contact doping district and the described trench gate is 0.2 μ m.
8. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that, described emitter region-base contact trench also comprises a barrier layer, this barrier layer covers the sidewall and the bottom surface of described emitter region-base contact trench, and near the described metal plug that is filled in described emitter region-base contact trench.
9. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that the described metal plug in described emitter region-base contact trench is a tungsten plug.
10. according to the described insulated trench gate electrode bipolar type transistor of claim 9, it is characterized in that described barrier layer is Ti/TiN or Co/TiN or Ta/TiN.
11., it is characterized in that described first conduction type is the N type according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, described second conduction type is the P type.
12., it is characterized in that each sidewall of described emitter region-base contact trench is straight line according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors.
13., it is characterized in that each sidewall of described emitter region-base contact trench is straight line, and this sidewall is perpendicular to the upper surface of described substrate according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors.
14., it is characterized in that each sidewall of described emitter region-base contact trench is an oblique line according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, and present the inclination of a predetermined angular between the upper surface of this sidewall and described substrate.
15. according to claim 1 or 2 insulated trench gate electrode bipolar type transistors, it is characterized in that, the top of each sidewall of described emitter region-base contact trench is straight line, this straight line is perpendicular to the upper surface of described substrate, the lower part of described each sidewall is an oblique line, the top of this oblique line and described each sidewall intersect and and the upper surface of described substrate between present the inclination of a predetermined angular, and intersect with the bottom surface of described emitter region-base contact trench.
16. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that, the top of each sidewall of described emitter region-base contact trench is formed in the described emitter region, and be straight line, the vertical upper surface with described substrate of this straight line, the lower part of described each sidewall is formed in the described base, and be an oblique line, the top of this oblique line and described each sidewall intersect and and the upper surface of described substrate between present the inclination of a predetermined angular, and intersect with the bottom surface of described emitter region-base contact trench.
17., it is characterized in that the angle between the described emitter region-lower part of base each sidewall of contact trench and the upper surface of described substrate is less than 85 degree according to the described insulated trench gate electrode bipolar type transistor of claim 16.
18. according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors, it is characterized in that, described emitter region-base contact trench also comprises an open top of widening that is positioned at described first insulating barrier, and this open-topped width of widening is greater than the width between the sidewall of each described the district's utmost point-district's utmost point contact trench.
19., it is characterized in that also comprise the metal level that is positioned at described first insulating barrier top, this metal level is filled in described emitter region-base contact trench simultaneously, forms metal plug according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors.
20., it is characterized in that described trench gate inner surface is lined with grid oxic horizon and fills the polysilicon that mixes according to claim 1 or 2 described insulated trench gate electrode bipolar type transistors.
21. the manufacture method of an insulated trench gate electrode bipolar type transistor is characterized in that, comprises the operation that forms trench gate, emitter region and base, also comprises:
Upper surface in described base and described trench gate covers first insulating barrier and provide mask plate on this first insulating barrier, etching forms the operation of a plurality of emitter regions-base contact trench subsequently, wherein, described emitter region-base contact trench passes described first insulating barrier and extends into described base; The operation of described etching emitter region-base contact trench comprises that also the method with unidirectional etching forms the operation of vertical trenched side-wall and the operation that forms the trenched side-wall that tilts with the lithographic method of gradual change angle in described base in described emitter region; Intersect the bottom surface of the trenched side-wall of wherein said inclination and described emitter region-base contact trench.
22. the manufacture method of the described insulated trench gate electrode bipolar type transistor of claim 21, it is characterized in that, comprise that also this emitter region-base contact doping district is positioned at described base and surrounds the bottom of described emitter region-base contact trench by providing the zero degree ion to inject the operation that forms emitter region-base contact doping district in described emitter region-base contact trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101495130A CN102201437A (en) | 2010-03-25 | 2010-03-25 | Trench insulated gate bipolar transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101495130A CN102201437A (en) | 2010-03-25 | 2010-03-25 | Trench insulated gate bipolar transistor and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102201437A true CN102201437A (en) | 2011-09-28 |
Family
ID=44661978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101495130A Pending CN102201437A (en) | 2010-03-25 | 2010-03-25 | Trench insulated gate bipolar transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102201437A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412151A (en) * | 2011-11-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
| CN102420134A (en) * | 2011-11-25 | 2012-04-18 | 上海华虹Nec电子有限公司 | Manufacturing method of super-junction combined punch-through type groove IGBT (Insulated Gate Bipolar Transistor) device |
| CN103035521A (en) * | 2012-11-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Process method for achieving minor carrier storage layer groove-type insulated gate bipolar translator (IGBT) |
| CN103107189A (en) * | 2013-02-28 | 2013-05-15 | 江苏物联网研究发展中心 | Insulated gate bipolar translator (IGBT) back structure and preparing method thereof |
| CN103441143A (en) * | 2013-07-10 | 2013-12-11 | 电子科技大学 | Latch-up prevention IGBT with mixed crystal emission area with variable components |
| CN103474458A (en) * | 2013-08-14 | 2013-12-25 | 中航（重庆）微电子有限公司 | Insulated gate bipolar transistor (IGBT) device and preparation method thereof |
| CN103794646A (en) * | 2012-10-29 | 2014-05-14 | 三星电机株式会社 | Semiconductor device |
| CN104078354A (en) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | Power semiconductor device and manufacturing method thereof |
| CN105895699A (en) * | 2015-02-13 | 2016-08-24 | 英飞凌科技股份有限公司 | Semiconductor Device and Method for Forming Semiconductor Device |
| CN107112358A (en) * | 2015-07-16 | 2017-08-29 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN113327854A (en) * | 2021-05-14 | 2021-08-31 | 深圳市威兆半导体有限公司 | Method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5623152A (en) * | 1995-02-09 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| US6717210B2 (en) * | 2002-09-02 | 2004-04-06 | Kabushiki Kaisha Toshiba | Trench gate type semiconductor device and fabricating method of the same |
| CN1941417A (en) * | 2005-09-26 | 2007-04-04 | 谢福渊 | Structure for avalanche improvement of ultra high density trench mosfet |
-
2010
- 2010-03-25 CN CN2010101495130A patent/CN102201437A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5623152A (en) * | 1995-02-09 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| US6717210B2 (en) * | 2002-09-02 | 2004-04-06 | Kabushiki Kaisha Toshiba | Trench gate type semiconductor device and fabricating method of the same |
| CN1941417A (en) * | 2005-09-26 | 2007-04-04 | 谢福渊 | Structure for avalanche improvement of ultra high density trench mosfet |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412151A (en) * | 2011-11-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
| CN102420134A (en) * | 2011-11-25 | 2012-04-18 | 上海华虹Nec电子有限公司 | Manufacturing method of super-junction combined punch-through type groove IGBT (Insulated Gate Bipolar Transistor) device |
| CN102420134B (en) * | 2011-11-25 | 2013-09-11 | 上海华虹Nec电子有限公司 | Manufacturing method of super-junction combined punch-through type groove IGBT (Insulated Gate Bipolar Transistor) device |
| CN103794646A (en) * | 2012-10-29 | 2014-05-14 | 三星电机株式会社 | Semiconductor device |
| CN103035521A (en) * | 2012-11-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Process method for achieving minor carrier storage layer groove-type insulated gate bipolar translator (IGBT) |
| CN103035521B (en) * | 2012-11-05 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | Realize the process of few groove-shaped IGBT of sub-accumulation layer |
| CN103107189A (en) * | 2013-02-28 | 2013-05-15 | 江苏物联网研究发展中心 | Insulated gate bipolar translator (IGBT) back structure and preparing method thereof |
| CN103107189B (en) * | 2013-02-28 | 2015-08-12 | 江苏物联网研究发展中心 | IGBT back structure and preparation method |
| CN104078354B (en) * | 2013-03-26 | 2015-09-16 | 杭州士兰集成电路有限公司 | Power semiconductor and manufacture method thereof |
| CN104078354A (en) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | Power semiconductor device and manufacturing method thereof |
| CN103441143B (en) * | 2013-07-10 | 2015-09-09 | 电子科技大学 | There is the anti-breech lock IGBT becoming component mixed crystal emitter region |
| CN103441143A (en) * | 2013-07-10 | 2013-12-11 | 电子科技大学 | Latch-up prevention IGBT with mixed crystal emission area with variable components |
| CN103474458A (en) * | 2013-08-14 | 2013-12-25 | 中航（重庆）微电子有限公司 | Insulated gate bipolar transistor (IGBT) device and preparation method thereof |
| CN103474458B (en) * | 2013-08-14 | 2016-06-08 | 中航（重庆）微电子有限公司 | IGBT device and preparation method thereof |
| CN105895699A (en) * | 2015-02-13 | 2016-08-24 | 英飞凌科技股份有限公司 | Semiconductor Device and Method for Forming Semiconductor Device |
| US10205011B2 (en) | 2015-02-13 | 2019-02-12 | Infineon Technologies Ag | Method for forming a semiconductor device with implanted chalcogen atoms |
| US10475911B2 (en) | 2015-02-13 | 2019-11-12 | Infineon Technologies Ag | Semiconductor device having a source region with chalcogen atoms |
| CN107112358A (en) * | 2015-07-16 | 2017-08-29 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN107112358B (en) * | 2015-07-16 | 2020-10-20 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN113327854A (en) * | 2021-05-14 | 2021-08-31 | 深圳市威兆半导体有限公司 | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102201437A (en) | Trench insulated gate bipolar transistor and manufacturing method thereof | |
| CN104051509B (en) | With the bigrid trench IGBT for burying the shielding of floating P types | |
| US8058670B2 (en) | Insulated gate bipolar transistor (IGBT) with monolithic deep body clamp diode to prevent latch-up | |
| US8872264B2 (en) | Semiconductor device having a floating semiconductor zone | |
| CN100499164C (en) | Trench semiconductor device and method of manufacturing it | |
| US20100193835A1 (en) | Trench insulated gate bipolar transistor (GBT) with improved emitter-base contacts and metal schemes | |
| CN107204372A (en) | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure | |
| CN102569373B (en) | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT | |
| KR20060040592A (en) | Semiconductor device having an edge termination structure and method of manufacture thereof | |
| CN102214691B (en) | Groove metal oxide semiconductor field effect tube (MOSFET) and manufacturing method thereof | |
| WO2018215727A1 (en) | A semiconductor device | |
| CN103295888A (en) | Semiconductor device and method for manufacturing the same | |
| JP2987040B2 (en) | Insulated gate semiconductor device | |
| CN105762182B (en) | IGBT device with high latch-up immunity | |
| CN101989602B (en) | Trench MOSFET | |
| CN103050521A (en) | Collector region lead-out structure for SiGe heterojunction bipolar transistor (HBT) device, and manufacturing method for collector region lead-out structure | |
| CN113690303A (en) | Semiconductor device and method for manufacturing the same | |
| WO2023070703A1 (en) | Power semiconductor device and manufacturing method therefor | |
| CN101989577B (en) | Method for manufacturing groove MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) | |
| CN208589449U (en) | A kind of trench-gate device structure with current-carrying subpool | |
| CN205621739U (en) | IGBT device with high locking -resisting ability | |
| CN205621737U (en) | Locking -resisting IGBT device | |
| CN206976352U (en) | A kind of power semiconductor for reducing conducting resistance | |
| RU122204U1 (en) | Schottky Diode with Groove Structure | |
| CN105762177B (en) | A kind of anti-latch IGBT device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110928 |