CN102201815B - Binary operation decoding device with high operation frequency - Google Patents
Binary operation decoding device with high operation frequency Download PDFInfo
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- CN102201815B CN102201815B CN201010147555.0A CN201010147555A CN102201815B CN 102201815 B CN102201815 B CN 102201815B CN 201010147555 A CN201010147555 A CN 201010147555A CN 102201815 B CN102201815 B CN 102201815B
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Abstract
The invention provides a binary operation decoding device with high operation frequency. The binary operation decoding device comprises a first lookup table, a second lookup table, a third lookup table, a fourth lookup table, a first multiplexer and a second multiplexer, wherein the input ends of the first and second lookup tables are coupled with the output end of a first register to receive signals from the first register; the input end of the third lookup table is coupled with the output end of the first lookup table to receive the signals from the first lookup table; the input end of the fourth lookup table is coupled with the output end of the second lookup table to receive the signals from the second lookup table; the first multiplexer is provided with a first input end used for receiving the signals from the third lookup table, and a second input end used for receiving the signals from the fourth lookup table; and the second multiplexer is provided with the first input end used for receiving the signals from the third lookup table, and the second input end used for receiving the signals from the second lookup table.
Description
Technical field
The present invention relates to the position decoder of a multidigit full text adaptive binary arithmetic coding, particularly relate to a kind of full text adaptive binary arithmetic coding decoder with two decision bit of the critical path of shortening.
Background technology
In full adaptive binary arithmetic coding (Context-adaptive Binary ArithmeticCoding, CABAC) decoding algorithm utilizes basic consecutive operations to go to calculate for the scope of situational variable, skew and look-up table.The data-dependent characteristic of adaptive binary arithmetic coding decoding in full, cause when real-time process high definition image, adaptive binary arithmetic coding decoding must do the computing of 3,000,000,000 times per second in full, therefore makes adaptive binary arithmetic coding decoding in full be difficult to reach high-speed decoding.Substantially, the position decoder of adaptive binary arithmetic coding comprises a decision bit decoder and a bypass position decoder in full, and by experiment, the 80%-90% position in known all positions is encoded into decision bit, and all the other positions are encoded into bypass position.Although the United States Patent (USP) of the inventors such as Jahanghir the 7th, 262, No. 722 have been disclosed the method using and utilize parallel framework to improve the usefulness of adaptive binary arithmetic coding in full, but in full adaptive binary arithmetic coding decoding algorithm is unlike the video decoded instrument of other H.264/AVC standard, and parallel framework be utilized to go to improve the usefulness of adaptive binary arithmetic coding in full and be not easy.Because adaptive binary arithmetic coding decoding is the decoding using consecutive order in full, but the decoding of consecutive order can make adaptive binary arithmetic coding decoding in full become the main bottleneck of H.264/AVC standard.
Summary of the invention
One embodiment of the invention disclose the position decoder of a kind of multidigit full text adaptive binary arithmetic coding, comprise one first look-up table, have the output that an input is coupled to one first register, in order to receive the signal that this first register exports; One second look-up table, has the output that an input is coupled to this first register, in order to receive the signal that this first register exports; One the 3rd look-up table, has the output that an input is coupled to this first look-up table, in order to receive the signal that this first look-up table exports; One the 4th look-up table, has the output that an input is coupled to this second look-up table, in order to receive the signal that this second look-up table exports; One first multiplexer, has the output that a first input end is coupled to the 3rd look-up table, and in order to receive the signal that the 3rd look-up table exports, one second input is coupled to the output of the 4th look-up table, in order to receive the signal that the 4th look-up table exports; And one second multiplexer, there is the output that a first input end is coupled to this first look-up table, in order to receive the signal that the 3rd look-up table exports, one second input is coupled to the output of this second look-up table, in order to receive the signal that this second look-up table exports; Wherein this first multiplexer and this second multiplexer are all controlled by one first signal.This decoder also comprises one second register of coupled in series, a first adder, a second adder and one first comparison module, and this first comparison module is in order to export this first signal.This decoder also comprises one the 3rd multiplexer, has a first input end is coupled to this second multiplexer output by one the 3rd register, in order to receive the signal that this second multiplexer exports; One the 5th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports; One the 6th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports; One the 7th look-up table, has the output that an input is coupled to the 5th look-up table, in order to receive the signal that the 5th look-up table exports; One the 8th look-up table, has the output that an input is coupled to the 6th look-up table, in order to receive the signal that the 6th look-up table exports; One the 4th multiplexer, has the output that a first input end is coupled to the 7th look-up table, and in order to receive the signal that the 7th look-up table exports, one second input is coupled to the output of the 8th look-up table, in order to receive the signal that the 8th look-up table exports; And one the 5th multiplexer, there is the output that a first input end is coupled to the 5th look-up table, in order to receive the signal that the 5th look-up table exports, one second input is coupled to the output of the 6th look-up table, in order to receive the signal that the 6th look-up table exports; Wherein the 4th multiplexer and the 5th multiplexer are all controlled by one second signal; Wherein the input of this first register is coupled to the output of the 5th multiplexer, in order to store the signal that the 5th multiplexer exports.This decoder also comprises one the 3rd adder of coupled in series, one the 4th adder and one second comparison module, and this second comparison module is in order to export this second signal.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of video signal processing system.
Fig. 2 is the schematic diagram of the decision bit decoder of the video signal processing system of Fig. 1.
Fig. 3 is the critical path of the decision bit decoder of key diagram 2.
Fig. 4 is the schematic diagram of the decision bit decoder that one embodiment of the invention disclose.
Fig. 5 and Fig. 6 is the detailed architecture of the decision bit decoder of key diagram 4.
Fig. 7 and Fig. 8 is the critical path of the decision bit decoder of key diagram 5 and Fig. 6.
Reference numeral explanation
10 video signal processing systems
11 video signal sources
12 video signal processors
13 video display
20 decoders
25,40,405 registers
35 decision bit decoders
30 bypass position decoders
100,300,400 decoders
102,116,502 range registers
103,503,115,530 state indices registers
104,652 rLPS look-up tables
105,505,611 LPS look-up tables
106,506,612 MPS look-up tables
107,110,111,112,415,409,515,516,517,518,519,610,616,623,618,620,621,622 multiplexers
108,109,508,509,641,643 adders
113,513,630 comparison modules
114,514,635 ruleization modules again
117,501,101 offset registers
118,520 incoming bit streams
119,120 updated value
407,500,700 first decision bit decoders
420,600,800 second decision bit decoders
552,614 the one rLPS look-up tables
555,613 the 2nd rLPS look-up tables
550 rLPS registers
Embodiment
Fig. 1 is the schematic diagram of the video signal processing system 10 of the position decoder (bin decoder) determining multidigit.Video signal processing system 10 comprises video signal source 11, video signal processor 12 and a video display 13.Video signal source 11 can be the video signal having utilized H.264/AVC standard to carry out recasting or the transmission compressed and/or encode, wherein H.264/AVC standard adopts adaptive binary arithmetic coding (context-based adaptive binary arithmetic coding, CABAC) technology in full to carry out compressing and/or encoding.Video signal source 11 exports H.264/AVC signal and carries out decoding and reassemble into original video signal to video signal processor 12, exports video display 13 to again watch for user after completing by video signal processor 12.
Video signal processor 12 can comprise a processor, decoder 20 and a memory.This processor is in order to control the operation of video signal processor 12; Decoder 20 is in order to decode to the video signal transmitted; Memory is in order to deposit video signal, in order to be stored in the data and/or look-up table that use in decode procedure, and in order to be used as service area, in addition, memory is also used as the connection of different piece in doab and video signal processor 12.In addition, decoder 20 can comprise one or more register 25,40, one decision bit decoder (decision bin decoder) 35, and a bypass position decoder (bypass bin decoder) 30.
Fig. 2 is the position decoder 100 of every clock process position (bin-per-cycle) of video signal processing system 10.Position decoder 100 can comprise an offset register 101, one range registers 102, one state indices register 103, one reference least possible state (reference least probablestate, rLPS) look-up table 104, one least possible state (least probable state, LPS) look-up table 105, one most probable state (most probable state, MPS) look-up table 106, multiple adder 108, 109, multiple multiplexer 107, 110, 111, 112, one comparison module 113, one ruleization module 114 again, one state indices register 115, one range registers 116, one offset register 117, with an incoming bit stream 118.The information being stored in offset register 101, range registers 102 and state indices register 103 can be inputted by the output of the register 25 of the decoder 20 of Fig. 1, or in certain embodiments, offset register 101, range registers 102 and state indices register 103 are part compositions of the register 35 of Fig. 1.
The input of the input of rLPS look-up table 104, the input of MPS look-up table 106 and LPS look-up table 105 is coupled to the output of state indices register 103, the output of state indices register 103 exports current full text state (context state), and current full text state can be used to capture suitable value from rLPS look-up table 104, MPS look-up table 106, LPS look-up table 105.The output of MPS look-up table 106 is coupled to the first input end of multiplexer 112, the output of LPS look-up table 105 is coupled to the second input of multiplexer 112, and the most probable state that the first input end of multiplexer 112 exports in order to receive MPS look-up table 106, the second input of multiplexer 112 is in order to receive the least possible state of LPS look-up table 105 output.The input of multiplexer 107 is coupled to the output of rLPS look-up table 104, the control input end of multiplexer 107 is coupled to the output of range registers 102, the possible reference state that the input of multiplexer 107 exports in order to receive rLPS look-up table 104, the signal that the control input end of multiplexer 107 exports in order to range of receiving register 102, and the signal that range registers 102 exports is in order to control multiplexer 107.The output of multiplexer 107 is coupled to the first input end of adder 108 and the first input end of multiplexer 110, and the second input of adder 108 is coupled to the output of range registers 102.In adder 108, the signal that the range registers 102 that the second input of adder 108 receives exports will the signal of the output of multiplexer 107 that receives from the first input end of adder 108 of deduction.The output of adder 108 is coupled to the second input of multiplexer 110 and the first input end of adder 109, and the second input of adder 109 is coupled to the output of offset register 101.In adder 109, the signal that the offset register 101 that the second input of adder 109 receives exports will the signal of the output of adder 108 that receives from the first input end of adder 109 of deduction.The first input end of multiplexer 111 is coupled to the output of offset register 101, second input of multiplexer 111 is coupled to the output of adder 109, the first input end of multiplexer 111 is in order to receive the signal of offset register 101 output, and the second input of multiplexer 111 is in order to receive the difference of adder 109 output.
In addition, the output of adder 109 is also coupled to the input of comparison module 113, and the output of comparison module 113 is coupled to the control input end of multiplexer 111,110 and 112.The difference that comparison module 113 exports in order to receive adder 109, and judge the difference of adder 109 exports whether be less than zero.And the judged result that comparison module 113 exports is in order to control multiplexer 111,110 and 112.In addition, the output of multiplexer 112 is coupled to the input of state indices register 115, and the signal that multiplexer 112 exports is in order to upgrade state indices register 115.
Again the first input end of ruleization module 114 is in order to receive incoming bit stream 118, again the second input of ruleization module 114 is coupled to the output of multiplexer 111, in order to receive the signal that multiplexer 111 exports, again the 3rd input of ruleization module 114 is coupled to the output of multiplexer 110, in order to receive the signal that multiplexer 110 exports, again the first output of ruleization module 114 is coupled to the input of offset register 117, again the second input of ruleization module 114 is coupled to the input of range registers 116, wherein the signal of ruleization module 114 output is again in order to upgrade offset register 117 and range registers 116 in turn.Offset register 117 exports updated value 119 and range registers 116 exports updated value 120.Wherein updated value 119, updated value 120 are simultaneously used in the state indices register 115 upgraded next time in decode cycle.
The position decoder 300 of Fig. 3 is the schematic diagram that the position decoder 100 of Fig. 2 comprises critical path.In figure 3, position decoder 300 illustrates how the critical path (critical path) of the position decoder of every clock process position (bin-per-cycle) becomes a design subject under discussion.As shown in Figure 3, the critical path of the position decoder 300 of every clock process position (bin-per-cycle) from the output of state indices register 103 through rLPS look-up table 104, multiplexer 107, adder 108, adder 109, comparison module 113, multiplexer 111, again ruleization module 114 and the offset register 117 that arrives.The signal that the range registers 102 that the control input end of multiplexer 107 receives exports in order to determine the output of rLPS look-up table 104 multiple signals in which signal need be passed to adder 108 via multiplexer 107.In adder 108, the signal that deduction exports from the multiplexer 107 that the first input end of adder 108 receives by the signal that the range registers 102 that the second input of adder 108 receives exports.In adder 109, the signal that the offset register 101 that the second input of adder 109 receives exports will the signal of the output of adder 108 that receives from the first input end of adder 109 of deduction.The input of comparison module 113 is in order to receive the difference of adder 109 output, and the judged result of comparison module 113 is then in order to control multiplexer 111.The signal that multiplexer 111 exports is supplied to again ruleization module 114 in order to upgrade offset register 117, and the updated value 119 exported by offset register 117 will be used in next time in decode cycle.Therefore, the critical path of the position decoder 300 of Fig. 3 ends at the output of offset register 117.But, the disposal ability of the position decoder 300 of every clock process position (bin-per-cycle) is that be not high enough to can in order to real-time decoding H.264/AVC video signal, particularly when processing high resolution image, the disposal ability of position decoder 300 is more inadequate.
In order to increase disposal ability, the position decoder 400 of every clock process two positions as shown in Figure 4 to be decoded a position except being used to every clock, also can often to decode two positions by clock.Fig. 4 is the schematic diagram of the position decoder 400 of every clock process two positions that one embodiment of the invention disclose.Position decoder 400 comprises register 405,1 first decision bit decoder 407, two multiplexer 415, a 409 and 1 second decision bit decoder 420.Register 405 is coupled to the first decision bit decoder 407 and multiplexer 409.First decision bit decoder 407 is coupled to multiplexer 415, multiplexer 409 and the second decision bit decoder 420.The output of the first decision bit decoder 407 exports the RLPS1 signal of Offset1, Range1 and adjoint more new state, wherein Offset1 and Range1 is received by the second decision bit decoder 420, but RLPS signal then inputs to multiplexer 415 along with the CTX2 RLPS/CTX2 State signal of outside.Multiplexer 415 controls and export selected results to the second decision bit decoder 420 by a Source select signal.Output output signal Offset2, Range2, RLPS2 and NextST of second decision bit decoder 420, wherein second decision bit decoder 420 export signal Offset2, Range2, RLPS2 and NextST can with the RLPS1 signal from the first decision bit decoder 407 in the lump input multiplexer 409.The signal that multiplexer 409 exports then passes back to register 405, therefore can start another circulation.
Although, for the high-resolution video signal of H.264/AVC standard, the position decoder of every clock process two positions has acceptable disposal ability, but its critical path remains the subject under discussion of design, but effectively can to shorten the critical path of the position decoder of every clock process two positions to the mode of previous stage through rearranging decoding process and mobile look-up table.The position decoder of every clock process two positions can be realized according to the framework of Fig. 5.
Please refer to Fig. 5 and Fig. 6.Fig. 5 illustrates that the first decision bit decoder 500, Fig. 6 illustrates the second decision bit decoder 600, and the connection relationship between the first decision bit decoder 500 and the second decision bit decoder 600.In Figure 5, the first decision bit decoder 500 comprises offset register 501, range registers 502, rLPS register 550, state indices register 503, MPS state look-up table 506, LPS state look-up table 505, the one rLPS look-up table 552, a 2nd rLPS look-up table 555, multiplexer 515-519, adder 508-509, state indices register 530, comparison module 513 and ruleization module 514 again.In figure 6, second decision bit decoder 600 comprises multiple multiplexer 610,616,623,618,620,621,622, one ruleization module 635 again, multiple adder 641,643, rLPS look-up table 652, MPS state look-up table 612, one LPS state look-up table 611, one the one rLPS look-up table 614, one the 2nd rLPS look-up table 613, and a comparison module 630.The input of MPS state look-up table 506 and the input of LPS state look-up table 505 are coupled to the output of state indices register 503, the current state that MPS state look-up table 506 and LPS state look-up table 505 export in order to accepting state index register 503.The input of the one rLPS look-up table 552 and the first input end of multiplexer 515 are coupled to the output of MPS state look-up table 506, in order to receive the most probable state selected by MPS state look-up table 506.The first input end of multiplexer 516 is coupled to the output of a rLPS look-up table 552, in order to receive one 32 signals that a rLPS look-up table 552 exports.The input of the 2nd rLPS look-up table 555 and the second input of multiplexer 515 are coupled to the output of LPS state look-up table 505, in order to receive the least possible state selected by LPS state look-up table 505, second input of multiplexer 516 is coupled to the output of the 2nd rLPS look-up table 555, in order to receive one 32 signals that the 2nd rLPS look-up table 555 exports.
The first input end of adder 508 and the first input end of multiplexer 517 are coupled to the output of rLPS register 550, second input of adder 508 is coupled to the output of range registers 502, the signal that the first input end of multiplexer 517 and the first input end of adder 508 export in order to receive rLPS register 550, the signal that the second input of adder 508 exports in order to range of receiving register 502.In adder 508, the signal that range registers 502 exports will deduct the signal exported from rLPS register 550, the output of adder 508 is coupled to the second input of multiplexer 517 and the second input of adder 509, the signal that the second input of adder 509 and the second input of multiplexer 517 export in order to receive adder 508.The output of offset register 501 is coupled to the first input end of adder 509 and the first input end of multiplexer 518, and the signal that the first input end of the first input end of multiplexer 518 and adder 509 exports in order to receive offset register 501.In adder 509, the signal that offset register 501 exports will deduct the signal exported from adder 508.Second input of multiplexer 518 is coupled to the output of adder 509, in order to receive the difference that adder 509 exports.The output of adder 509 is also coupled to the input of comparison module 513, and the input of comparison module 513 is in order to receive the difference of adder 509 output, and comparison module 513 judges the difference of adder 509 exports whether be less than zero.The output of comparison module 513 is coupled to the control input end of multiplexer 518,517,516 and 515, and wherein the judged result of comparison module 113 is in order to control multiplexer 518,517,516 and 515.
In addition, the output of multiplexer 515 is coupled to the input of state indices register 530, and the signal that multiplexer 515 exports is in order to upgrade state indices register 530.State indices register 530 can export the first input end (as shown in Figure 6) of the multiplexer 610 of state to the second decision bit decoder 600 of renewal in turn.Similarly, the first input end of multiplexer 519 is coupled to the output of multiplexer 516, second input of multiplexer 519 is coupled to another rLPS look-up table, after multiplexer 519 receives the signal exported from multiplexer 516 and another rLPS look-up table, by the first input end of the multiplexer 616 of output one 32 signal to the second decision bit decoders 600.Again the first input end of ruleization module 514 is in order to receive incoming bit stream 520, the signal that second input exports in order to receive multiplexer 518, the signal that 3rd input exports in order to receive multiplexer 517, then the skew signal that the first output that the first input end of multiplexer 623 and the first input end of adder 641 receive again ruleization module 514 exports, second input of adder 643 receives again the scope signal of the second output output of ruleization module 514, again the shifted bits stream (shifted bitstream) that the 3rd output that ruleization module 635 receives again ruleization module 514 exports, and the control input end of multiplexer 618 receives again 2 highest significant positions (the Most Significant Bit in the scope signal of the second output output of ruleization module 514, MSB) signal (as shown in Figure 6) is controlled as it.
Second input of multiplexer 610 and the input of rLPS look-up table 652 receive a StateIndex2 signal.Second input of multiplexer 616 is coupled to the output of rLPS look-up table 652, in order to receive the signal (first input end of multiplexer 616 is coupled to multiplexer 519, in order to receive the rLPS signal exported from multiplexer 519) that rLPS look-up table 652 exports.The control input end of multiplexer 610 and multiplexer 616 then receives a Stage2_Source_Se1 signal, and the control signal that Stage2_Source_Se1 signal is used for as multiplexer 610 and multiplexer 616.
The input of MPS state look-up table 612 and the input of LPS state look-up table 611 are coupled to the output of multiplexer 610, in order to receive the signal that multiplexer 610 exports.The input of the one rLPS look-up table 614 and the first input end of multiplexer 620 are coupled to the output of MPS state look-up table 612, in order to receive the most probable state selected by MPS state look-up table 612.The first input end of multiplexer 621 is coupled to the output of a rLPS look-up table 614, in order to receive one 32 signals that a rLPS look-up table 614 exports.The input of the 2nd rLPS look-up table 613 and the second input of multiplexer 620 are coupled to the output of LPS state look-up table 611, in order to receive the least possible state selected by LPS state look-up table 611.Second input of multiplexer 621 is coupled to the output of the 2nd rLPS look-up table 613, in order to receive 32 signals that the 2nd rLPS look-up table 613 exports.
The input of multiplexer 618 is coupled to the output of multiplexer 616; According to the selection of Stage2_Source_Se1 signal, multiplexer 618 can receive 1 group of 8 signal that multiplexer 616 exports, multiplexer 618 is then subject to controlling from 2 highest significant position signals of rule module 514 again, exports the first input end of 1 group of 8 signal to adder 643 and the first input end of multiplexer 622.Second input of multiplexer 622 and the second input of adder 641 are coupled to the output of adder 643.In adder 643, after 1 group of 8 signal that the scope signal exported deduction exports from multiplexer 618 by adder 643, export difference multiplexer 622 and adder 641 at the most from rule module 514 again.In adder 641, adder 641 deducts from the skew signal that rule module 514 exports again the difference signal exported from adder 643.Second input of multiplexer 623 is coupled to the output of adder 641, in order to receive the difference that adder 641 exports.The output of adder 641 is also coupled to the input of comparison module 630, and the input of comparison module 630 is in order to receive the difference of adder 641 output, and comparison module 630 judges the difference of adder 641 exports whether be less than zero.The output of comparison module 630 is coupled to the control input end of multiplexer 623,622,621 and 620, and wherein the judged result of comparison module 630 is in order to control multiplexer 623,622,621 and 620.Again the first input end of ruleization module 635 is in order to receive the shifted bits stream from the module of ruleization again 514 of the first decision bit decoder 500, second input is coupled to the output of multiplexer 623, in order to receive the signal that multiplexer 623 exports, 3rd input is coupled to the output of multiplexer 622, in order to receive the signal that multiplexer 622 exports, the offset register 501 of the first output output one skew signal to the first decision bit decoder 500 and the second output export the range registers 502 of scope signal to a first decision bit decoder 500.And offset register 501 and range registers 502 are by the skew signal that recycles at next from rule module 635 again and scope signal.Similarly, the signal that the signal that multiplexer 621 exports delivers to rLPS register 550 and multiplexer 620 output delivers to state indices register 503, allows the first decision bit decoder 500 recycle at next.
Fig. 7 and Fig. 8 is the critical path between detail bit decoder 500 and position decoder 600.As shown in Figure 7 and Figure 8, a critical path is had to start from the output of range registers 502 through adder 508 between position decoder 500 and position decoder 600, adder 509 is extended to again by the output of adder 508, continue to extend to comparison module 513 from the output of adder 509, through the output of multiplexer 517 after it, again via the output of rule module 514 again to adder 643, continue to extend to adder 641 from the output of adder 643, then comparison module 630 is arrived again, finally, the signal exported by comparison module 630 go to control multiplexer 623 via rule module 635 again export next circulation the skew signal of palpus.
In summary, compared with traditional design, the length that the critical path of the position decoder of every clock process two positions is come than the position decoder of every clock process position.But the mode rearranging decoding process and mobile look-up table that the present invention proposes reduces the length of critical path.Design of the present invention demonstrates and reduce by 33% in time demand.Such as, before improving without the present invention, the frequency of the position decoder of every clock process two positions is 150MHz (Fujitsu 90nm technique), but adopt proposed by the invention rearrange decoding process after, the frequency of the position decoder of every clock process two positions can be promoted to 225MHz.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. a binary arithmetic operation decoding device for high operation frequency, comprises;
One first look-up table, has the output that an input is coupled to one first register, in order to receive the signal that this first register exports;
One second look-up table, has the output that an input is coupled to this first register, in order to receive the signal that this first register exports;
One the 3rd look-up table, has the output that an input is coupled to this first look-up table, in order to receive the signal that this first look-up table exports;
One the 4th look-up table, has the output that an input is coupled to this second look-up table, in order to receive the signal that this second look-up table exports;
One first multiplexer, has the output that a first input end is coupled to the 3rd look-up table, and in order to receive the signal that the 3rd look-up table exports, one second input is coupled to the output of the 4th look-up table, in order to receive the signal that the 4th look-up table exports; And
One second multiplexer, has the output that a first input end is coupled to this first look-up table, and in order to receive the signal that this first look-up table exports, one second input is coupled to the output of this second look-up table, in order to receive the signal that this second look-up table exports;
Wherein this first multiplexer and this second multiplexer are all controlled by one first signal.
2. binary arithmetic operation decoding device as claimed in claim 1, also comprise one second register of coupled in series, a first adder, a second adder and one first comparison module, this first comparison module is in order to export this first signal.
3. binary arithmetic operation decoding device as claimed in claim 1, also comprises:
One the 3rd multiplexer, has a first input end is coupled to this second multiplexer output by one the 3rd register, in order to receive the signal that this second multiplexer exports;
One the 5th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports;
One the 6th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports;
One the 7th look-up table, has the output that an input is coupled to the 5th look-up table, in order to receive the signal that the 5th look-up table exports;
One the 8th look-up table, has the output that an input is coupled to the 6th look-up table, in order to receive the signal that the 6th look-up table exports;
One the 4th multiplexer, has the output that a first input end is coupled to the 7th look-up table, and in order to receive the signal that the 7th look-up table exports, one second input is coupled to the output of the 8th look-up table, in order to receive the signal that the 8th look-up table exports; And
One the 5th multiplexer, has the output that a first input end is coupled to the 5th look-up table, and in order to receive the signal that the 5th look-up table exports, one second input is coupled to the output of the 6th look-up table, in order to receive the signal that the 6th look-up table exports;
Wherein the 4th multiplexer and the 5th multiplexer are all controlled by one second signal.
4. binary arithmetic operation decoding device as claimed in claim 3, wherein the input of this first register is coupled to the output of the 5th multiplexer, in order to store the signal that the 5th multiplexer exports.
5. binary arithmetic operation decoding device as claimed in claim 3, also comprise one the 3rd adder of coupled in series, one the 4th adder and one second comparison module, this second comparison module is in order to export this second signal.
6. binary arithmetic operation decoding device as claimed in claim 5, also comprises:
One the 6th multiplexer, has the output that a first input end is coupled to this first multiplexer, in order to receive the signal that this first multiplexer exports.
7. binary arithmetic operation decoding device as claimed in claim 6, also comprises:
One the 7th multiplexer, has the output that a first input end is coupled to the 6th multiplexer, and in order to receive the signal that the 6th multiplexer exports, one second input is coupled to the output of one the 9th look-up table, in order to receive the signal that the 9th look-up table exports; And
One the 8th multiplexer, has the output that an input is coupled to the 7th multiplexer, the signal that the output in order to receive the 7th multiplexer exports.
8. binary arithmetic operation decoding device as claimed in claim 7, wherein the 3rd multiplexer and the 7th multiplexer are all controlled by one the 3rd signal.
9. binary arithmetic operation decoding device as claimed in claim 7, wherein the first input end of the 3rd adder is coupled to the output of the 8th multiplexer, in order to receive the signal that the 8th multiplexer exports.
10. binary arithmetic operation decoding device as claimed in claim 7, also comprises:
One the 4th register, has an output and is coupled to the first input end of second adder and the first input end of one the 9th multiplexer, and wherein this second adder and the 9th multiplexer are in order to receive the signal of the 4th register output.
11. binary arithmetic operation decoding devices as claimed in claim 10, also comprise:
One the 5th register, has an output and is coupled to the first input end of first adder and the first input end of 1 the tenth multiplexer, and wherein this first adder and the tenth multiplexer are in order to receive the signal of the 5th register output.
12. binary arithmetic operation decoding devices as claimed in claim 11, also comprise:
One ruleization module again, there is a first input end in order to receive an incoming bit stream, one second input is coupled to the output of the 9th multiplexer, in order to receive the signal that the 9th multiplexer exports, one the 3rd input is coupled to the output of the tenth multiplexer, in order to receive the signal that the tenth multiplexer exports, one first output is coupled to the first input end of the 4th adder, one second output is coupled to the second input of the 3rd adder, wherein the first input end of the 4th adder and the second input of the 3rd adder are in order to receive the signal of this rule module output again.
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| US6574651B1 (en) * | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
| CN1773868A (en) * | 2004-11-08 | 2006-05-17 | 联发科技股份有限公司 | Path equity operating method and related apparatus for fast witt ratio detector |
| CN101145790A (en) * | 2006-12-08 | 2008-03-19 | 威盛电子股份有限公司 | Decoder, addition-comparison-selection unit and its method |
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| US6574651B1 (en) * | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
| CN1773868A (en) * | 2004-11-08 | 2006-05-17 | 联发科技股份有限公司 | Path equity operating method and related apparatus for fast witt ratio detector |
| CN101145790A (en) * | 2006-12-08 | 2008-03-19 | 威盛电子股份有限公司 | Decoder, addition-comparison-selection unit and its method |
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