CN102223147A - On-line rapid automatic frequency calibration circuit for frequency synthesizer and method thereof - Google Patents
On-line rapid automatic frequency calibration circuit for frequency synthesizer and method thereof Download PDFInfo
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- CN102223147A CN102223147A CN 201110082152 CN201110082152A CN102223147A CN 102223147 A CN102223147 A CN 102223147A CN 201110082152 CN201110082152 CN 201110082152 CN 201110082152 A CN201110082152 A CN 201110082152A CN 102223147 A CN102223147 A CN 102223147A
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Abstract
The invention discloses an on-line rapid automatic frequency calibration circuit for frequency synthesizer and a method thereof. The automatic frequency calibration circuit mainly comprises a rapid charge and discharge circuit (21), a comparator circuit (22) and a digital logic processing circuit. The calibration method in the invention adopts closed loop calibration. The main thinking is taking capacitance array as expansion of variable capacitance and imitating establishment process of phase-locked loop only with variable capacitance and without capacitance array to integrate automatic frequency calibration process and the phase-locked loop establishment process as one body. According to the invention, calibration time of frequency synthesizer is reduced, thus output frequency of the frequency synthesizer can be switched rapidly.
Description
Technical field
The invention belongs to electronic technology field, specifically be suitable for but be not limited to the fast frequency calibration steps and the circuit of radio frequency transceiver medium frequency synthesizer.
Background technology
At present, in transceiver, frequency synthesizer is used for producing programmable accurate oscillator signal, as shown in Figure 1, it is generally by reference oscillator 11, phase frequency detector 12, charge pump 13, loop filter 14,, voltage controlled oscillator 15 and frequency divider 16 constitute.The frequency synthesizer that can produce the fractional frequency division ratio generally also comprises sigma-delta modulator 17.Wherein the reference frequency output of frequency synthesizer 29 depends on the reference frequency output of voltage controlled oscillator 15, and for obtaining lower phase noise, voltage controlled oscillator is generally realized with voltage controlled oscillator.Such oscillator phase is lower, but voltage controlled gain is also lower, and low voltage controlled gain helps optimizing the noise of phase-locked loop, but makes the oscillator reference frequency output also less.In order to obtain the reference frequency output of broad, the capacitor and inductor voltage controlled oscillator all can be realized many tuning curves by switched capacitor array 18 usually.Can under low voltage controlled gain, cover bigger frequency range like this.
Traditional automatic frequency calibration circuit 19 is general to adopt the open loops calibration, exports with reference to output and frequency divider with two counters 120 and 121 pairs respectively and counts.Judge the magnitude relationship of two frequencies then by count value, again capacitor array is made corresponding change.Binary search algorithm is used in being provided with of capacitor array, from a high position, determines the every height of residue successively.Detailed process is as follows:
1. earlier with the be connected disconnection of loop filter, give fixing current potential of voltage controling end (being generally half supply voltage) of voltage controlled oscillator, capacitor array extreme higher position 1 with voltage controlled oscillator;
2. in a predefined set time, count reference oscillator output and frequency divider output simultaneously with two counters;
3. after counting finished, relatively two numerical value judged which frequency is faster, the height of corresponding setting next bit capacitor array control bit.
4.. repeating step 2 and 3 up to the height that can not differentiate two frequencies, illustrate that the difference of two frequencies has met the requirements of precision.
5. disconnection alignment loop, connected ring path filter and voltage controlled oscillator make frequency synthesizer enter locking process.
Above-mentioned method has some intrinsic shortcomings.Because sub-band is narrower, mean that difference on the frequency is less between each frequency band, so counter need be counted the difference on the frequency that could differentiate requirement than the multicycle; When beginning to count, the phase place of two inputs is uncertain, also needs more count cycles just can balance out the error that initial phase causes; More all to count the fixed cycle number at every turn, can not adapt to automatically, cause the waste of alignment time; The simultaneously overall alignment time also can be increased and becomes big with the capacitor array figure place.Above-mentioned shortcoming all makes the time of frequency automatic calibration longer.The calibration of open loop simultaneously need be inserted switch, the performance when influencing the frequency synthesizer operate as normal at the input of voltage controlled oscillator.For the decimal frequency synthesizer, in calibration process, also to close the sigma-delta modulator.
Along with technology constantly develops, people are more and more higher to the requirement of radio communication, such as requiring same transceiver can satisfy different communication standards, cover a plurality of frequency ranges, broadband not only increases circuit complexity, make the improvement of noise difficult more, also make the alignment time of frequency synthesizer longer, use traditional automatic frequency collimation technique to be difficult to reach the requirement of some communication standard.
Summary of the invention
The technical issues that need to address of the present invention are to provide a kind of alignment time that reduces frequency synthesizer, the online fast automatic frequency calibration circuit and the method that are used for frequency synthesizer that its output frequency can be switched fast.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the online fast automatic frequency calibration circuit of frequency synthesizer mainly includes the fast charging and discharging circuit, comparator circuit and Digital Logic treatment circuit;
Described fast charging and discharging circuit has a control end and discharge and recharge output, discharges and recharges output T-Ring path filter, when the control end signal when low, fast charging and discharging circuit output high-impedance state discharges and recharges the not influence of voltage on the output; When control end signal when being high, the fast charging and discharging circuit is moved the voltage that discharges and recharges output to half supply voltage fast;
Described comparator input terminal connects the output that discharges and recharges of fast charging and discharging circuit, comparator is connected to control end, two outputs of comparator and export to the Digital Logic treatment circuit, comparator has two threshold values of height, when control end is low level, if the voltage of input is higher than the high threshold of setting, output just becomes high level, and output remains low level simultaneously; If be lower than the low threshold value of setting, then output becomes high level, and simultaneously output remains low level, when control end is high level, and two outputs and all by zero setting;
Decision increases or reduces the electric capacity number of opening in the capacitor array to described Digital Logic treatment circuit according to input condition, behind each change capacitor array, give fast charging and discharging circuit and comparator circuit by control end output asserts signal, the fast charging and discharging circuit is turn-offed, make two outputs of comparator circuit and be low level.
A kind of as above-mentioned calibration steps of the online fast automatic frequency calibration circuit that is used for frequency synthesizer comprises the steps:
1) the Digital Logic treatment circuit is with the capacitor array control word high position 1 of voltage controlled oscillator, promptly open half capacitor array, making control end is high level, and the fast charging and discharging circuit will be moved half supply voltage place to discharging and recharging output, and the output of comparator simultaneously is set as low level; The high level of control end becomes low level after keeping 2 clock cycle, make fast charging and discharging circuit output high resistant, phase-locked loop circuit just disconnects with the automatic frequency calibration circuit like this, phase-locked loop is set up process with freedom of entry then, and comparator also discharges and recharges monitoring the voltage on the output and can react;
2) freely set up in the process at phase-locked loop, if the phase lag of frequency divider output is in the phase place of reference oscillator output, then discharging and recharging output is recharged, voltage raises, if be elevated to the high threshold place of comparator, then comparator output terminal becomes high level, the electric capacity number that the Digital Logic treatment circuit will reduce to open in the capacitor array, otherwise if comparator output terminal becomes high level, the Digital Logic treatment circuit will increase the electric capacity number of opening in the capacitor array;
3) after the electric capacity change is finished, at the control end high level signal of two clock cycle of output, in at this moment, the fast charging and discharging circuit will be moved half supply voltage to discharging and recharging output end voltage again, comparator output also will be by zero setting, and the high level of control end finishes the back phase-locked loop and enters the process of foundation once more;
4) repeating step 2) and step 3), up to finding correct capacitor array configuration.
In the above-mentioned method, the change that inserts the electric capacity number in the capacitor array is divided into two stages, and the adjusting of electric capacity number is the process of binary search in first stage capacitor array, and the change of electric capacity all reduced by half than the last time at every turn; Second stage then is to do to increase one or subtract one adjusting on existing basis, up to finding final capacitor array configuration.
Beneficial effect of the present invention: circuit of the present invention is realized simple and reliable, can be when decimal frequency divider be worked in-service monitoring, implement frequency calibration automatically; Avoid long shortcoming of rolling counters forward time in the conventional calibration method, used this method to reduce the alignment time greatly; The closed loop calibration structure need not disconnect loop; Avoid calibration circuit when frequency synthesizer is worked, to have a negative impact.
Description of drawings
Fig. 1 is the frame diagram that adopts the frequency synthesizer of traditional automatic frequency calibration circuit.
Fig. 2 is the frame diagram that adopts the frequency synthesizer of automatic frequency calibration circuit of the present invention.
The flow chart of Fig. 3 calibration steps of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
The frame diagram of the frequency synthesizer of the automatic frequency calibration circuit of the present invention of employing as shown in Figure 2, the structure of frequency synthesizer is a prior art, is not described in detail.The online fast automatic frequency calibration circuit of frequency synthesizer of the present invention mainly includes fast charging and discharging circuit 21, comparator circuit 22 and Digital Logic treatment circuit 23;
Described fast charging and discharging circuit 21 has a control end 25 and discharges and recharges output 26, discharges and recharges output 26 T-Ring path filters, when control end 25 signals when low, fast charging and discharging circuit output high-impedance state discharges and recharges the not influence of voltage on the output 26; When control end 25 signals when being high, fast charging and discharging circuit 21 is fast discharging and recharging the input that output 26(is a loop filter 14) voltage move half supply voltage to; Though when it filled (putting) electricity, charge pump 13 is also simultaneously in work, and was bigger because it fills (putting) electric current, so do not influence the realization of drawing the level function.
Described comparator 22 input termination fast charging and discharging circuit 21 discharge and recharge output 26, comparator 22 is connected to control end 25, two outputs 27 of comparator 22 and 28 are exported to Digital Logic treatment circuit 23, comparator has two threshold values of height, when control end 25 is low level, if the voltage of input is higher than the high threshold of setting, output 28 just becomes high level, and output 27 remains low level simultaneously; If be lower than the low threshold value of setting, then output 27 becomes high level, and simultaneously output 28 remains low level, and when control end 25 was high level, two outputs 27 and 28 were all by zero setting;
Decision increases or reduces the electric capacity number of opening in the capacitor array to described Digital Logic treatment circuit 23 according to input condition, behind each change capacitor array, give fast charging and discharging circuit 21 and comparator circuit 22 by control end 25 output asserts signal, the fast charging and discharging circuit is turn-offed, make two outputs 27 and 28 of comparator circuit 22 be low level.
Calibration steps of the present invention adopts closed loop calibration, main thought is with the expansion of capacitor array as variable capacitance, imitation has only variable capacitance and the process of setting up of phase-locked loop when not having capacitor array, and the automatic frequency calibration process is integrated with the process of setting up of phase-locked loop.
When initialization, open half electric capacity of capacitor array, promptly only with the high position 1 of capacitor array control bit.Simultaneously control voltage of voltage-controlled oscillator is moved to centered level, phase-locked loop begins to enter the process of foundation.If voltage controlled oscillator control voltage drops to certain level, then reduce the electric capacity number that capacitor array inserts; Otherwise,, then open the more electric capacity in the capacitor array if control voltage is elevated to a certain level.Regulate repeatedly up to finding correct capacitor array configuration.
Use this calibration steps frequency synthesizer the process of setting up as shown in Figure 3, wherein N is the figure place of capacitor array 120 in the voltage controlled oscillator 15.Step process is described below:
1) Digital Logic treatment circuit 23 is with the capacitor array control word high position 1 of voltage controlled oscillator, promptly open half capacitor array, make control end 25 be high level, fast charging and discharging circuit 21 will be moved half supply voltage place to discharging and recharging output 26, and the output of comparator 22 simultaneously is set as low level; The high level of control end 25 becomes low level after keeping 2 clock cycle, make fast charging and discharging circuit 21 output high resistants, phase-locked loop circuit just disconnects with the automatic frequency calibration circuit like this, phase-locked loop is set up process with freedom of entry then, and comparator also discharges and recharges monitoring the voltage on the output 26 and can react;
2) freely set up in the process at phase-locked loop, if the phase lag of frequency divider output is in the phase place of reference oscillator output, then discharging and recharging output 26 is recharged, voltage raises, if be elevated to the high threshold place of comparator 22, then comparator output terminal 28 becomes high level, for improving the output frequency of voltage controlled oscillator, and then the frequency of raising frequency divider output node, the electric capacity number that Digital Logic treatment circuit 23 will reduce to open in the capacitor array, otherwise if comparator output terminal 27 becomes high level, Digital Logic treatment circuit 23 will increase the electric capacity number of opening in the capacitor array;
3) after the electric capacity change is finished, at the control end high level signal of 25 two clock cycle of output, in at this moment, the fast charging and discharging circuit will be moved half supply voltage to discharging and recharging output 26 voltages again, comparator output also will be by zero setting, and the high level of control end 25 finishes the back phase-locked loop and enters the process of foundation once more;
4) repeating step 2) and step 3), up to finding correct capacitor array configuration.
In the above-mentioned method, the change that inserts the electric capacity number in the capacitor array is divided into two stages, and the adjusting of electric capacity number is the process of binary search in first stage capacitor array, and the change of electric capacity all reduced by half than the last time at every turn; Second stage then is to do to increase one or subtract one adjusting on existing basis, up to finding final capacitor array configuration.
In a word; though the present invention has exemplified above-mentioned preferred implementation, should illustrate, though those skilled in the art can carry out various variations and remodeling; unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included in protection scope of the present invention.
Claims (3)
1. an online fast automatic frequency calibration circuit that is used for frequency synthesizer is characterized in that: mainly include fast charging and discharging circuit (21), comparator circuit (22) and Digital Logic treatment circuit (23);
Described fast charging and discharging circuit (21) has a control end (25) and discharges and recharges output (26), discharge and recharge output (26) T-Ring path filter, when control end (25) signal when low, fast charging and discharging circuit output high-impedance state discharges and recharges the not influence of voltage on the output (26); When control end (25) signal when being high, fast charging and discharging circuit (21) is moved the voltage that discharges and recharges output (26) to half supply voltage fast;
Described comparator (22) input termination fast charging and discharging circuit (21) discharge and recharge output (26), comparator (22) is connected to control end (25), Digital Logic treatment circuit (23) is exported in two outputs (27) and (28) of comparator (22), comparator has two threshold values of height, when control end (25) is low level, if the voltage of input is higher than the high threshold of setting, output (28) just becomes high level, and output (27) remains low level simultaneously; If be lower than the low threshold value of setting, then output (27) becomes high level, and output (28) remains low level simultaneously, and when control end (25) was high level, two outputs (27) and (28) were all by zero setting;
Decision increases or reduces the electric capacity number of opening in the capacitor array to described Digital Logic treatment circuit (23) according to input condition, behind each change capacitor array, give fast charging and discharging circuit (21) and comparator circuit (22) by control end (25) output asserts signal, the fast charging and discharging circuit is turn-offed, make two outputs (27) and (28) of comparator circuit (22) be low level.
2. a calibration steps that is used for the online fast automatic frequency calibration circuit of frequency synthesizer as claimed in claim 1 is characterized in that, comprises the steps:
1) Digital Logic treatment circuit (23) is with the capacitor array control word high position 1 of voltage controlled oscillator, promptly open half capacitor array, making control end (25) is high level, fast charging and discharging circuit (21) will be moved half supply voltage place to discharging and recharging output (26), and the output of comparator (22) simultaneously is set as low level; The high level of control end (25) becomes low level after keeping 2 clock cycle, make fast charging and discharging circuit (21) output high resistant, phase-locked loop circuit just disconnects with the automatic frequency calibration circuit like this, phase-locked loop is set up process with freedom of entry then, and comparator also discharges and recharges monitoring the voltage on the output (26) and can react;
2) freely set up in the process at phase-locked loop, if the phase lag of frequency divider output is in the phase place of reference oscillator output, then discharging and recharging output (26) is recharged, voltage raises, if be elevated to the high threshold place of comparator (22), then comparator output terminal (28) becomes high level, the electric capacity number that Digital Logic treatment circuit (23) will reduce to open in the capacitor array, otherwise, if comparator output terminal (27) becomes high level, Digital Logic treatment circuit (23) will increase the electric capacity number of opening in the capacitor array;
3) after the electric capacity change is finished, at control end (25) high level signal of two clock cycle of output, in at this moment, the fast charging and discharging circuit will be moved half supply voltage to discharging and recharging output (26) voltage again, comparator output also will be by zero setting, and the high level of control end (25) finishes the back phase-locked loop and enters the process of foundation once more;
4) repeating step 2) and step 3), up to finding correct capacitor array configuration.
3. in accordance with the method for claim 2, it is characterized in that: the change that inserts the electric capacity number in the described capacitor array is divided into two stages, the adjusting of electric capacity number is the process of binary search in first stage capacitor array, and the change of electric capacity all reduced by half than the last time at every turn; Second stage then is to do to increase one or subtract one adjusting on existing basis, up to finding final capacitor array configuration.
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| CN102522984A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Phase-locked loop and voltage-controlled oscillating circuit thereof |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
| CN103036560A (en) * | 2012-12-13 | 2013-04-10 | 广州润芯信息技术有限公司 | Phase-locked loop and circuit and method of closed loop frequency self-calibration of phase-locked loop |
| CN103078636A (en) * | 2012-12-27 | 2013-05-01 | 四川和芯微电子股份有限公司 | Phase-locked loop system |
| CN104022738A (en) * | 2014-05-23 | 2014-09-03 | 中国电子科技集团公司第四十一研究所 | Phase-locked loop automatic presetting system and presetting method thereof |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104283553A (en) * | 2013-07-02 | 2015-01-14 | 成都国腾电子技术股份有限公司 | Self-calibration system for helping frequency source circuit losing lock due to temperature change be locked again |
| CN104579330A (en) * | 2015-01-20 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Two-step automatic frequency calibration circuit and method of phase-locked loop |
| CN105897260A (en) * | 2016-04-15 | 2016-08-24 | 武汉大学 | Auto frequency calibration circuit used for radio frequency phase-locked loop and calibrating method |
| CN110113048A (en) * | 2019-05-17 | 2019-08-09 | 芯翼信息科技(南京)有限公司 | Clock calibration circuit and clock correcting method based on phaselocked loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102522984A (en) * | 2011-12-31 | 2012-06-27 | 杭州士兰微电子股份有限公司 | Phase-locked loop and voltage-controlled oscillating circuit thereof |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
| CN102970031B (en) * | 2012-11-05 | 2015-04-08 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer |
| CN103036560A (en) * | 2012-12-13 | 2013-04-10 | 广州润芯信息技术有限公司 | Phase-locked loop and circuit and method of closed loop frequency self-calibration of phase-locked loop |
| CN103036560B (en) * | 2012-12-13 | 2016-01-13 | 广州润芯信息技术有限公司 | Phase-locked loop, its closed loop frequency auto-calibration circuits and method |
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| CN104283553B (en) * | 2013-07-02 | 2017-07-04 | 成都振芯科技股份有限公司 | It is a kind of to help vary with temperature and self-calibration system that the frequency source circuit of losing lock is locked again |
| CN104283553A (en) * | 2013-07-02 | 2015-01-14 | 成都国腾电子技术股份有限公司 | Self-calibration system for helping frequency source circuit losing lock due to temperature change be locked again |
| CN104022738B (en) * | 2014-05-23 | 2016-11-23 | 中国电子科技集团公司第四十一研究所 | Phaselocked loop automatic pre-set system and pre-setting method thereof |
| CN104022738A (en) * | 2014-05-23 | 2014-09-03 | 中国电子科技集团公司第四十一研究所 | Phase-locked loop automatic presetting system and presetting method thereof |
| CN104038215B (en) * | 2014-06-13 | 2017-06-09 | 南京邮电大学 | A kind of ∑ △ fractional frequencies synthesizer automatic frequency calibration circuit |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104579330A (en) * | 2015-01-20 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Two-step automatic frequency calibration circuit and method of phase-locked loop |
| CN105897260A (en) * | 2016-04-15 | 2016-08-24 | 武汉大学 | Auto frequency calibration circuit used for radio frequency phase-locked loop and calibrating method |
| CN105897260B (en) * | 2016-04-15 | 2018-12-14 | 武汉大学 | A kind of fast automatic frequency calibration circuit and calibration method for RF Phase-Lock Loop |
| CN110113048A (en) * | 2019-05-17 | 2019-08-09 | 芯翼信息科技(南京)有限公司 | Clock calibration circuit and clock correcting method based on phaselocked loop |
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