CN102237145A - Clamped storage device and testing method thereof - Google Patents

Clamped storage device and testing method thereof Download PDF

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Publication number
CN102237145A
CN102237145A CN201010167944XA CN201010167944A CN102237145A CN 102237145 A CN102237145 A CN 102237145A CN 201010167944X A CN201010167944X A CN 201010167944XA CN 201010167944 A CN201010167944 A CN 201010167944A CN 102237145 A CN102237145 A CN 102237145A
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data
memory storage
signal processing
group
signal
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薛念宗
谢晋升
陈俊宏
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Novatek Microelectronics Corp
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Novatek Microelectronics Corp
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Abstract

The invention discloses a clamped storage device and a testing method thereof. The clamped storage device comprises a control unit, a storage unit and a signal processing and measuring unit. The control unit outputs a plurality of signals comprising a mode selection signal and a group of control signals. The storage unit is controlled by the control unit and used for reading a datum at a predetermined address, and the storage unit is provided with a group of output end points. The signal processing and measuring unit is provided with a group of input end points and a group of output end points, wherein the input end points are connected with the group of output end points of the storage unit, and the signal processing and measuring unit reads the datum from the group of input end points and determines whether predetermined processing is performed on the datum according to the mode selection signal. Thereafter, the datum is output through the group of output end points.

Description

Pincers go into the formula memory storage with and method of testing
Technical field
The present invention relates to a kind of pincers and go into the formula memory storage, and be particularly related to a kind of pincers and go into the formula memory storage and have the several data output channel, help testing process.
Background technology
Go at traditional pincers in the design of formula memory storage, the planning of the time that writes and read is difference to some extent all usually.Chief reason is, when memory storage writes data, the driving force of data line (data line) will be much larger than the load of bit line (bit line) and storage mnemon (memory cell) itself, therefore during writing, data can be by data line with the short time, writes direct in the storage mnemon by bit line.Yet during reading, storage unit is behind preliminary filling bit line and data line, the data of then storing mnemon can be sent on bit line and the data line, by the time the current potential on the data line is set up, utilize induction amplifier device (sense amplifier) that faint voltage difference is amplified again, read the value of including of storage mnemon at last from data bus.This reads the suitable redundant and complicated of process, so the time for reading of memory storage usually can be much larger than the write time of memory storage.
Because chip system becomes increasingly complex, the demand of memory span is also increasing.If time for reading can't shorten, then pincers test duration of going into the formula memory storage will occupy the test duration of the chip system overwhelming majority, therefore how to shorten the time for reading of memory storage effectively, to accelerate the flow process of follow-up testing authentication, under the application conditions that memory capacity increases day by day, be the necessity that its existence is arranged really.
Go at traditional pincers on the checking way of formula memory storage, normally utilize the data bus of a word group (word) width size,, whether read and write normally to determine whole memory storage by the contents value that control device comes accessing storage devices.This way mainly must be earlier set after the group address memory storage, by control device readback data from the address that memory storage corresponded to again, man-to-man like this reading of data mode, will certainly increase the time of read storage device, and then cause extra testing cost, especially in the big more system of memory capacity, this way is just more inapplicable.
Therefore the proof machine of going into the formula memory storage with regard to pincers is shaped on and need continuing research and development.
Summary of the invention
The invention provides a kind of pincers and go into the formula memory storage, it allows in checking fruit process the technology of faster measuring to be arranged at least.
The invention provides a kind of pincers and go into the formula memory storage, comprise a control module, a storage unit and a signal Processing and measuring unit.Control module is exported a plurality of signals, comprises a mode select signal and one group of control signal.The controlled unit of storage unit is controlled, and to read data in predetermined address, this storage unit has one group of exit point.Signal Processing and measuring unit have one group of input endpoint and one group of exit point, wherein the input endpoint is connected with this group exit point of storage unit, this signal Processing and measuring unit read this data from this group input endpoint, and according to this mode select signal, whether decision carries out a predetermined process to these data.Thereafter, these data are exported by this group exit point.
The invention provides a kind of method of testing of memory storage, the pincers that is used in is as described gone into the formula memory storage, comprises a test data is written to this storage unit by this control module.Again, start-up mode selects signal that this test data is directly exported by this group exit point, is sent to an output port through this signal Processing and measuring unit.
The present invention proposes a kind of method of testing of memory storage, being used in a pincers goes in the formula memory storage, wherein pincers is gone into the formula memory storage and is comprised a storage unit, has a plurality of exit points and a signal processing unit, wherein under a normal manipulation mode, after the data of this storage unit output of this signal processing unit processes, export by an output port.Method of testing comprises: write a test data to this storage unit; And an outgoing route that passes through this signal processing unit, directly test data is exported by this output port without signal Processing.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates according to one embodiment of the invention, and pincers is gone into system's frame synoptic diagram of formula memory storage.
Fig. 2 illustrates according to one embodiment of the invention, the circuit diagram of signal Processing and measurement mechanism.
Fig. 3 illustrates according to another embodiment of the present invention, and pincers is gone into system's frame synoptic diagram of formula memory storage.
Fig. 4 illustrates according to another embodiment of the present invention, the electrical block diagram of signal Processing and measurement mechanism.
[main element symbol description]
100,150: pincers is gone into the formula memory storage
102,152: memory storage
104,154: signal Processing and measurement mechanism
106,156: output unit
108,158: control device
200: multiplexer
202: signal processing apparatus
204: the position selecting arrangement
210: direct outgoing route
Embodiment
The present invention goes in the design of formula memory storage at pincers, utilizes the existing a large amount of I/O port of chip system, as the retaking of a year or grade path of memory storage, with the effect that realizes measuring fast.Below the present invention is described, but the present invention is not limited only to illustrated embodiment for some embodiment.Can do suitable mutually combining between the illustrated embodiment again.
Along with technology is more and more progressive, the transistor size that unit area can be put is increasing always, and attainable circuit is also complicated day by day, and therefore more and more circuit are wrapped in the chip to be designed, and the requirement of storage space is also increasing.Based on above-mentioned reason, the design that pincers is gone into formula storage system (embeddedmemory) replaces the design of simple function chip (stand alone) gradually, becomes the main flow of design backward.
Fig. 1 illustrates according to one embodiment of the invention, and pincers is gone into the system architecture synoptic diagram of formula memory storage.Consult Fig. 1, pincers is gone into the system architecture of formula memory storage 100, with regard to general utility functions, has for example comprised control device 108, memory storage 102, signal Processing and measurement mechanism 104 and output unit 106.Pincers is gone into formula memory storage 100 under normal data access operation pattern, can come memory storage 102 is carried out access by control device 108.When extraneous desire write data to memory storage 102, control device 108 can be obtained desire writing position and data from data bus according to the input of control signal, reaches the action that memory storage 102 writes again.When extraneous desire during to the memory storage reading of data, control device can be obtained the position of desiring to read and deliver to memory storage 102 via data bus according to the input of control signal, the data of memory storage 102 is read at last again.
Pincers is gone into formula memory storage 100 and is one and has the chip system that pincers is gone into memory storage, and it singly just can not provide the space of data storage, and prior still the needs can handle data.When if signal processing apparatus begins to carry out computing to the data in the memory storage, control device 108 can be read previously stored data from memory storage 102, handle by signal Processing and measurement mechanism 104 again, after signal Processing and measurement mechanism 104 execution, the information of being handled can be delivered to output unit 106 and carry out the adjustment of signal level and intensity, deliver to the output of I/O port at last again and link with extraneous.
Before more detailed description technology of the present invention, describe earlier general traditional pincers and go into the formula storage system, when the design stores device the Several Factors that must consider.Because the restriction of chip area and encapsulation, the number of I/O port can not be too many usually.Based on the considering of the data readback time in the testing process, the width of data bus that control device provides need be enough wide in addition, and addressing just can be too not frequent with the number of times that reads.Though increase the width of data bus, can significantly shorten the test duration, but such way, then must increase the number of I/O port, relatively packaging cost and chip area also can become big, therefore in the design of conventional memory device, the width size of determination data bus must be considered test duration and chip area factor simultaneously.
Memory storage 102 differed widely usually in the time that writes and read, and time for reading is normally greater than write time of memory storage 102.Yet go at pincers in the design of formula storage system, because the evolution of technology, the clock of system is more and more faster, and the related data volume that needs to handle also heightens.When the demand of storage device capacity increasing, and the number of I/O port is also more and more, in order to increase the tested performance of chip system, if the test-schedule of memory storage is still considered to verify by control device 108 sense datas, must be increased the test duration and the cost of entire chip system.
The present invention is directed to pincers and go into memory storage in the formula storage system, propose the design mechanism that can shorten the test duration.Yet the present invention also is not limited only to the use of verification msg.The present invention will originally read the path of memory storage data by control device, change by other I/O ports of chip system and export, and the I/O port that utilizes general chip system is usually far more than the characteristic of memory storage data-bus width.With preferable situation one, each position in memory storage all has its corresponding I/O port can supply output, and memory storage reads the total data time under this arranges, and meeting is identical with the time that conventional memory device reads a position.Thus, the test duration of memory storage can significantly shorten.
The present invention for example does different designs in signal Processing with measurement mechanism 104, also can pass through identical I/O port, DA[1 to reach verification msg] ... DA[YZ] output, and needn't be from control device 108 outputs.The data of memory storage 102 for example can be come the address of representative data position with the marking mode of X, Y, Z.And present embodiment, the quantity of the exit point of memory storage 102 for example is DI[1], DI[2] ..., DI[YZ], put 104 input as signal processing device with measuring.
Control device 108 is done the general data access by 108 pairs of memory storages 102 of control device to allow the outside except having data bus and control bus, signal Processing and measurement mechanism 104 are accepted the retaking of a year or grade mode control signal that control device 108 produces, and just mode select signal comes signal Processing and measurement mechanism 104 operator schemes.Control device 108 produces the control signal operation of control store device 102, signal Processing and measurement mechanism 104 and output unit 106 respectively, and signal Processing and measurement mechanism 104 are more also controlled by the control signal of reading mode.
Fig. 2 illustrates according to one embodiment of the invention, the circuit diagram of signal Processing and measurement mechanism.Consult Fig. 2, signal Processing and measurement mechanism 104 can keep the playback mode that general pincers is gone into the formula storage system, the path that also provides the another one memory storage to read in addition, its signal according to the retaking of a year or grade pattern are selected with normal mode output or the pattern output to measure.
As shown in Figure 2, in signal Processing and measurement mechanism 104, corresponding each input endpoint DI has an output unit, and it comprises a multiplexer 200, a signal processing apparatus 202, and a direct outgoing route 210.Signal Processing is connected respectively with the exit point DI of memory storage 102 with the input endpoint DI of measurement mechanism 104.An input end of multiplexer 200 is connected with input endpoint DI by direct outgoing route 210.Another input end of multiplexer 200 is connected with input endpoint DI via signal processing apparatus 202.Signal processing apparatus 202 can deal with the input data according to need, for example is to convert digital signal to simulating signal.Multiplexer 200 is according to the selection of retaking of a year or grade pattern control, and the signal of an end is wherein exported to output terminal DO.
For example, when the control signal of retaking of a year or grade pattern is low state (Low), this represents a normal mode, the signal after multiplexer 200 can be selected to handle through signal processing apparatus 202, and with this signal output.And the control signal of working as the retaking of a year or grade pattern is set at high state (High), this representation signal is handled with measurement mechanism 104 and is set at a measurement pattern, this moment, the data of memory storage 102 were passed through direct outgoing route 210, by the exit point DO output of signal Processing and measurement mechanism 104.
Return in the operation of integrated circuit of Fig. 2, signal Processing can be connected with the input endpoint of an output unit 106 with the exit point DO of measurement mechanism 104.After output unit 106 receives input signal, can do level and intensity is adjusted to this signal, then deliver to I/O output port DA again.Note that at this output unit 106 is optionally elements, it is used for carrying out signal level and intensity adjustment, when meeting subsequent drive the semaphore request of palpus, among some were used, output unit 106 was not a necessary element.
By the setting of Fig. 1 and Fig. 2, a large amount of I/O output port number just can be utilized to the output terminal to data readback under the verification operation pattern.The complete verification msg of memory storage 102 is read apace.Shared by at this moment I/O output port and normal mode, therefore can not increase the number of extra I/O port.In complicated day by day chip system, the capacity of storer and the constantly increase of I/O port, and the way of this embodiment will be more suitable for the chip system of this type and use.
On the number of the I/O port of considering, the design of Fig. 2 also only is a kind of mode wherein.Under the retaking of a year or grade pattern, based on the verification msg in the memory storage is directly passed through under the notion of I/O port output, had by the verification msg of retaking of a year or grade and can do some arrangements again, utilize the output terminal of I/O port with more much efficient.
Fig. 3 illustrates according to another embodiment of the present invention, and pincers is gone into the system architecture synoptic diagram of formula memory storage.Consult Fig. 3, pincers is gone into formula memory storage 150 in another embodiment that measures fast, has comprised control device 158, memory storage 152, signal Processing and measurement mechanism 154 and output unit 156.Compared to the embodiment of Fig. 1, its difference is that signal Processing and measurement mechanism 154 have increased by one group of position and selected signal.Control device 158 has the position that cooperates the outside to select a signal that signal Processing and measurement mechanism 154 are done control.The position selects the effect of signal as follows.When the number deficiency of I/O port when once exporting all bit data of the permutation in memory storage 102, at this moment output-controlling device can utilize the position to select signal, mode according to time division multiplexing, on same I/O port, under different time, do in good time switching, obtaining the output of different checking bit data, also can collect in the permutation data of all at last.This mode can be made suitable change to signal Processing and measurement mechanism 154.
Fig. 4 illustrates according to another embodiment of the present invention, the electrical block diagram of signal Processing and measurement mechanism.Consult Fig. 4, signal Processing and measurement mechanism 154 comprise input signal DI[1] [Z:1] to input signal DI[Y] [Z:1], wherein Y for example represents number of words, and Z represents figure place.Each exit point DO[1] to DO[Y] in order to export the output signal of a word, Z position being arranged at this word, Z for example is 8, but the Z value is not defined as 8.For each exit point, an output unit is all arranged, comprise a multiplexer 200, selecting arrangement 204, signal processing apparatus 202.Signal input part point DI accepts numeric word data that include the Z position each time by memory storage 152, transmit put in place selecting arrangement 204 and signal processing apparatus 202 respectively, it is connected respectively to two input ends of multiplexer again, by the exit point DO that the signal of two one is exported in the selection of retaking of a year or grade mode signal, its number is to be reduced to Y at present embodiment.
Under normal operation, when the control signal of retaking of a year or grade pattern is low state, signal Processing and measurement mechanism 154 can be planned as normal mode.Input signal is respectively after the data by input endpoint DI input Z position, after signal processing apparatus 202 computings, again with signal by corresponding respectively multiplexer 200, deliver to output signal respectively to exit point DO.At this, because the data of input are the numerical datas of Z position, signal processing apparatus 202 for example can become the digital data conversion of Z position the single simulation signal of simulation.Therefore System on Chip/SoC is under general operation, and the mode of its running is all identical with first embodiment of signal Processing and measurement mechanism.
Again, when for example the retaking of a year or grade mode control signal was high state, signal Processing and measurement mechanism 154 can be planned as measurement pattern.This moment input signal DI[1] [Z:1] to DI[Y] [Z:1], can be respectively through a position selecting arrangement 204, utilize the position select a signal make bit data according to the time with output in regular turn.Control mode for example is to utilize M bar control line, wherein M=log 2Z else delivers to the output terminal of a selecting arrangement 204 with the timesharing in regular turn of different bit data and each.For example, position selecting arrangement 204 can be selected the setting of signal by the position, to determine that input bit data DI[1] [Z:1], can be sent to DO[1] exit point.With a word 8 data instance is arranged, input signal DI[1] [8:1], the position selects a signal timesharing in regular turn to select DI[1] [1], DI[1] [2] ... DI[1] wherein that position of [8] is output to DO[1] position.Through 8 times data readback, can collect a whole complete digital data.
Switching controls by digit selection line, sequence number is that 1 position selecting arrangement 204 to sequence number is that position selecting arrangement 204 timesharing in regular turn of Y is directly passed multiplexer 1 to multiplexer Y with bit data, distinctly signal is directly delivered to output terminal DO[1 again] to DO[Y], need not to do the action of signal Processing.Utilize the mode of time division multiplexing, solve pincers and gone into the problem that formula memory storage I/O port number can't once be exported memory storage permutation bit data, but still can use the advantage of a large amount of I/O port of System on Chip/SoC, quicken the action of the retaking of a year or grade of memory storage, and then reduce the test duration of memory storage.
Then, can do the needed signal Processing of corresponding subsequent operation with the output unit 156 of measurement mechanism 154 back, for example strengthen voltage of signals level etc. in signal Processing.
Be noted that when system be when being in the data readback state of Validation Mode, though the signal of being exported by the I/O port is a simulating signal, its corresponding bit data only has two states.As long as therefore can differentiate two states of bit data, it can be decided by follow-up sensing mechanism, can not influence the function in normal running.In other words, pincers is gone into formula memory storage 150 and not necessarily will be exported by output unit 156, and can be directly by signal Processing and measurement mechanism 154 outputs, to carry out outside data verification.
With regard to the operation mechanism of integral body, pincers is gone into control device, memory storage, signal Processing and the measurement mechanism of formula memory storage and the operation effectiveness of output unit also for example can be following running.
Control signal when control device is used for producing the storage access data, signal Processing and measurement mechanism when the accessing storage devices output data must control timing and the relevant control signal of decision output unit output configuration.
Memory storage is by the signal of control device input, decide desire that access is carried out in that address of memory storage, the action of read-write is mainly decided by the input signal of control device, when desire reads memory storage, then control device can be sent corresponding address and reads to memory storage and with data, when desire write data to memory storage, then control device can be delivered to memory storage with the address and the data of desire input, and data are write corresponding address.
The signal that signal Processing and measurement mechanism can receiving/storing device be read, can decide the operator scheme of circuit by the control signal of retaking of a year or grade pattern, when the retaking of a year or grade pattern is low state, this moment, signal Processing and measurement mechanism operated in normal mode, the data that memory storage is read can be done computing through signal processing apparatus earlier, after handling by multiplexer data are delivered to the input end of output unit again.
When the retaking of a year or grade pattern was high state, this moment, signal Processing and measurement mechanism operated in measurement pattern, and the data that memory storage is read can be directly via the input end of delivering to output unit after the multiplexer again.This way mainly is to utilize the characteristic of I/O output port much larger than the width of data bus, the data that memory storage is read are directly delivered to output unit output, large quantities of data can be once read, under the situation that does not influence the circuit normal running, the test duration of memory storage can be quickened again.
Output unit: its input signal is that the output signal by signal Processing and measurement mechanism is provided, output signal is the I/O output port, strengthen output data by output unit, deliver to the I/O output port at last again, be used for to promote the drives ability by signal Processing and measurement mechanism.
Memory storage in addition must not be defined in the memory storage of particular type.I/O port of the present invention has dual-use function, except reaching the normal running of memory storage, also can be used for the function that other rapid datas are measured.And data are in when checking, and it needn't directly be exported by the I/O port through signal Processing.And the direct mode of output according to the quantity of the exit point of I/O port, also can directly be exported bit data in multiplex's mode according to sequential.Again, the selected of output order can change according to actual design.
The present invention proposes to go at pincers the design of formula Cun Chu Zhuan Catching-rabbits, if be applied in the technical of quick measurement, can change the retaking of a year or grade path of memory storage by signal Processing and measurement mechanism, change by I/O port from original data bus and export much larger than data-bus width.In test, owing to can once read many data, therefore can shorten the test duration, reduce cost.
Again, the present invention utilizes signal Processing and measurement mechanism, changes the retaking of a year or grade path of memory storage, can utilize the I/O port output of System on Chip/SoC fully, and also can not be increased to the number of extra pin.
Again, System on Chip/SoC of the present invention utilizes this mode to do testing authentication fast to memory storage, if verify under the identical test duration, then this way can be carried out more groups test procedure, and therefore the covering scope of test can be comparatively complete.
Though the present invention with embodiment openly as above; right its is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.

Claims (16)

1. a pincers is gone into the formula memory storage, comprising:
One control module is exported a plurality of signals, comprises a mode select signal and one group of control signal;
One storage unit is controlled by this control module, and to read data in predetermined address, this storage unit has one group of exit point; And
One signal Processing and measuring unit, one group of input endpoint and one group of exit point are arranged, wherein this input endpoint is connected with this group exit point of this storage unit, this signal Processing and measuring unit read this data from this group input endpoint, and according to this mode select signal, whether decision carries out a predetermined process to these data, and in by this group exit point these data being exported thereafter.
2. pincers as claimed in claim 1 is gone into the formula memory storage, and wherein this signal Processing is identical and corresponding one by one with this quantity of organizing input endpoint and this group exit point of measuring unit.
3. pincers as claimed in claim 2 is gone into the formula memory storage, and wherein this signal Processing and measuring unit comprise:
A plurality of signal processing apparatus, each this signal processing apparatus is used from this exit point and is received this data organizing each exit point of exit point, and these data are carried out this predetermined process;
A plurality of multiplexers, each this multiplexer is to organizing each exit point of exit point, and wherein each this multiplexer comprises:
One first input end is used for directly receiving the data by this storage unit input; And
One second input end is coupled to a signal processing apparatus of these a plurality of signal processing apparatus, to receive these data through this predetermined process;
Wherein this multiplexer is controlled by this mode select signal, to export these data of this first input end or this second input end.
4. pincers as claimed in claim 3 is gone into the formula memory storage, and when wherein this mode select signal started, these a plurality of multiplexers were exported the data of this first input end, otherwise the data of this second input end are exported.
5. pincers as claimed in claim 1 is gone into the formula memory storage, and wherein this group input endpoint of this signal Processing and measuring unit is that each fixed qty is for once organizing exit point, to organizing an output of exit point.
6. pincers as claimed in claim 4 is gone into the formula memory storage, and wherein this signal Processing and measuring unit comprise:
A plurality of output units, each this output unit is to organizing each setting of exit point, and wherein each this output unit comprises:
One multiplexer has a first input end and one second input end, and an output terminal, and wherein this output terminal constitutes this group exit point, and this multiplexer is selected by this first input end or the output of this second input end by this mode select signal;
A selected cell, one output terminal and group's input end are arranged, wherein this output terminal is connected to this first input end of this multiplexer, this group's input end is connected to this group exit point of this storage unit correspondence, select signal for one that produces by this control module, the data of this group's input end are outputed to this output terminal in regular turn; And
One signal processing unit has an output terminal and group's input end, and wherein this group exit point that this group's input end is corresponding with this storage unit connects, and conversion process becomes the single simulation signal by this output terminal output.
7. pincers as claimed in claim 6 is gone into the formula memory storage, and wherein the quantity of this group's input end is a bit quantity that digital data comprised.
8. pincers as claimed in claim 6 is gone into the formula memory storage, and when wherein this mode select signal started, these a plurality of multiplexers were exported the data of this first input end, otherwise the data of this second input end are exported.
9. pincers as claimed in claim 1 is gone into the formula memory storage, and wherein this storage unit also comprises one group of data-signal end points, is connected with this control module, directly this storage unit is write and reading of data by this control module.
10. pincers as claimed in claim 1 is gone into the formula memory storage, also comprises an output unit, is connected with this group exit point of measuring unit with this signal Processing, and one of them that is subjected to this group control signal controlled, and exports behind signal enhancement.
11. pincers as claimed in claim 1 is gone into the formula memory storage, wherein this control module is accepted a retaking of a year or grade mode control signal and is controlled, to start this mode select signal.
12. pincers as claimed in claim 1 is gone into the formula memory storage, wherein this mode select signal starts down in a test pattern, to control this signal Processing and measuring unit.
13. the method for testing of a memory storage is used in pincers as claimed in claim 1 and goes into the formula memory storage, comprising:
One test data is written to this storage unit by this control module;
Start this mode select signal, this test data is directly exported by this group exit point, be sent to an output port through this signal Processing and measuring unit.
14. the method for testing of memory storage as claimed in claim 13, also comprise induction by the signal of this test data of this signal Processing and measuring unit output with the decision bit content.
15. the method for testing of a memory storage, being used in a pincers goes in the formula memory storage, wherein this pincers is gone into the formula memory storage and is comprised a storage unit, have a plurality of exit points, and a signal processing unit, wherein under a normal manipulation mode, after the data of this storage unit output of this signal processing unit processes, by output port output, this method of testing comprises:
Write a test data to this storage unit; And
By an outgoing route of this signal processing unit, directly test data is exported by this output port without signal Processing.
16. the method for testing of memory storage as claimed in claim 15, also comprise induction by the signal of this test data of this signal processing unit output with the decision bit content.
CN201010167944XA 2010-04-22 2010-04-22 Clamped storage device and testing method thereof Pending CN102237145A (en)

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CN108447522A (en) * 2018-03-28 2018-08-24 睿力集成电路有限公司 The test method of memory device

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Application publication date: 20111109