CN102246275B - Methods of forming multi-doped junctions on a substrate - Google Patents

Methods of forming multi-doped junctions on a substrate Download PDF

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CN102246275B
CN102246275B CN200880132247.1A CN200880132247A CN102246275B CN 102246275 B CN102246275 B CN 102246275B CN 200880132247 A CN200880132247 A CN 200880132247A CN 102246275 B CN102246275 B CN 102246275B
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substrate
diffusion
temperature
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dopant
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CN102246275A (en
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苏尼尔·沙阿
马尔科姆·阿博特
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Innovalight Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first surface region and a second surface region. The method also includes depositing a first set of nanoparticles on the first surface region, the first set of nanoparticles including a first dopant. The method further includes heating the substrate in an inert ambient to a first temperature and for a first time period creating a first densified film, and further creating a first diffused region with a first diffusion depth in the substrate beneath the first surface region. The method also includes exposing the substrate to a diffusion gas including phosphorous at a second temperature and for a second time period creating a PSG layer on the first substrate surface and further creating a second diffused region with a second diffusion depth in the substrate beneath the second surface region, wherein the first diffused region is proximate to the second diffused region. The method further includes exposing the substrate to a oxidizing gas at a third temperature and for a third time period, wherein a SiO2 layer is formed between the PSG layer and the substrate surface, wherein the first diffusion depth is substantially greater than the second diffusion depth.

Description

On substrate, form the method for many doped junctions
Technical field
This disclosure relates generally to p-n junction, and relates to particularly the method for form many doped junctions on substrate.
Background technology
Semiconductor has formed the basis that hyundai electronics is learned.Owing to having the physical characteristic that can optionally change and control between conduction and insulation, semiconductor for example, is necessary in most of modern electrical equipments (, computer, portable phone, photovoltaic cell etc.).
One of the most useful semiconductor structure is p-n junction.As the essential structure piece of many electronic devices and electric equipment, p-n junction trends towards in one direction conduction current and block electric current in another direction, and trends towards producing electric field.This last characteristic is useful for the application (as solar cell) of drawing electric charge.
In typical solar cell, absorbed light generally will produce electron-hole pair.Afterwards, electronics in electric field (or Built-in potential) in p-n junction p-type side can attracted to N-shaped region (conventionally doped with phosphorus) and repel mutually with p-type region (conventionally doped with boron), and the hole in p-n junction N-shaped side can attracted to p-type region and repel mutually with N-shaped region in electric field.Conventionally, N-shaped region and/or p-type region can comprise respectively the relative doping content of varying level separately, are usually expressed as n-, n+, n++, p-, p+, p++ etc.Built-in potential depends on two doped level between adjacent layer conventionally, and therefore electric field strength depends on two doped level between adjacent layer conventionally.
Most of solar cells are generally formed on the silicon wafer doped with the first dopant (normally boron), this first dopant forms absorbent body area, the second counter-doping agent (normally phosphorus) thus in this absorbent body area diffusion form emitter region, to complete p-n junction.After adding passivation and antireflecting coating, can add metal contact element (finger on emitter and busbar, and at the liner (pad) at the absorber back side) to draw produced electric charge.Particularly, emitter dopants concentration must for carrier collection and with the contacting both and be optimized of metal electrode.
Generally speaking, the low concentration of the dopant atom in emitter region by cause the two low again in conjunction with (therefore solar battery efficiency is higher) and with the electrically contacting of the difference of metal electrode.On the contrary, the high concentration of dopant atom will cause the two high combination again (reducing the efficiency of solar cell) and the low resistance ohmic contact with metal electrode.Conventionally, in order to reduce manufacturing cost, generally with single dopant, spread to form emitter, the concentration of dopant is selected as the compromise between combination again and ohmic contact.Therefore, the potential efficiency of solar cell (being converted into the percentage of electric sunlight) has been lowered.
A solution is to use binary doped or emitter optionally.Selective emitter is used for low again the first lightly doped region that combination is optimized and for low resistance ohmic metal, contacts the second heavily doped region (having same dopant type) being optimized.But the structure of selective emitter may be difficult to complete in a step diffusion process, and may relate to multiple masking steps, has therefore increased manufacturing cost.In addition, owing to generally there is no visual border between highly doped emitter region and low-doped emitter region, so metal contact element is snapped on the highly doped region of previous deposition, may be difficult.
As emitter region, the deposition of BSF (back surface field) also may have problems.BSF is generally the region that is positioned at rear surface of solar cell, and it tends to make the minority carrier in absorbent body area to repel mutually with the back of the body surface of wafer and the high recombination region territory at metallized area place.Conventionally can be with forming BSF with the dopant of those same types used in absorbent body area, in this case, the concentration of the dopant atom in this BSF is chosen as to the concentration higher than the absorbent body area that is used for adulterating, therefore between wafer body and back of the body surface, produces potential barrier.
In addition, in typical solar battery structure, BSF forms with aluminium (or material of other depositions), generally first be screen-printed on the back side of solar cell, and in through furnace, carried out common backed together with front metal contact (conventionally being formed by the silver-colored paste of silk screen printing) afterwards.Typically, the silicon atom in wafer tends in aluminium diffusion and recrystallization subsequently, thereby aluminium atom is attached in silicon crystal.But although manufacture relatively easily, the thermal coefficient of expansion (about 24 μ m/m ℃) of aluminium is much higher than silicon (about 3 μ m/m ℃).Therefore, be tending towards occurring wafer bending.Although with the Al BSF of silk screen printing realized charge carrier again in conjunction with aspect certain reduce, but still have overleaf significantly again in conjunction with occurring, this tends to reduce the efficiency of solar cell.
Alternatively, can by with absorbent body area in the diffusion of dopant atom (counter-doping agent) of those opposite types of using by back of the body surface passivation.In this case, in the rear side of substrate, set up floating junction, verified this also provides effective passivation.Generally must to the absorbent body area of solar cell, provide ohmic contact with the second diffusion zone.
Finally, likely use local heavily doped region only on the surperficial zonule of the back of the body, to form ohmic contact, and use surface passivation layer (for example SiN in other regions x, TiO 2, SiO 2) reduce combination again.In this case, these superficial layers have not only reduced the binding site again at silicon face place, and the fixed charge that minority carrier and surface are repelled mutually is also provided.Be similar to the formation of high efficiency emitter (for example selective emitter), effectively the formation of BSF is usually directed to many treatment steps and therefore for the common high cost of manufacture.
In view of the foregoing, provide a kind of optimization method that forms many doped junctions on substrate to make us wishing.
Summary of the invention
The present invention relates to the method that forms many doped junctions on substrate in one embodiment.The substrate providing doped with boron is provided the method, and this substrate comprises the first substrate surface, and this first substrate surface has first surface region and second surface region.Described method also comprises that by first group of nanoparticle deposition, on described first surface region, this first group of nano particle comprises the first dopant.Described method is further included under inert environments described substrate heating to the first temperature and lasting very first time section, thereby produce the first dense film, and further produce the first diffusion zone, in the substrate of this first diffusion zone under described first surface region, there is the first diffusion depth.Described method is also included in and at the second temperature, described substrate is exposed in the diffusion gas that comprises phosphorus and continued for the second time period, thereby produce PSG layer on described the first substrate surface, and further produce the second diffusion zone, in the substrate of this second diffusion zone under described second surface region, have the second diffusion depth, wherein said the first diffusion zone is adjacent with described the second diffusion zone.Described method is further included in and at the 3rd temperature, described substrate is exposed in oxidizing gas and continued for the 3rd time period, wherein between described PSG layer and described substrate surface, forms SiO 2layer, wherein said the first diffusion depth is fully greater than described the second diffusion depth.
Accompanying drawing explanation
In the figure of accompanying drawing, by way of example but not explained the present invention in the mode of restriction, same in the drawings reference number refers to similar key element, and wherein:
Figure 1A to Fig. 1 F shows according to one of a kind of optimization method of the present invention group of reduced graph, and the method is used for using diffusing step simultaneously on substrate, to form many doped junctions;
Fig. 2 A to Fig. 2 G shows according to one of a kind of optimization method of the present invention group of reduced graph, and the method is used for diffusing step at the same time and forms the selective emitter with nano particle BSF;
Fig. 3 A to Fig. 3 G shows according to one of a kind of optimization method of the present invention group of reduced graph, and the method forms the selective emitter on the back of the body surface with backplate contact that area reduces and passivation for diffusing step at the same time;
Fig. 4 shows according to the reduced graph of the solar cell with selective emitter and aluminium BSF of the present invention;
Fig. 5 shows according to the reduced graph of the solar cell with selective emitter and dense film back side contact of the present invention;
Fig. 6 shows the reduced graph reflectivity of the crystalline silicon on the reflectivity of fine and close nanometer particle film and silicon chip being compared according to of the present invention;
Fig. 7 A to Fig. 7 C shows according to the reduced graph of the different electric characteristics of the zones of different of selective emitter of the present invention; And
Fig. 8 shows according to the reduced graph of one group of I-V curve that the solar cell only with light dope emitter and the solar cell with selective emitter are compared of the present invention.
Embodiment
Referring now to preferred implementations more of the present invention as shown in the drawing, describe the present invention in detail.In the following description, many details have been listed to provide thorough understanding of the present invention.But what it should be apparent to those skilled in the art that is to implement the present invention without some or all in these details.In other cases, in order not cause unnecessary coverage to the present invention, well-known treatment step and/or structure are not described in detail.
As discussed previously, on substrate, form many doped junctions (as for solar cell) and often have problems, because conventionally require diffusion process and multiple patterning step of multiple separation, thereby increased manufacturing cost.
In a kind of favourable mode, IV family nano particle that can the doping by being combined as high-concentration dopant agent layer and dopant diffuse source with while diffusing step forms many doped junctions on substrate.The in the situation that of selective emitter, the first diffusion zone and the second diffusion zone are identical dopant type (both for N-shaped or be all p-type), and the in the situation that of BSF, diffusion zone can form by arbitrary dopant type (N-shaped and/or p-type).Selective emitter and BSF also form in diffusing step at the same time.
Generally speaking, nano particle is a kind of microscopic particles that is at least less than 100nm on one dimension.Term " IV family nano particle " typically refers to the IV family nano particle of the hydrogen end-blocking with the average diameter between about 1nm to 100nm, and comprises silicon, germanium, carbon or their combination.Term " IV family nano particle " also comprises the IV family nano particle being doped.Such as, compared with tending to the massive material (> 100nm) of the constant physical property (fusion temperature, boiling temperature, density, conductivity etc.) with irrelevant its size.
Because their size is little, nano particle also tends to be difficult to operation.Therefore,, in a kind of favourable mode, the nano particle of assembling can be suspended in for example, among colloidal dispersion or colloid (ink), to transport and preserve described nano particle.Usually, the colloidal dispersion of IV family nano particle is possible, because the interactional intensity of this particle surface and solvent is enough to overcome density contrast, density contrast can cause material in liquid, sink or float conventionally.That is the nano particle that, less nano particle is larger more easily disperses.
Generally speaking, IV family nano particle is transferred among colloidal dispersion under vacuum or under the environment of the basic anaerobic of inertia.The method and apparatus (as sonication method, high-shear mixer and high pressure/high shear homogenizer) that in addition, can use particle to disperse is helped the dispersion of nano particle in selected solvent or solvent mixture.
The example of solvent comprises alcohols, aldehydes, ketone, carboxylic acids, ester class, amine, organosiloxane class, halogenated hydrocarbon and other varsols.In addition, these solvents can mix, to optimize the physical characteristic such as viscosity, density, polarity etc.
In addition, for better by IV family nanoparticulate dispersed in colloidal dispersion, can form nano particle END CAPPED GROUP group as alcohols, aldehydes, ketone, carboxylic acids, ester class, amine and organosiloxane class by being added with organic compounds.Alternatively, can among gas being joined to plasma chamber, carry out on-the-spot interpolation end-capping group.These end-capping groups can preheat middle removal subsequently in the process of sintering process or at proper lower temperature before sintering process.
For example, the large volume end-capping reagent that is suitable for using in the preparation of the IV of end-blocking family semiconductor nanoparticle comprises C4-C8 side chain alcohols, ring-type alcohols, aldehydes and ketone, as the tert-butyl alcohol, isobutanol, cyclohexanol, methyl cyclohexanol, hutanal, isobutylaldehyde, cyclohexanone, also include organic siloxane class, as methoxyl group (three (TMS) silane) (MTTMSS), three (TMS) silane (TTMSS), decamethyltetrasiloxane (DMTS) and trimethyl methoxy silane (TMOS).
Once prepare, colloidal dispersion can be applied on substrate and through heat-treated, to IV family nano particle is sintered to fine and close conducting film and dopant is diffused among wafer.The example of painting method includes but not limited to: roller coat covers, the coating of slit die formula, intaglio printing, flexographic plate roll printing and ink jet printing method etc.
In addition, the different structure of the IV family nano particle colloidal dispersion of doping can mix to prepare by the selectivity of the IV family nano particle of doping, unadulterated and/or different doping.For example, can prepare the different formulations of the IV family nano particle colloidal dispersion of mixing, wherein the dopant level of certain layer of knot be by by doping mix to prepare with unadulterated IV family nano particle, to reach the requirement of this layer.Alternatively, the IV family nano particle colloidal dispersion of described mixing can be used for compensates for substrate defect, as the passivation of oxygen atom, to reduce undesirable energy state.
Referring now to Figure 1A to Fig. 1 F,, one group of reduced graph has illustrated the method according to a kind of optimization of the present invention, the method is used for using diffusing step simultaneously on substrate, to form many doped junctions, as having on the solar cell of selective emitter (using identical dopant type) or BSF (using different dopant type).
In Figure 1A, use such as roller coat cover, the painting method of the coating of slit die formula, intaglio printing, flexographic plate roll printing, ink jet printing method etc. is deposited on the nano particle 100 of one group of doping on the surface of silicon chip 102 of doping.Doping nanoparticle deposition after, for remove residual solvent can stoving temperature (preferably from 100 ℃ to 500 ℃, more preferably about 350 ℃ and about 450 ℃ and most preferably about 400 ℃) cure described silicon chip.This cure can be under air ambient or under inert environments (as with nitrogen, argon gas or forming gas) carry out.
In Figure 1B, the silicon chip 102 of doping is such as positioned in, in sintering furnace (quartz tube furnace, through furnace etc.).Optionally, can with extra heating process before spreading by particle presintering, to improve the formation of the ohmic contact of low combination again.For example, can by the nano particle 100 of this group doping sintering temperature (preferably between about 500 ℃ and about 1000 ℃, more preferably between about 750 ℃ and 850 ℃ and most preferably about 800 ℃) lower sintering and lasting sintering time (and preferably between about 5 seconds and about 2 minutes, more preferably between about 5 seconds and about 20 seconds and most preferably under inert environments (as nitrogen, argon gas etc.) about 15 seconds) so that formation dense film.In addition, when this dense film forms, the dopant atom in the nano particle 100 of this group doping also may start to spread in the silicon chip 102 of doping, thereby forms first initial doping (higher concentration of dopant) region 112a.
In addition, the in the situation that of solar cell, BSF can be put on to the back of the body surface of the silicon chip of doping, to the minority carrier in absorbent body area is repelled mutually with the high recombination region territory at wafer back surface and metallized area place.Can form BSF with Aluminum Paste (or material of other depositions), be generally first screen-printed on the back side of solar cell, and in through furnace, carry out common backed afterwards together with front metal contact.
In Fig. 1 C, start diffusing step simultaneously.The silicon chip 102 of doping is loaded onto in diffusion furnace and is heated to diffusion temperature (preferably continuing to continue to continue about 15 minutes at about 800 ℃ between about 10 minutes and about 20 minutes and most preferably between about 750 ℃ and about 850 ℃ between about 5 minutes and about 30 minutes and more preferably between about 700 ℃ and about 1000 ℃).
During this period of time, make nitrogen flow through and be filled with low concentration liquid POCl as carrier gas 3(phosphorous oxychloride), O 2gas and N 2the bubbler of gas is so that formation processing gas 101.
In Fig. 1 D, in the thermal process of Fig. 1 C, O 2molecule and POCl 3molecule reacts and forms and comprise P on the silicon chip 102 of doping 2o 5pSG (phosphosilicate glass) layer 106 of (phosphorous oxides).The Cl producing as accessory substance 2metal impurities in the silicon chip 102 of gas and doping react and are removed.Along with the continuation of this chemical process, phosphorus diffuses in silicon wafer and formation second doping (lower doping content) region 104.
In Fig. 1 E, use O 2and N 2form the second oxidizing gas 109.First furnace chamber is heated to oxidizing temperature (preferably between about 800 ℃ and about 1100 ℃, more preferably between about 950 ℃ and about 1050 ℃ and most preferably about 1000 ℃).Because the silicon atom in silicon chip 102 surfaces of oxygen and doping reacts, formed SiO afterwards 2(silicon dioxide) layer 107 (approximately 10-50nm) is (at N 2: O 2under the mixture of about 1: 1).
Once reach enough SiO 2thickness, for example, after 15 to 30 minutes, stop O 2gas flow.Afterwards at N 2under environment, quartz chamber is heated between about 900 ℃ and 1100 ℃, to order about the dopant atom in the nano particle 100 of this group doping originally, enter the more depths of the silicon chip 102 of doping, thereby form first final doping (higher doping content) region 112b.That is to say, and by SiO 2layer in 107 entry deterrence silicon chip 102, the dopant atom difference in PSG layer 106, the dopant atom in the nano particle 100 of this group doping can continue to diffuse in the first doped region 112b.Therefore, the diffusion depth of the first final doped region 112b can fully be greater than the diffusion depth of the second doped region 104 correspondences, thereby makes to be penetrated into by front metal contact (as shown in Figure 4) minimizing possibility of the shunting causing in the substrate of slight counter-doping.
In Fig. 1 F, if needed, can PSG layer 206 be removed with batch formula HF wet-cleaned platform (wet bench) or other applicable devices.
Referring now to Fig. 2 A to Fig. 2 G,, one group of reduced graph has illustrated the method according to a kind of optimization of the present invention, and the method is used for diffusing step at the same time and forms the selective emitter with nano particle BSF.
In Fig. 2 A, use such as roller coat cover, the painting method of the coating of slit die formula, intaglio printing, flexographic plate roll printing, ink jet printing method etc. is deposited on highly doped N-shaped nano-particle layer 200 on the front surface of silicon chip 202 of p doping.Deposition after, for remove residual solvent can the first stoving temperature (preferably from 100 ℃ to 500 ℃, more preferably about 350 ℃ and about 450 ℃ and most preferably about 400 ℃) cure described silicon chip.Curing can be under air ambient or under inert environments, and (as with nitrogen, argon gas or forming gas) carries out.
In Fig. 2 B, same use such as on the back of the body surface of the silicon chip 202 that roller coat covers, the painting method of the coating of slit die formula, intaglio printing, flexographic plate roll printing, ink jet printing method etc. is deposited on highly doped p-type nano-particle layer 220 p doping subsequently to form BSF (and to forming ohmic contact with back metal contacts part (backplate grid)).
Afterwards, for remove residual solvent in highly doped p-type nano-particle layer 220 the second stoving temperature (preferably from 100 ℃ to 500 ℃, more preferably about 350 ℃ and about 450 ℃ and most preferably about 400 ℃) cure the silicon chip 202 of p doping.This cure can be under air ambient or under inert environments (as with nitrogen, argon gas or forming gas) carry out.
In Fig. 2 C, start diffusing step simultaneously.The silicon chip 202 of p doping is such as positioned in, in stove (quartz tube furnace, through furnace etc.).Optionally, can with extra heating process before spreading by particle presintering, to improve the formation of the ohmic contact of low combination again.
Therefore, then can by the nano particle 220 of the nano particle 200 of N-shaped doping and p-type doping simultaneously under inert environments with sintering temperature sintering so that each self-forming dense film (preferably between about 500 ℃ and about 1000 ℃, more preferably between about 750 ℃ and 850 ℃ and most preferably about 800 ℃), and for example, at inert environments (N 2, Ar, forming gas) lower lasting sintering time (preferably between about 5 seconds and about 2 minutes, more preferably between about 5 seconds and about 20 seconds and most preferably about 15 seconds).
When dense film separately forms, n dopant atom in the nano particle 200 of this group N-shaped doping starts to diffusion in the silicon chip 202 of p doping to form the area with high mercury 212a of initial n doping, and p dopant atom in the nano particle 220 of this group p-type doping also starts to diffusion in the silicon chip 202 of p doping to form the area with high mercury 222a of initial p doping.
In Fig. 2 D, the silicon chip 202 of p doping is heated to diffusion temperature (preferably continuing between about 5 minutes and about 30 minutes between about 700 ℃ and about 1000 ℃, more preferably continuing to continue about 15 minutes at about 800 ℃ between 10 minutes and 20 minutes and most preferably between about 750 ℃ and about 850 ℃), in during this period of time, make nitrogen flow through and be filled with low concentration liquid POCl as carrier gas 3(phosphorous oxychloride), O 2gas and N 2the bubbler of gas is so that formation processing gas 230.
In Fig. 2 E, along with the continuation in the thermal process shown in Fig. 2 D, O 2molecule and POCl 3molecule reacts to form positive PSG layer 232 and back side PSG layer 234 on the silicon chip 202 in p doping, and the two includes P 2o 5(phosphorous oxides).The Cl producing as accessory substance 2metal impurities in the silicon chip 202 of gas and p doping react and are removed.Along with the continuation of this chemical process, phosphorus diffuses in silicon wafer to form the low concentration region 204 of positive n doping.In addition, at the nano-particle layer 201 of p-type doping, be patterned in the solar battery structure of (not shown), phosphorus spreads in the region of nano-particle layer 201 of p-type doping to conventionally not having in silicon wafer.In addition, the phosphorus of low concentration (N-shaped) spreads in BSF layer 220, and this BSF layer has boron (p-type) concentration of dopant greatly improving.
In Fig. 2 F, use O 2and N 2form the second oxidizing gas 236.By furnace chamber be heated to oxidizing temperature (preferably between about 800 ℃ and about 1100 ℃, more preferably between about 950 ℃ and 1050 ℃ and most preferably about 1000 ℃) continue between about 5 minutes and 30 minutes.
Along with the silicon atom in the silicon chip 302 of oxygen and p doping reacts, at the positive SiO of the interior formation of silicon wafer 202 of p doping 2(silicon dioxide) layer 207 and back side SiO 2(silicon dioxide) layer 240, respectively naturally approximately 10nm to about 50nm.Once reach enough SiO 2thickness, stops O 2gas flow.
Afterwards at N 2under environment, quartz chamber is heated to diffusion temperature between about 900 ℃ and 1100 ℃ and lasting diffusion time of section (preferably between about 5 minutes and about 60 minutes, more preferably continue about 22 minutes between 15 and 30 minutes and most preferably), to order about dopant atom (script is in the nano-particle layer 200 of N-shaped doping and the nano-particle layer 220 of p-type doping), enter the more depths of the silicon chip 202 of p doping, thereby form the area with high mercury 212a of final n doping and the area with high mercury 222b that final p adulterates.As discussed previously, the dopant atom in positive PSG layer 232 is by positive SiO 2layer 207 stops in its silicon chip 202 that further diffuses into p doping, and overleaf the dopant atom in PSG layer 234 by the SiO at the back side 2layer 240 stops in its silicon chip 202 that further diffuses into p doping.Therefore, the diffusion depth of the area with high mercury 212b of final n doping can fully be greater than the diffusion depth of low concentration region 204 correspondences of positive n doping, thereby makes to be penetrated into by front metal contact (not shown) the minimizing possibility of the shunting causing in the substrate of slight counter-doping.
In Fig. 2 G, if needed, can positive PSG layer 232 and back side PSG layer 234 be removed with batch formula HF wet-cleaned platform or other applicable devices.
Referring now to Fig. 3 A to Fig. 3 G,, one group of reduced graph has illustrated the method according to a kind of optimization of the present invention, and the method forms the selective emitter on the back of the body surface with backplate contact that area reduces and passivation for diffusing step at the same time.
In Fig. 3 A, use as roller coat covers, the painting method of the coating of slit die formula, intaglio printing, flexographic plate roll printing, ink jet printing method etc. is deposited on highly doped N-shaped nano-particle layer 300 on the front surface of the silicon chip 302 that p adulterates.Doping nanoparticle deposition after, for remove residual solvent can the first stoving temperature (preferably from about 100 ℃ to about 500 ℃, more preferably about 350 ℃ and about 450 ℃ and most preferably about 400 ℃) cure described silicon chip.
This cure can be under air ambient or under inert environments (as with nitrogen, argon gas or forming gas) carry out.The nano particle 300 of this group N-shaped doping will form the highly doped part of described selective emitter.
In Fig. 3 B, then highly doped p-type nano-particle layer 301 is deposited on the back of the body surface of silicon chip 302 of p doping to form the back side contact that area reduces.After being heavily doped to form ohmic contact, back side contact that described area reduces is general also to be used as roller coat covers, the painting method of the coating of slit die formula, intaglio printing, flexographic plate roll printing, ink jet printing method etc. deposits to mate backplate grid (not shown) (the many wide lines of 120um that for example meet at right angles with the wide busbar line of a pair of 500um and separate with 2mm spacing).Generally must use SiO 2, SiN xor other technologies are by 303 passivation of region, the remaining back side, so that minimize owing to the loss of combination again.
As previously mentioned, after the nano-particle layer 300 of N-shaped doping and nano-particle layer 301 depositions of p-type doping, for remove residual solvent can the second stoving temperature (preferably from about 100 ℃ to about 500 ℃, more preferably about 350 ℃ and about 450 ℃ and most preferably about 400 ℃) cure the silicon chip 302 that p adulterates.This cure can be under air ambient or under inert environments (as with nitrogen, argon gas or forming gas) carry out.
In Fig. 3 C, the silicon chip 302 of p doping is such as positioned in, in stove (quartz tube furnace, through furnace etc.).Optionally, can with extra heating process before spreading by particle presintering, to improve the formation of the ohmic contact of low combination again.
Therefore, the nano particle 301 of the nano particle 300 of N-shaped doping and p-type doping can be carried out to sintering with sintering temperature simultaneously under inert environments afterwards so that each self-forming dense film (preferably between about 500 ℃ and about 1000 ℃, more preferably between about 750 ℃ and 850 ℃ and most preferably about 800 ℃), and for example, at inert environments (N 2, Ar, forming gas) lower lasting sintering time (preferably between about 5 seconds and about 2 minutes, more preferably between about 5 seconds and about 20 seconds and most preferably about 15 seconds).
When dense film separately forms, n dopant atom in the nano particle 300 of this group N-shaped doping starts to diffusion in the silicon chip 302 of p doping to form the area with high mercury 312a of initial n doping, and p dopant atom in the nano particle 301 of this group p-type doping also starts to diffusion in the silicon chip 302 of p doping to form the area with high mercury 313a of initial p doping.
In Fig. 3 D, start diffusing step simultaneously.The silicon chip 302 of p doping is loaded in diffusion furnace and is heated to diffusion temperature (preferably continuing between about 5 minutes and about 30 minutes between about 700 ℃ and about 1000 ℃, more preferably continuing to continue about 15 minutes at about 800 ℃ between 10 minutes and 20 minutes and most preferably between about 750 ℃ and about 850 ℃), in during this period of time, make nitrogen flow through and be filled with low concentration liquid POCl as carrier gas 3(phosphorous oxychloride), O 2gas and N 2the bubbler of gas is so that formation processing gas 330.
In Fig. 3 E, along with the continuation in the thermal process shown in Fig. 3 D, O 2molecule and POCl 3molecule reacts to form positive PSG layer 332 and back side PSG layer 334 on the silicon chip 302 in p doping, and the two includes P 2o 5(phosphorous oxides).The Cl producing as accessory substance 2metal impurities in the silicon chip 302 that gas adulterates with p react and are removed.Along with the continuation of this chemical process, phosphorus diffuses in silicon wafer to form the low concentration region 322 of the low concentration region 304 of positive n doping and the n doping at the back side.As discussed previously, dopant concentration is tended to make again in conjunction with minimizing.
In Fig. 3 F, use O 2and N 2form the second oxidizing gas 336.By furnace chamber be heated to oxidizing temperature (preferably between about 800 ℃ and about 1100 ℃, more preferably between about 950 ℃ and about 1050 ℃ and most preferably about 1000 ℃) continue between about 5 minutes and 30 minutes.
Along with the silicon atom in the silicon chip 302 of oxygen and p doping reacts, at the positive SiO of the interior formation of silicon wafer 302 of p doping 2(silicon dioxide) layer 307 and back side SiO 2(silicon dioxide) layer 340, respectively naturally approximately 10nm to about 50nm.Once reach enough SiO 2thickness, stops O 2gas flow.
Afterwards at N 2under environment, quartz chamber is heated to diffusion temperature between about 900 ℃ and 1100 ℃ and lasting diffusion time of section (preferably between about 5 minutes and about 60 minutes, more preferably continue about 22 minutes between 15 and 30 minutes and most preferably), to order about dopant atom (script is in the nano-particle layer 300 of N-shaped doping and the nano-particle layer 301 of p-type doping), enter the more depths of the silicon chip 302 of p doping, thereby form the area with high mercury 312b of final n doping and the area with high mercury 313b that final p adulterates.As discussed previously, the dopant atom in positive PSG layer 332 is by positive SiO 2layer 307 stops in its silicon chip 302 that further diffuses into p doping, and overleaf the dopant atom in PSG layer 334 by back side SiO 2layer 340 stops in its silicon chip 302 that further diffuses into p doping.
In Fig. 3 G, if needed, can positive PSG layer 332 and back side PSG layer 334 be removed with batch formula HF wet-cleaned platform or other applicable devices.
Referring now to Fig. 4,, reduced graph has illustrated the solar cell that has selective emitter and aluminium BSF according to of the present invention.As discussed previously, n++ (highly doped) nano particle dense film 412 and n++ diffusion zone 414 form and sintering on p-(light dope) silicon chip 410.Afterwards with POCl 3process forms n-diffusion zone 408.On n-diffusion zone 408, form SiO afterwards 2layer 406, to help the front surface passivation of silicon chip 410, and is controlled at POCl 3the diffusion of phosphorus atoms in process.
SiN xlayer 404 is at SiO 2on the front surface of layer 406, form.Picture SiO 2layer 406 is the same, SiN xlayer 404 helps the surface of passivation silicon chip 410, thereby makes wafer body be subject to the minimum contamination of external source and reduce the again combination of minority carrier in the surface of silicon chip 410.In addition SiN, xlayer 404 can be optimized to reduce the reflectivity of solar cell front surface, thereby substantially improves efficiency and therefore improve performance.On silicon chip 410, form afterwards front metal contact 402 and BSF/ back metal contacts part 416.Front metal contact 402 is generally by comprising Ag powder (70wt% is to 80wt%), lead borosilicate glass PbO-B 2o 3-SiO 2the Ag paste of (1wt% is to 10wt%) and organic component (15wt% is to 30wt%) forms.BSF/ back metal contacts part 416 is generally formed by aluminium, and is configured to produce electric field, and the back of the body surface that this electric field repels minority carrier and therefore the makes minority carrier again impact of combination minimizes.In addition, generally Ag liner (not shown) is applied on BSF/ back metal contacts part 416, thereby to assists welding to be interconnected in module.
Referring now to Fig. 5,, reduced graph has illustrated the solar cell that has selective emitter and dense film back side contact according to of the present invention.N++ (highly doped) nano particle dense film 512, n++ diffusion zone 514, p++ nano particle dense film back side contact 520 and p++ nano particle diffusion zone 518 are to form and sintering on p-(light dope) silicon chip 510.Afterwards with POCl 3process forms positive n-diffusion zone 508 and back side n-diffusion zone 526.On n diffusion zone 508, form SiO afterwards 2layer 506.Afterwards at SiO 2on the front surface of layer 506, form SiN x504 layers.With previously described Ag paste, on silicon chip 510, form front metal contact 502 and back metal contacts part 522 afterwards.
Referring now to Fig. 6,, Fig. 6 is the reduced graph reflectivity of compact nanometer particle film and the reflectivity of the crystalline silicon on silicon chip being compared according to the present invention.As mentioned above, these two surfaces are all coated with the nitride layer of thermal growth oxide and PECVD deposition.Wavelength in nanometer is shown on transverse axis 602, and the percentage of reflectivity is shown on the longitudinal axis 604.
As mentioned above, conventionally use SiN xreduce the reflectivity of solar cell and therefore improve its efficiency.For the light of any setted wavelength of directive solar cell, the hyaline layer that the percentage of this reflectivity and light pass (is mainly SiN at this xlayer) thickness and the Absorption Characteristics on surface, below relevant.
In the case of the selective emitter (there is no fine and close nanometer particle film) of the diffusion described in Figure 1A to Fig. 1 F, for light dope emitter region and heavy doping emitter region for the two, SiN xthe thickness of layer is identical, and surface, below is all crystalline silicon (or the crystalline silicon being covered by thermic grow oxide thin layer), is therefore identical.Therefore, visually front metal contact is snapped on highly doped region and may be had problems.But in the present invention, surface, described below is different and is visually therefore different.Although lightly doped emitter region 606 has the optical characteristics (being extinction coefficient and refractive index) of crystalline silicon, compact nanometer particle film 608 has the different optical characteristics slightly similar from the optical characteristics of amorphous silicon.At this, the reflectivity of lightly doped emitter region 606 has minimal reflection point near the wavelength of 600nm, and this produces a kind of outward appearance of blueness, and the reflectivity of compact nanometer particle film 608 does not have obvious minimum value, and this produces a kind of outward appearance of white.Therefore, because this difference in optical characteristics is tended to make each surface and had different colors, and between these colors, there is high contrast, so visually front metal contact is snapped on highly doped region and can more easily be completed.
Referring now to Fig. 7 A to Fig. 7 C,, reduced graph has illustrated the different electric characteristics according to the zones of different of selective emitter of the present invention.At this, on slight boron doped silicon chip, prepare one group of nano particle substrate, to assist, 4 point probes of sheet resistance are measured.On the Part I of this substrate surface, form the nano particle dense film 704 of phosphorus doping, and with PSG 702, form phosphorus diffusion zone on Part II.
In Fig. 7 A, measure sheet resistance 706.Sheet resistance is generally that the one of the resistance of film to having uniform thickness or layer is measured, and records take Ohm/sq as unit.At this, by substrate presintering 20 seconds and spreading at 725 ℃ 19 minutes with phosphorus deposit at 1000 ℃, at 975 ℃, be oxidized 15 minutes subsequently and at 1000 ℃, anneal 30 minutes.As can be seen, the region that comprises nano particle dense film has the sheet resistance between 10Ohm/sq and 20Ohm/sq, and the region with PSG is between 120-200Ohm/sq.
In Fig. 7 B, measure efficiency 708.The efficiency of solar cell is generally when solar cell is connected with circuit, change the percentage of energy of (from the light absorbing to electric energy) and collection.In general, the loss of solar cell can be broken down into reflection loss, thermodynamic efficiency, again in conjunction with loss and resistance electrical loss.
This term be with maximum power point divided by the light irradiance of the input under standard test condition (STC) (with W/m 2meter) and the surface area (m of solar cell 2) ratio calculate.STC assigned temperature is that 25 ℃ and the irradiance with air quality 1.5 (AM 1.5) spectrum are 1000W/m 2.Maximum power is the maximized point of product that makes electric current (I) and voltage (V).Be IxV.
At this, half substrate is printed with nanoparticle inks pattern, afterwards 1000 ℃ of sintering 20 seconds, and second half is not applied in nanoparticle inks.Then described substrate is spread 26 minutes with phosphorus deposit at 750 ℃, at 975 ℃, be oxidized 15 minutes subsequently and at 1000 ℃, anneal 30 minutes.In this case, the phosphorus doping intensity in the region that there is no ink is higher than 100Ohm/sq and to have in the region of ink be lower than 60Ohm/sq.As can be seen, the region that comprises nano particle dense film has the efficiency between about 12% and about 14%, and the region with PSG is between about 2% and about 10%.
In Fig. 7 C, measure fill factor, curve factor (FF) 710.Fill factor, curve factor is that maximum power is divided by open circuit voltage (V oc) and short circuit current (I sc) ratio of product.At this, the substrate of half is printed with the nanoparticle inks of patterning, afterwards 800 ℃ of sintering 20 seconds, and second half does not have ink.Then described substrate is spread 26 minutes with phosphorus deposit at 750 ℃, at 975 ℃, be oxidized 15 minutes subsequently and at 1000 ℃, anneal 30 minutes.In this case, the phosphorus doping intensity in the region that there is no ink is higher than 75Ohm/sq and to have in the region of ink be lower than 50Ohm/sq.In all three kinds of situations, nano silicon particles ink has been assisted the formation of selective doping, wherein in the scope that applies ink, has formed heavily doped region.As can be seen, the region that comprises nano particle dense film has the FF between about 75% and about 80%, and the region with PSG is between about 55% and about 20%.
Referring now to Fig. 8,, reduced graph has illustrated according to the present invention one group of I-V curve that the solar cell only with light dope emitter and the solar cell with selective emitter are compared.In general, along with the load in solar cell changes to approaching open circuit (infinitely great resistance) from approaching short circuit (zero resistance), can draw out I-V curve.
At this, voltage (V) illustrates on transverse axis 802, and electric current (J) illustrates on the longitudinal axis 804.Curve 806 has been described light dope emitter solar battery, and curve 808 has been described heavy doping nano particle dense film selective emitter.Although these two batteries all have front metal contact and back metal contacts part as previously mentioned, light dope emitter solar battery 806 has slight, uniform concentration of dopant on whole silicon chip (comprising the region under front metal contact).In contrast, heavy doping nano particle dense film selective emitter 808 has heavily doped region under front metal contact, and substantially on the remainder of this solar cell, has lightly doped region.Consequently, heavy doping nano particle dense film selective emitter 808 forms better ohm (low-resistivity) with front metal contact and contacts, and this is corresponding to higher net efficiency.This can see by the region 810 on chart, and reflected the net gain of on power (and therefore in efficiency), heavy doping nano particle dense film is achieved this net gain.
Therefore, in favourable mode, selective emitter can be formed together with nano particle dense film, make like this to reach abundant high bulk lifetime and good surperficial recombination current density.
For the object of this disclosure and unless otherwise indicated, " one " or " one " (" a, an ") meaning is " one or more ".All patents, application, list of references and the publication of quoting at this by reference its entirety is incorporated to herein, as them, is incorporated to by reference separately.
With reference to different specific and illustrative execution modes, present invention is described.But, be understood that and can carry out many changes and change but still within the spirit and scope of the present invention.Advantage of the present invention is included as electric equipment (as solar cell) production low cost and high efficiency knot.
The invention discloses illustrative embodiments and best mode, can to disclosed execution mode change and change however still as theme of the present invention defined by the following claims and spirit within.

Claims (31)

1. for form a method for many doped junctions on substrate, described method comprises:
Substrate doped with boron is provided, and described substrate comprises front surface, and described front surface has first surface region and second surface region;
By the first group of nanoparticle deposition that comprises the first dopant on described first surface region;
Under inert environments, described substrate heating is also continued to very first time section to the first temperature, produce thus the first dense film and the first diffusion zone, in the substrate of described the first diffusion zone under described first surface region, there is the first diffusion depth;
Described substrate be exposed in the diffusion gas that comprises phosphorus at the second temperature and continued for the second time period, on the second surface region of described front surface, produce thus PSG layer and the second diffusion zone, in the substrate of described the second diffusion zone under described second surface region, have the second diffusion depth, wherein said the first diffusion zone is adjacent with described the second diffusion zone; And
In described substrate being exposed to oxidizing gas at the 3rd temperature and continue the 3rd time period, between described PSG layer and described front surface, form SiO thus 2layer and with respect to described the second diffusion depth, increase described the first diffusion depth.
2. the method for claim 1, wherein said the first temperature is between 500 ° of C and 1000 ° of C.
3. the method for claim 1, wherein said the first temperature is between 750 ° of C and 850 ° of C.
4. the method for claim 1, wherein said the first temperature is about 800 ° of C.
5. the method for claim 1, wherein said very first time section is between 5 seconds and 2 minutes.
6. the method for claim 1, wherein said very first time section is between 5 seconds and 20 seconds.
7. the method for claim 1, wherein said very first time section is about 15 seconds.
8. the method for claim 1, wherein said diffusion gas comprises POCl 3, O 2and N 2.
9. the method for claim 1, wherein said the second temperature is between 700 ° of C and 1000 ° of C, and described the second time period is between 5 minutes and 30 minutes.
10. the method for claim 1, wherein said the second temperature is between 750 ° of C and 850 ° of C, and described the second time period is between 10 minutes and 20 minutes.
11. the method for claim 1, wherein said the second temperature is about 800 ° of C, and described the second time period is about 15 minutes.
12. the method for claim 1, wherein said the 3rd temperature is between 800 ° of C and 1100 ° of C.
13. the method for claim 1, wherein said the 3rd temperature is between 950 ° of C and 1050 ° of C.
14. the method for claim 1, wherein said the 3rd temperature is about 1000 ° of C.
15. the method for claim 1, wherein said the 3rd time period is between 15 minutes and 30 minutes.
16. the method for claim 1, described method be further included in deposition described first group of nano particle after, by the second group of nanoparticle deposition that comprises the second dopant on the 3rd surf zone on the back of the body surface of described substrate.
17. methods as claimed in claim 16, the step of wherein said heated substrate further produces the second dense film and the 3rd diffusion zone, in the substrate of described the 3rd diffusion zone under described the 3rd surf zone, has the 3rd diffusion depth.
18. methods as claimed in claim 17, wherein said the first dopant is phosphorus, and described the second dopant is boron.
19. the method for claim 1, described method is deposited on the first metal paste on the back of the body surface of described substrate before being further included in described substrate being exposed in described diffusion gas.
20. methods as claimed in claim 19, after wherein in described substrate is exposed to described oxidizing gas, described method further comprises at least one surface passivation is deposited upon on the front surface of described substrate, and the second metal paste is deposited on described at least one surface passivation layer.
21. 1 kinds for forming the method for many doped junctions on substrate, and described method comprises:
Substrate doped with boron is provided, and described substrate comprises front surface, and described front surface has first surface region and second surface region;
By the first group of nanoparticle deposition that comprises the first dopant on described first surface region;
Described substrate be exposed in the diffusion gas that comprises phosphorus at the first temperature and continue very first time section, produce thus the first diffusion zone, the PSG layer on the second surface region of described front surface and the second diffusion zone, in the substrate of described the first diffusion zone under described first surface region, there is the first diffusion depth, and there is the second diffusion depth in the substrate of described the second diffusion zone under described second surface region; And
In described substrate being exposed to oxidizing gas at the second temperature and continue the second time period, between described PSG layer and described front surface, form SiO thus 2layer and with respect to described the second diffusion depth, increase described the first diffusion depth.
22. methods as claimed in claim 21, wherein said diffusion gas comprises POCl 3, O 2and N 2.
23. methods as claimed in claim 21, wherein said the first temperature is between 700 ° of C and 1000 ° of C, and described very first time section is between 5 minutes and 30 minutes.
24. methods as claimed in claim 21, wherein said the first temperature is about 800 ° of C, and described very first time section is about 15 minutes.
25. methods as claimed in claim 21, wherein said the second temperature is between 800 ° of C and 1100 ° of C.
26. methods as claimed in claim 21, wherein said the second temperature is about 1000 ° of C.
27. methods as claimed in claim 21, wherein said the second time period is between 15 minutes and 30 minutes.
28. methods as claimed in claim 21, after described method is further included in the described first group of nano particle of deposition, by the second group of nanoparticle deposition that comprises the second dopant on the 3rd surf zone on the back of the body surface of described substrate, the counter-doping agent that wherein said the second dopant is described the first dopant.
29. methods as claimed in claim 28, wherein said the first dopant is phosphorus, and described the second dopant is boron.
30. methods as claimed in claim 21, described method is deposited on the first metal paste on the back of the body surface of described substrate after being further included in the described first group of nano particle of deposition.
31. methods as claimed in claim 30, after wherein in described substrate is exposed to described oxidizing gas, described method further comprises at least one surface passivation is deposited upon on the front surface of described substrate, and the second metal paste is deposited on described at least one surface passivation layer.
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