CN102315131B - The manufacture method of transistor - Google Patents
The manufacture method of transistor Download PDFInfo
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- CN102315131B CN102315131B CN201110300269.8A CN201110300269A CN102315131B CN 102315131 B CN102315131 B CN 102315131B CN 201110300269 A CN201110300269 A CN 201110300269A CN 102315131 B CN102315131 B CN 102315131B
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Abstract
A manufacture method for transistor, comprising: provide Semiconductor substrate; Form grid structure and the side wall being positioned at described grid structure side successively on the semiconductor substrate; Form the photoresist layer of patterning on the semiconductor substrate; With described photoresist layer, grid structure and side wall for mask, in described Semiconductor substrate, carry out light dope ion implantation, form source/drain extension area; With described photoresist layer, grid structure and side wall for mask, in described source/drain extension area, carry out heavy doping ion injection, form source/drain region.The present invention can simplify step, saves production cost.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of manufacture method of transistor.
Background technology
In the semiconductor device, lightly doped drain (LightlyDopedDrain, LDD) structure is MOS (MetalOxideSemiconductor, metal-oxide semiconductor (MOS)) transistor is to weaken drain region electric field, to overcome a kind of structure that hot current-carrying effect (Hotcarriereffect) is taked, namely in channels a low-doped drain extension region is set near drain electrode, the drain extension region making this low-doped is receiving portion component voltage also, thus prevents hot current-carrying effect.Therefore, generally all LDD structure to be formed in existing MOS transistor manufacture craft.
Be made as example below with Laterally Diffused Metal Oxide Semiconductor (LaterallyDiffusedMetalOxideSemiconductor, LDMOS) transistor, illustrate that prior art comprises the manufacturing process of the transistor of LDD structure.
Shown in figure 1, provide the Semiconductor substrate 10 of P type;
Shown in figure 2, in described Semiconductor substrate 10, form the high-pressure trap area 11 of P type;
Shown in figure 3, in described high-pressure trap area 11, form the body zone 12 of P type and the drift region 13 of N-type, described body zone 12 is connected with described drift region 13, and the degree of depth of described drift region 13 is greater than the degree of depth of described body zone 12;
Shown in figure 4, in described body zone 12 and drift region 13, form fleet plough groove isolation structure 14 respectively, region deviding between two fleet plough groove isolation structures 14 wherein in described drift region 13 drain region;
Shown in figure 5, described Semiconductor substrate 10 forms grid structure, described grid structure comprises gate dielectric layer 15 and grid 16;
Shown in figure 6, described Semiconductor substrate 10 forms the first photoresist 23 of patterning, with described first photoresist 23 and described grid structure for mask carries out light dope ion implantation;
Shown in figure 7, in body zone 12, form extension area, N-type source 17, and form N-type drain extension region 18 in drift region 13, extension area, described source 17 and drain extension region 18 form LDD structure, and remove described first photoresist 23;
Shown in figure 8, formation side wall 19 around described grid structure;
Shown in figure 9, described Semiconductor substrate 10 forms the second photoresist 24 of patterning, with described second photoresist 24, described grid structure and described side wall 19 for mask carries out heavy doping ion injection;
With reference to shown in Figure 10, in extension area, source 17, form the source region 20 of N-type, and form the drain region 21 of N-type in drain extension region 18, and remove described second photoresist 24;
With reference to shown in Figure 11, in described body zone 12, form the body draw-out area 22 of P type.
So far, the N-type ldmos transistor comprising LDD structure is obtained.
Under the prerequisite that drain width is identical, the resistivity of the ldmos transistor relatively comprising LDD structure and the ldmos transistor not comprising LDD structure, with reference to shown in Figure 12, can find: the drain resistance rate comprising the ldmos transistor of LDD structure is smaller, the series resistance namely comprising the ldmos transistor drain electrode of LDD structure is smaller.
But in above-mentioned manufacturing process, in order to obtain source/drain extension area and source/drain region, needing the first photoresist 23 first forming patterning, after source/drain extension area to be formed, removing described first photoresist 23; Then side wall 19 is formed; Form the second photoresist 24 of patterning again, remove described second photoresist 24 after source/drain region to be formed, described first photoresist 23 is substantially identical with described second photoresist 24.Thus making step more complicated, the production cost of ldmos transistor is higher.
Similarly, comprising in the manufacturing process of the metal-oxide-semiconductor of LDD structure at other, in order to obtain source/drain extension area and source/drain region, also needing formation and the removal step of successively carrying out photoresist for twice.
Therefore, how to comprise in the metal-oxide-semiconductor of LDD structure in making, reduce making step, reduce production cost and just become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of manufacture method of transistor, to simplify step, saves production cost.
For solving the problem, the invention provides a kind of manufacture method of transistor, comprising:
Semiconductor substrate is provided;
Form grid structure and the side wall being positioned at described grid structure side successively on the semiconductor substrate;
Form the photoresist layer of patterning on the semiconductor substrate;
With described photoresist layer, grid structure and side wall for mask, in described Semiconductor substrate, carry out light dope ion implantation, form source/drain extension area;
With described photoresist layer, grid structure and side wall for mask, in described source/drain extension area, carry out heavy doping ion injection, form source/drain region.
Alternatively, described transistor is ldmos transistor.
Alternatively, described transistor is CMOS (ComplementaryMetal-Oxide-SemiconductorTransistor, complementary metal oxide semiconductors (CMOS)) transistor.
Alternatively, the source region of described transistor and drain region are unsymmetric structure.
Alternatively, the manufacture method of described transistor also comprises: after forming described source/drain extension area, carry out annealing in process.
Alternatively, the manufacture method of described transistor also comprises: after forming described source/drain region, carries out annealing in process.
Alternatively, described transistor comprises body draw-out area, and described manufacture method also comprises: after the described source/drain region of formation, organizator draw-out area; After the described body draw-out area of formation, carry out annealing in process.
Alternatively, described transistor is N-type, and described light dope ion is phosphonium ion; The energy range of described light dope ion implantation comprises 50keV ~ 100keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
Alternatively, described transistor is N-type, and described light dope ion is arsenic ion; The energy range of described light dope ion implantation comprises 90keV ~ 200keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
Alternatively, described transistor is P type, and described light dope ion is boron ion; The energy range of described light dope ion implantation comprises 12keV ~ 35keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
Alternatively, described transistor is P type, and described light dope ion is indium ion; The energy range of described light dope ion implantation comprises 80keV ~ 300keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
Compared with prior art, the present invention has the following advantages: after formation of the gate structure, first form side wall, then form the photoresist layer of patterning, respectively with described photoresist layer, grid structure and side wall for mask, successively carry out light dope ion implantation and heavy doping ion and inject, form source/drain extension area and source/drain region successively, thus eliminate formation and the removal step of a photoresist layer, simplify the making step of transistor, eventually reduce the production cost of transistor.
Accompanying drawing explanation
Fig. 1 to Figure 11 is the manufacturing process schematic diagram that prior art comprises the transistor of LDD structure;
Figure 12 is the drain resistance rate-drain width schematic diagram of the ldmos transistor comprising LDD structure and do not comprise LDD structure;
Figure 13 is the schematic flow sheet of the manufacture method of embodiment of the present invention transistor;
Figure 14 to Figure 22 is the schematic diagram of the manufacture method of the embodiment of the present invention one ldmos transistor;
Figure 23 to Figure 29 is the schematic diagram of the manufacture method of the embodiment of the present invention two ldmos transistor;
Figure 30 is the schematic diagram of the manufacture method of the embodiment of the present invention three nmos pass transistor.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, prior art comprises in the process of the transistor of LDD structure in making, in order to form source/drain extension area and source/drain region, the photoresist of the patterning needing successively twice formation substantially identical, namely needs to carry out twice substantially identical lithography step.In order to simplify making step and reduce production cost, the invention provides a kind of manufacture method of transistor, first form side wall, then the photoresist layer of patterning is formed, respectively with described photoresist layer for mask, successively carry out light dope ion implantation and heavy doping ion and inject, form source/drain extension area and source/drain region successively, thus eliminate formation and the removal step of a photoresist layer, namely eliminate a lithography step.
With reference to shown in Figure 13, the manufacture method of semiconductor device provided by the invention comprises:
Step S1, provides Semiconductor substrate;
Step S2, forms grid structure and the side wall being positioned at described grid structure side on the semiconductor substrate successively;
Step S3, forms the photoresist layer of patterning on the semiconductor substrate;
Step S4, with described photoresist layer, grid structure and side wall for mask, carries out light dope ion implantation in described Semiconductor substrate, forms source/drain extension area;
Step S5, with described photoresist layer, grid structure and side wall for mask, carries out heavy doping ion injection in described source/drain extension area, forms source/drain region.
Be described in detail below in conjunction with accompanying drawing.
Embodiment one
The present embodiment is to make N-type ldmos transistor, and the manufacture method of ldmos transistor specifically comprises the following steps.
First, with reference to shown in Figure 14, Semiconductor substrate 100 is provided.
The material of described Semiconductor substrate 100 can be silicon, germanium silicon or silicon-on-insulator (Silicon-On-Insulator, SOI) etc.In the present embodiment, the material of described Semiconductor substrate 100 is the silicon substrate of P type doping.
Comprise in described Semiconductor substrate 100:
High-pressure trap area 110;
Be positioned at body zone 120 and the drift region 130 of described high-pressure trap area 110, described body zone 120 is connected with described drift region 130, and the degree of depth of described drift region 130 is greater than the degree of depth of described body zone 120;
Be positioned at multiple fleet plough groove isolation structures 140 of described body zone 120 and described drift region 130.
Wherein, described high-pressure trap area 110, body zone 120, drift region 130 can be formed by the mode of carrying out ion implantation in Semiconductor substrate 100, and described high-pressure trap area 110 and body zone 120 are the doping of P type, and described drift region 130 is N-type doping.
Wherein, the region deviding between two fleet plough groove isolation structures 140 in described drift region 130 is drain region.
Particularly, the Doped ions of described P type doping can be boron ion or indium ion etc.; The Doped ions of described N-type doping can be phosphonium ion or arsenic ion etc.
Then, with reference to shown in Figure 15, described Semiconductor substrate 100 forms grid structure, and described grid structure comprises gate dielectric layer 150 and grid 160.
The formation method of described grid structure is known for those skilled in the art, therefore does not repeat them here.Such as: the material of described gate dielectric layer 150 can be silica, the material of described grid 160 can be polysilicon.
Then, with reference to shown in Figure 16, side wall 170 is formed in the side of described grid structure.
The material of described side wall 170 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine arbitrarily, and its concrete formation process is known for those skilled in the art, therefore does not repeat them here.
Then, with reference to shown in Figure 17, described Semiconductor substrate 100 forms the photoresist layer 180 of patterning.Particularly, the first upper surface coating photoresist of structure shown in Figure 16, then by expose and the photoetching process such as development forms the structure shown in Figure 17.
Wherein, the photoresist layer 180 being positioned at described body zone 120 upper surface defines the region of the body draw-out area of follow-up formation.Described photoresist layer 180, fleet plough groove isolation structure 140, grid structure and side wall 170 define source region and drain region jointly.Preferably, described source region and drain region are not symmetrical centered by grid structure, thus ensure that the source/drain region of follow-up formation is unsymmetric structure, namely drain region is away from grid structure, therefore the existence of side wall 170 can not impact drain extension region, finally can ensure the drain electrode stable performance of semiconductor device.
The photoresist layer 180 that this step is formed is identical with the photoresist layer of the patterning formed when forming source/drain region in prior art, therefore does not repeat them here.
Then, with reference to shown in Figure 18, with described photoresist layer 180, grid structure and side wall 170 for mask, in described body zone 120 and described drift region 130, light dope ion implantation is carried out respectively.
N-type light dope ion implantation is carried out, to form N-type source/drain extension area in the present embodiment.Owing to now having formed side wall 170, and extension area, source needs to be formed in Semiconductor substrate 100 corresponding to side wall 170 lower surface, and therefore part light dope ion needs the side wall 170 through side, to form extension area, source.
In one example in which, phosphonium ion is injected respectively in described body zone 120 and described drift region 130, with the vertical plane on vertical semiconductor devices surface for benchmark, the angle of ion implantation can be greater than 0 degree and be less than or equal to 45 degree, the energy range of ion implantation can be 50keV ~ 100keV, and the dosage range of ion implantation can be 1E13/cm
2~ 1E14/cm
2, thus form the extension area, source 210 shown in Figure 19 and drain extension region 220.
In another example, arsenic ion is injected respectively in described body zone 120 and described drift region 130, with the vertical plane on vertical semiconductor devices surface for benchmark, the angle of ion implantation can be greater than 0 degree and be less than or equal to 45 degree, the energy range of ion implantation can be 90keV ~ 200keV, and the dosage range of ion implantation can be 1E13/cm
2~ 1E14/cm
2, thus form the extension area, source 210 shown in Figure 19 and drain extension region 220.
In addition, after formation source/drain extension area, annealing in process can also be carried out, as: quick sharp cutting edge of a knife or a sword annealing process (RTA), with the Doped ions in activation of source/drain extension region.
Then, with reference to shown in Figure 20, with described photoresist layer 180, grid structure and side wall 170 for mask, in extension area, described source 210 and drain extension region 220, heavy doping ion injection is carried out respectively.
The injection of N-type heavy doping ion is carried out, to form N-type source/drain region in the present embodiment.The method that the present embodiment forms source/drain region is same as the prior art, namely the present invention can not change the parameters such as ion implantation angle, ion implantation energy and ion implantation dosage in heavy doping ion injection process, in extension area, described source 210 and described drain extension region 220, inject phosphonium ion or arsenic ion respectively, thus form the source region 230 shown in Figure 21 and drain region 240.
After formation source/drain region, just can remove described photoresist layer 180.
Wherein, remove described photoresist layer 180 and the method for ashing can be adopted to realize, also can to adopt in prior art other known photoresist minimizing technology, it should not limit the scope of the invention at this.
Then, with reference to shown in Figure 22, organizator draw-out area 250 in described body zone 120.
Particularly, described body draw-out area 250 can by being formed to implanting p-type Doped ions in body zone 120, and it is known for those skilled in the art, therefore does not repeat them here.
After organizator draw-out area 250, annealing in process can also be carried out, to activate the Doped ions in source region 230, drain region 240 and body draw-out area 250.
It should be noted that, in other embodiments of the invention, after formation source/drain extension area, annealing in process can not be carried out, but after organizator draw-out area 250, carry out annealing in process, with while activation of source extension area 210, drain extension region 220, source region 230, Doped ions in drain region 240 and body draw-out area 250.
So far, the ldmos transistor shown in Figure 22 is obtained.
In other embodiments, when forming P type ldmos transistor, described light dope ion can be boron ion, and now, the energy range of ion implantation can comprise 12keV ~ 35keV, and ion implantation dosage scope can comprise 1E13/cm
2~ 1E14/cm
2, the angle of ion implantation can be greater than 0 degree and be less than or equal to 45 degree; Described light dope ion can also be indium ion, and now, the energy range of ion implantation can comprise 80keV ~ 300keV, and ion implantation dosage scope can comprise 1E13/cm
2~ 1E14/cm
2, the angular range of ion implantation can be greater than 0 degree and be less than or equal to 45 degree.
Embodiment two
Present embodiments provide the manufacture method of another kind of ldmos transistor, mainly comprise:
With reference to shown in Figure 23, provide Semiconductor substrate 100, comprise in described Semiconductor substrate 100: body zone 120 and drift region 130, described body zone 120 is connected with described drift region 130, and the degree of depth of described drift region 130 equals the degree of depth of described body zone 120;
With reference to shown in Figure 24, described Semiconductor substrate 100 forms grid structure and is positioned at the side wall 170 around described grid structure, described grid structure comprises successively and is positioned at gate dielectric layer 150 in described Semiconductor substrate 100 and grid 160;
With reference to shown in Figure 25, described Semiconductor substrate 100 forms the photoresist layer 280 of patterning;
With reference to shown in Figure 26, with described photoresist layer 280, grid structure and side wall 170 for mask, in described body zone 120 and described drift region 130, carry out light dope ion implantation respectively, form extension area, source 210 and drain extension region 220;
With reference to shown in Figure 27, with described photoresist layer 280, grid structure and side wall 170 for mask, in extension area, described source 210 and drain extension region 220, carry out heavy doping ion injection respectively, form source region 230 and drain region 240;
With reference to shown in Figure 28, remove described photoresist layer 280;
With reference to shown in Figure 29, organizator draw-out area 250 in described body zone 120.
The present embodiment, after formation extension area, source/drain region or after forming source/drain region or after organizator draw-out area 250, can carry out annealing in process.
The difference of the ldmos transistor that the present embodiment makes and the ldmos transistor that embodiment one makes is: all do not comprise fleet plough groove isolation structure in body zone 120 described in the present embodiment and described drift region 130, therefore, after the photoresist layer 280 forming patterning, region, body draw-out area 250, region, source region 230 and region, drain region 240 is exposed; And described region, source region 230 and region, described drain region 240 asymmetric.
The relevant parameter that in the present embodiment, light dope ion implantation and heavy doping ion are injected can reference example one.
The present embodiment first forms side wall 170, then the photoresist layer 280 of patterning is formed, respectively with described photoresist layer 280, grid structure and side wall 170 for mask, successively carry out light dope ion implantation and heavy doping ion injection, form source/drain extension area and source/drain region successively, thus eliminate formation and the removal step of a photoresist layer, simplify the making step of the ldmos transistor comprising LDD structure, eventually reduce the production cost of transistor.
It should be noted that; the method of the present embodiment can also be adopted to make the ldmos transistor of other structures; it only can form a photoresist layer; just can with photoresist layer, grid structure and side wall for mask; carry out light dope ion implantation and heavy doping ion injection successively; thus form source/drain extension area and source/drain region, therefore should not limit the scope of the invention at this.
Embodiment three
Provide a kind of manufacture method of nmos pass transistor in the present embodiment, as shown in figure 30, described method mainly comprises described nmos pass transistor:
There is provided the Semiconductor substrate 300 of P type, described Semiconductor substrate 300 comprises: P type potential well 310 and multiple fleet plough groove isolation structure 320, region deviding between the described fleet plough groove isolation structure 320 of part drain region;
Described Semiconductor substrate 300 forms grid structure, and described grid structure comprises: gate dielectric layer 330 and grid 340;
Side wall 350 is formed in the relative both sides of described grid structure;
Described Semiconductor substrate 300 forms photoresist layer;
With described photoresist layer, grid structure and side wall 350 for mask, in described Semiconductor substrate 300, carry out light dope ion implantation, form extension area, N-type source 360 and N-type drain extension region;
With described photoresist layer, grid structure and side wall 350 for mask, heavy doping ion injection is carried out in extension area, described N-type source 360 and N-type drain extension region, in extension area, N-type source 360, form N-type source region 380, and form N-type drain region 390 in N-type drain extension region.
The present embodiment, after formation source/drain extension area or after forming source/drain region, can carry out annealing in process.
The present embodiment first forms side wall 350, then the photoresist layer of patterning is formed, respectively with described photoresist layer, grid structure and side wall 350 for mask, successively carry out light dope ion implantation and heavy doping ion injection, form source/drain extension area and source/drain region successively, thus eliminate formation and the removal step of a photoresist layer, simplify the making step of the nmos pass transistor comprising LDD structure, eventually reduce the production cost of transistor.
The relevant parameter that in the present embodiment, light dope ion implantation and heavy doping ion are injected can reference example
It should be noted that, in the above-described embodiments, for the nmos pass transistor of the ldmos transistor of two kinds of concrete structures and a kind of concrete structure, but the present invention is not restricted to this, the inventive method may be used for making other transistors comprising LDD structure, as: PMOS transistor, high pressure (if operating voltage is 5V or 3.3V) CMOS transistor, thus eliminate formation and the removal step of a photoresist layer, finally save the production cost of transistor.Preferably, the source region of described transistor and drain region are unsymmetric structure, namely centered by grid structure, described source region and described drain region asymmetric, and described drain region is away from grid structure, thus can avoid the impact on drain electrode.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a manufacture method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form grid structure and the side wall being positioned at described grid structure side successively on the semiconductor substrate;
Form the photoresist layer of patterning on the semiconductor substrate;
With described photoresist layer, grid structure and side wall for mask, in described Semiconductor substrate, carry out light dope ion implantation, form source/drain extension area;
With described photoresist layer, grid structure and side wall for mask, in described source/drain extension area, carry out heavy doping ion injection, form source/drain region;
Described transistor is ldmos transistor;
Described transistor comprises body draw-out area, and described manufacture method also comprises: after the described source/drain region of formation, organizator draw-out area; After the described body draw-out area of formation, carry out annealing in process;
Wherein, the source region of described transistor and drain region are not symmetrical centered by grid structure, and drain region is away from grid structure, thus make the source region of formation and drain region be unsymmetric structure, avoid the impact on drain extension region.
2. the manufacture method of transistor as claimed in claim 1, is characterized in that, also comprise: after forming described source/drain extension area, carry out annealing in process.
3. the manufacture method of transistor as claimed in claim 1, is characterized in that, also comprise: after forming described source/drain region, carry out annealing in process.
4. the manufacture method of transistor as claimed in claim 1, it is characterized in that, described transistor is N-type, and described light dope ion is phosphonium ion; The energy range of described light dope ion implantation comprises 50keV ~ 100keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
5. the manufacture method of transistor as claimed in claim 1, it is characterized in that, described transistor is N-type, and described light dope ion is arsenic ion; The energy range of described light dope ion implantation comprises 90keV ~ 200keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
6. the manufacture method of transistor as claimed in claim 1, it is characterized in that, described transistor is P type, and described light dope ion is boron ion; The energy range of described light dope ion implantation comprises 12keV ~ 35keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
7. the manufacture method of transistor as claimed in claim 1, it is characterized in that, described transistor is P type, and described light dope ion is indium ion; The energy range of described light dope ion implantation comprises 80keV ~ 300keV, and the dosage range of described light dope ion implantation comprises 1E13/cm
2~ 1E14/cm
2.
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|---|---|---|---|---|
| US5217910A (en) * | 1990-11-05 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device having sidewall spacers and oblique implantation |
| US6426258B1 (en) * | 1997-12-24 | 2002-07-30 | Seiko Instruments Inc. | Method of manufacturing a semiconductor integrated circuit device |
| CN1635617A (en) * | 2003-12-29 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing pMOS for titanium silicide preparing process window |
| CN101911302A (en) * | 2008-01-10 | 2010-12-08 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method thereof |
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| US20060125041A1 (en) * | 2004-12-14 | 2006-06-15 | Electronics And Telecommunications Research Institute | Transistor using impact ionization and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5217910A (en) * | 1990-11-05 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device having sidewall spacers and oblique implantation |
| US6426258B1 (en) * | 1997-12-24 | 2002-07-30 | Seiko Instruments Inc. | Method of manufacturing a semiconductor integrated circuit device |
| CN1635617A (en) * | 2003-12-29 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing pMOS for titanium silicide preparing process window |
| CN101911302A (en) * | 2008-01-10 | 2010-12-08 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method thereof |
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