CN102315838A - Clock pulse circuit and time resetting method - Google Patents
Clock pulse circuit and time resetting method Download PDFInfo
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- CN102315838A CN102315838A CN201010220761XA CN201010220761A CN102315838A CN 102315838 A CN102315838 A CN 102315838A CN 201010220761X A CN201010220761X A CN 201010220761XA CN 201010220761 A CN201010220761 A CN 201010220761A CN 102315838 A CN102315838 A CN 102315838A
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Abstract
The invention provides a clock pulse circuit and a time resetting method and can be applied to a time circuit. The time circuit provides time information according to a reference clock pulse. The clock pulse circuit comprises a clock pulse detector which is used for detecting whether the reference clock pulse interrupts, wherein when the reference clock pulse interrupts, a clock pulse interruption signal is generated as a reference of resetting of the time circuit.
Description
Technical field
The present invention relates to a kind of reset circuit of clock pulse circuit, reset effectively real-time circuit is produced.
Background technology
(real time clock's real-time clock RTC) is widely used, for example a lot of all free information of electronic product.Temporal information for example can be used to write down the application of time of origin of each Action Events or the like.Therefore, real-time clock also is a reference time information.
General fashion, real-time clock are to rely on the running of direct capacitance store charge.When the battery removal, can there be difference the running time according to real-time clock circuit electricity consumption condition.The running time is also different with regard to receiving the influence of direct capacitance appearance value and IC processing procedure simultaneously.Therefore, when charge depletion, real-time clock just decommissions.In battery reinstalled, real-time clock need rely on a reset signal that entire circuit is resetted, and with this circuit malfunction of prompting user, need reset the time.But the different influences such as voltage, circuit and element that the length of this reset signal and real-time clock starting of oscillation time are all supplied power.
That is to say how to guarantee the real-time clock active homing, is a problem.
Summary of the invention
The present invention provides clock pulse circuit and time repositioning method, can effectively guarantee resetting of real-time clock at least.
According to an embodiment, the present invention proposes a kind of clock pulse circuit can be used in a time circuit.Time circuit provides a time information according to one with reference to clock pulse.The clock pulse circuit comprises a clock pulse detector, whether should be in order to detecting with reference to clock pulse generation disruption, wherein when this during with reference to clock pulse generation disruption, send the foundation that a clock pulse interrupt signal resets as this time circuit.
According to an embodiment, in described clock pulse circuit, the clock pulse detector provides an operating power by a bias unit.The clock pulse detector for example comprises a capacitor, a derailing switch and a comparator.Capacitor is connected between this bias unit and the ground voltage, wherein a link of capacitor and bias unit output one detecting voltage.Derailing switch is connected between bias unit and the ground voltage parallelly connected with this capacitor.When with reference to a clock pulse edge interval of clock pulse the time with regard to this derailing switch of conducting, when not at the clock pulse edge interval, just break off this derailing switch.Comparator receives detecting voltage and reference voltage, when detecting voltage greater than reference voltage, sends this reset signal.
The present invention proposes a kind of time repositioning method; A time circuit is used to reset; Comprise receiving one of this time circuit whether should be with reference to clock pulse generation disruption with reference to clock pulse and detecting; Wherein when this during with reference to clock pulse generation disruption, send the foundation of a clock pulse interrupt signal as this time circuit that whether resets.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphic elaborating as follows.
Description of drawings
Fig. 1 is the block schematic diagram that a system cooperates the real-time clock circuit.
Fig. 2 is the block schematic diagram that cooperates reset circuit according to the clock pulse circuit of one embodiment of the invention.
Fig. 3 is the block schematic diagram that cooperates reset circuit according to another clock pulse circuit of one embodiment of the invention.
Fig. 4 is the circuit diagram according to the clock pulse detector of one embodiment of the invention.
Fig. 5 is the circuit diagram according to another clock pulse detector of one embodiment of the invention.
Fig. 6 is the characteristic sketch map according to the clock pulse edge interval of one embodiment of the invention.
Fig. 7 is the clock pulse detecting schematic diagram of mechanism according to one embodiment of the invention.
Fig. 8 is the schematic flow sheet that resets according to time of one embodiment of the invention.
Reference numeral:
100: power management IC;
102: system;
104: real-time clock (RTC);
106: reset circuit;
200: crystal oscillator (OSC);
202: buffer (BUF);
204: time circuit;
206: the voltage generation unit;
208: the clock pulse detector;
210: reset circuit;
212: comparator;
212 ': circuits for triggering;
218: derailing switch;
220: capacitor;
300: storage device;
S100～S118: step.
Embodiment
The time reset mechanism that the present invention proposes can provide a reliable reset signal, and it can be not affected by environment, and effective RTC reset signal can be provided.This circuit also can the effective application power supply, can continue to detect the oscillating crystal of generation with reference to clock pulse, can guarantee that the proper reset circuit is up to the clock pulse operate as normal.
Below lift some embodiment the present invention is described, but the present invention is not limited only to the embodiment that lifted.Also can suitably mutually combine between the embodiment.
Real-time clock provides the real time of a system, helps understanding an operating state of whole system relative time.Therefore, the real-time clock circuit is a basic circuit, and need correspond to the real time, if the time that the real-time clock circuit produces is inaccurate, for example can cause the mistake of corresponding time of each incident of system.
Fig. 1 is the block schematic diagram that a system cooperates the real-time clock circuit.Consult Fig. 1, battery provides power supply to a system 102 through a power management IC 100, also provides power supply to real-time clock (RTC) 104 circuit simultaneously.When battery was dismantled, reset circuit 106 can startup send reset signal to real-time clock (RTC) 104 circuit.
Fig. 2 is the block schematic diagram that cooperates reset circuit according to the clock pulse circuit of one embodiment of the invention.Consult Fig. 2, the framework of clock pulse circuit can comprise a time circuit 204 and a clock pulse detector 208.Time circuit 204 for example is real-time clock (RTC) circuit, according to the clock pulse of reference, uses to external system in order to real time information to be provided.The clock pulse of reference for example is to provide through a crystal oscillator (OSC) 200, again through producing after the delay of buffer (BUF) 202.With reference to clock pulse is to be in high-frequency clock signal, after being received by time circuit 204, converts temporal information to.
Under the usual condition, before the direct capacitance electric charge does not exhaust fully, that is to say that voltage reduces to that crystal oscillator 200 just can decommission before 0, this is because the running of crystal oscillator 200 need maintain an operating voltage.
Whether clock pulse detector 208 is arranged in the reset circuit 210, by voltage generation unit 206 power supply is provided, and also receives the clock pulse of reference in addition, to detect with reference to clock pulse generation disruption.When with reference to clock pulse generation disruption, send a clock pulse interrupt signal, for example be high potential, as the reset signal of time circuit 204.When getting back to normal condition with reference to clock pulse, the clock pulse interrupt signal is for example changed into electronegative potential, and not resetting time circuit 204.It is by the system requirements decision that the clock pulse interrupt signal is enabled by high potential or electronegative potential, is not restricted to enabled by high potential.
Fig. 3 is the block schematic diagram that cooperates reset circuit according to another clock pulse circuit of one embodiment of the invention.Consult Fig. 3; The framework of present embodiment is similar with Fig. 2 with operation mechanism; But the reset signal of sending for example is temporarily to be stored in a storage device 300 earlier, for example is a buffer, and it reads the value of this storage device 300 through software or other hardware; And how decision is disposed time circuit 204, for example right resetting time circuit 204.
In order to reach the function of above-mentioned clock pulse detector 208, below lift an embodiment and explain.Fig. 4 is the circuit diagram according to the clock pulse detector of one embodiment of the invention.Consult Fig. 4, voltage generation unit 206 for example is that the mode with current source provides power supply to clock pulse detector 208.The clock pulse of clock pulse detector 208 received pulse forms.Clock pulse detector 208 provides power supply by voltage generation unit 206, and wherein clock pulse detector 208 comprises a capacitor 220, a derailing switch 218 and a comparator 212.Capacitor 220 is connected between a voltage generation unit 206 and the ground voltage.Link output one detecting voltage between capacitor 220 and the voltage generation unit 206 is represented with VRTC.Derailing switch 218 is connected between voltage generation unit 206 and the ground voltage, and parallelly connected with capacitor 220.Derailing switch 218 is controlled according to clock pulse.When with reference to a clock pulse edge interval of clock pulse the time with regard to actuating switch device 218, when not at the clock pulse edge interval with regard to cut-off switch device 218.Comparator 212 receives a detecting voltage (VRTC) and a reference voltage.Reference voltage is represented with VREF.Just send reset signal when detecting voltage (VRTC) greater than VREF.
Fig. 5 is the circuit diagram according to another clock pulse detector of one embodiment of the invention.Consult Fig. 5, its circuit is similar with Fig. 4 with operation mechanism, can be accomplished by circuits for triggering 212 '.Circuits for triggering 212 ' for example are Shi Mite circuits for triggering (Schmitt Trigger).When detecting voltage surpasses the trigger voltage that the Shi Mite circuits for triggering set, just send the reset signal of clock pulse interrupt signal as time circuit.
How to detect the edge of clock pulse and how control switch device 218 can adopt general technology to reach, and need not particular form.Yet clock pulse detector 208 is the effects that will reach the detecting clock pulse, and its mechanism is described in Fig. 7.
The following characteristic of describing the clock pulse edge interval earlier.Fig. 6 is the characteristic sketch map according to the clock pulse edge interval of one embodiment of the invention.Consult Fig. 6, clock pulse for example is a pulse signal, and it has and rises or the drop edge.The edge detection signal can produce a short pulse on the edge of, can be used for the conducting and the disconnection of control switch device.The width of short pulse is decided according to actual needs.Can learn through the edge detection signal whether clock pulse interrupts.
Fig. 7 is the clock pulse detecting schematic diagram of mechanism according to one embodiment of the invention.Consult Fig. 7 and Fig. 4, if clock pulse is when running, the edge detection signal can produce short pulse according to its frequency.This short pulse can make derailing switch 218 conductings, impels capacitor 220 discharges.Interval at non-edge, edge detection signal meeting cut-off switch device 218 is recharged capacitor 220.Because the clock pulse cycle is very short, so the charging interval of capacitor 220 is short, and its magnitude of voltage VRTC does not surpass reference voltage level VREF as yet will get back to ground voltage because of discharge.
When clock pulse takes place to interrupt, do not have the edge in a short time and occur.Therefore, capacitor 220 can be continued charging or even the voltage that reaches capacity.So, the VRTC when capacitor 220 just can judge that greater than reference voltage level VREF clock pulse interrupts.So a reset signal can be issued.When clock pulse was got back to normal running again, the clock pulse edge can occur again, caused capacitor 220 discharges, and stopped to send reset signal.
In other words, detect the clock pulse of clock generating circuit with circuit.Before clock pulse does not normally occur, can send reset signal, and keep this signal and after clock pulse produces, just can turn off this reset signal.If but during the course, clock pulse disappears again, then reset signal still can take place once again, occurs once again up to clock pulse.Can guarantee that so circuit is that running is having the situation of normal clock pulse, and circuit resetted really, can not take place that clock pulse has operated but situation that reset signal produces not yet, or reset signal is finished, but clock pulse normal operation not yet.
From the flow process of operation, it can be represented with an operating process.Fig. 8 is the schematic flow sheet that resets according to time of one embodiment of the invention.Consult Fig. 8, step S100 represents the time started flow process that resets.At step S102, the bias circuit starting is to provide needed power supply.At step S104, circuit for detecting starts, and begins to detect the state of clock pulse.At step S106, whether decision receives clock signal.At step S108,, just capacitor is charged if do not receive clock signal.At step S110, when capacitor was charged, relatively whether VRTC greater than VREF, if VRTC is greater than the VREF step S116 that arrives.If VRTC just gets back to step S106 greater than VREF.Subsequent steps S106 at step S112, just produces switch controlling signal and makes the derailing switch conducting if receive clock signal.At step S114, because the derailing switch conducting just produces discharge to capacitor.At step S116, send reset signal.At step S118, this homing action finishes, yet whole flow process can be got back to step S106, continues the detecting clock pulse.
The time reset mechanism that the present invention proposes can provide a reliable clock pulse detecting mechanism, and effective RTC reset signal can be provided.The time reset mechanism also can effectively be utilized power supply, continues detecting and produces the oscillating crystal with reference to clock pulse, through circuit for detecting, can guarantee to send correct reset signal, up to the clock pulse operate as normal.
But the present invention also can guarantee the limit of the running of clock pulse until opereating specification, and need not receive the accurate position influence of voltage.This is because circuit is the detecting clock pulse, and under the effective situation of clock pulse, but all normal operations of circuit need not be handled especially.But general circuit then can need detecting voltage, and a preset critical value just stops circuit, and is unusual to avoid running.So under identical capacitance, this circuit can let the time of running longer.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, and any affiliated those skilled in the art are not breaking away from the spirit and scope of the present invention; When doing a little change and retouching, so protection scope of the present invention is when being as the criterion with the scope that claim was defined.
Claims (9)
1. a clock pulse circuit can be used for a time circuit, and this time circuit provides a time information according to one with reference to clock pulse, and this clock pulse circuit comprises:
Whether one clock pulse detector should be with reference to clock pulse generation disruption in order to detecting, wherein when this during with reference to clock pulse generation disruption, send the foundation whether a clock pulse interrupt signal is reset as this time circuit.
2. clock pulse circuit according to claim 1 is characterized in that, wherein the value of this clock pulse interrupt signal will be stored in the foundation to reset as this time circuit in the storage device.
3. clock pulse circuit according to claim 1 is characterized in that, wherein this clock pulse detector provides an operating power by a bias unit, and this clock pulse detector comprises:
One capacitor is connected between this bias unit and the ground voltage, wherein a link of this capacitor and this bias unit output one detecting voltage;
One derailing switch is connected between this bias unit and this ground voltage parallelly connectedly with this capacitor, wherein when at this this derailing switch of conducting during with reference to a clock pulse edge interval of clock pulse, when not at this clock pulse edge interval, breaks off this derailing switch;
And a comparator, receiving should detecting voltage and a reference voltage, when this detecting voltage sends the reset signal of this clock pulse interrupt signal as this time circuit during greater than this reference voltage.
4. clock pulse circuit according to claim 3 is characterized in that, wherein this clock pulse detector comprises that a clock pulse edge detection device should determine this clock pulse edge interval with reference to clock pulse with detecting.
5. clock pulse circuit according to claim 3 is characterized in that, wherein the conducting through this derailing switch makes this capacitor discharge when this clock pulse edge interval, and the disconnection through this derailing switch in the time of beyond this clock pulse edge interval makes this capacitor charging.
6. clock pulse circuit according to claim 1 is characterized in that, wherein this clock pulse detector provides an operating power by a bias unit, and this clock pulse detector comprises:
One capacitor is connected between this bias unit and the ground voltage, wherein a link of this capacitor and this bias unit output one detecting voltage;
One derailing switch is connected between this bias unit and this ground voltage parallelly connectedly with this capacitor, wherein when at this this derailing switch of conducting during with reference to a clock pulse edge interval of clock pulse, when not at this clock pulse edge interval, breaks off this derailing switch;
And circuits for triggering, receiving should detecting voltage, when this detecting voltage surpasses the trigger voltage of these circuits for triggering, sends the reset signal of this clock pulse interrupt signal as this time circuit.
7. time repositioning method, the time circuit that is used to reset comprises:
Receive this time circuit one with reference to clock pulse;
And whether detecting should be with reference to clock pulse generation disruption, wherein when this during with reference to clock pulse generation disruption, send whether the reset foundation of this time circuit of clock pulse interrupt signal conduct.
8. time repositioning method according to claim 7; It is characterized in that; Wherein whether detecting should be to decide according to this one edge occurrence frequency with reference to clock pulse with reference to this step of clock pulse generation disruption, when in a period of time, not detecting the clock pulse edge variation, was judged to be and interrupted.
9. time repositioning method according to claim 7 is characterized in that, wherein whether detecting should comprise with reference to this step of clock pulse generation disruption:
Utilize a capacitor and a switch of parallel connection, be connected between a bias generator and the ground voltage;
It is interval to detect this one edge with reference to clock pulse;
When at this this edge interval with reference to clock pulse, this switch of conducting is to this capacitor discharge;
When not at this this edge interval, break off this switch and make bias generator this capacitor charging with reference to clock pulse;
And, send the reset signal of this clock pulse interrupt signal as this time circuit when a magnitude of voltage of this capacitor during greater than a reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010220761XA CN102315838A (en) | 2010-07-02 | 2010-07-02 | Clock pulse circuit and time resetting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010220761XA CN102315838A (en) | 2010-07-02 | 2010-07-02 | Clock pulse circuit and time resetting method |
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| Publication Number | Publication Date |
|---|---|
| CN102315838A true CN102315838A (en) | 2012-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010220761XA Pending CN102315838A (en) | 2010-07-02 | 2010-07-02 | Clock pulse circuit and time resetting method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917350A (en) * | 1997-03-28 | 1999-06-29 | Cypress Semiconductor Corp. | Asynchronous pulse discriminating synchronizing clock pulse generator with synchronous clock suspension capability for logic derived clock signals for a programmable device |
| CN1255691A (en) * | 1998-11-30 | 2000-06-07 | 日本电气株式会社 | Power supply circuit builting integrated circuit |
| JP2003075479A (en) * | 2001-09-05 | 2003-03-12 | Advantest Corp | Clock source, time measuring apparatus, tester and oscillator |
| US6668334B1 (en) * | 2000-06-27 | 2003-12-23 | Lucent Technologies Inc. | Apparatus for detecting clock failure within a fixed number of cycles of the clock |
-
2010
- 2010-07-02 CN CN201010220761XA patent/CN102315838A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917350A (en) * | 1997-03-28 | 1999-06-29 | Cypress Semiconductor Corp. | Asynchronous pulse discriminating synchronizing clock pulse generator with synchronous clock suspension capability for logic derived clock signals for a programmable device |
| CN1255691A (en) * | 1998-11-30 | 2000-06-07 | 日本电气株式会社 | Power supply circuit builting integrated circuit |
| US6668334B1 (en) * | 2000-06-27 | 2003-12-23 | Lucent Technologies Inc. | Apparatus for detecting clock failure within a fixed number of cycles of the clock |
| JP2003075479A (en) * | 2001-09-05 | 2003-03-12 | Advantest Corp | Clock source, time measuring apparatus, tester and oscillator |
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Application publication date: 20120111 |