CN102337541A

CN102337541A - Etching method used in process of manufacturing conical through silicon via (TSV)

Info

Publication number: CN102337541A
Application number: CN2011102886691A
Authority: CN
Inventors: 陈骁; 罗乐; 徐高卫
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2011-09-23
Filing date: 2011-09-23
Publication date: 2012-02-01

Abstract

The invention relates to an etching method used in the process of manufacturing a conical through silicon via (TSV). The method is characterized by comprising the following steps of: depositing a SiO2 layer on the front side of a silicon wafer, and photoetching to remove SiO2 from a graph and expose silicon on the lower side; putting into a special treatment steel (STS) etching machine, and performing first-step etching on the front side of the silicon wafer, wherein an etching stage and a passivation stage are performed alternately in the first-step etching process so as to obtain a vertical deep hole with the depth of 50 to 200 micrometers; and performing second-step etching on the front side of the silicon wafer, and thus obtaining a conical deep hole in an inverted trapezoid shape. The etching method is high in maneuverability and is suitable for industrial production, the process cost of the TSV of a wafer can be expected to be reduced, and the electroplating filling yield of the TSV is improved.

Description

A kind of lithographic method that adopts when the silicon through hole is worn in taper of making

Technical field

The present invention relates to a kind of making taper and wear silicon through hole (Through Silicon Via; TSV) employed lithographic method the time, described lithographic method is workable, is suitable for suitability for industrialized production; Not only reduce the technology cost of making wafer TSV, and improved the yield rate of the plating filling of TSV.

Background technology

In order to satisfy the needs of VLSI (VLSI) development, novel 3D stacked package technology is arisen at the historic moment.It is with minimum size and the lightest weight; The chip and the multiple technologies of different performance are integrated in the single package, are a kind of through making vertical electricity conducting between chip and the chip, between wafer and the wafer, realize the up-to-date encapsulation interconnection technique that interconnects between the chip; Different with IC encapsulation bonding in the past with the superimposing technique of using salient point; Described encapsulation interconnection technique is to adopt TSV (Through Silicon Via wears the silicon through hole) to replace the 2D-Cu interconnection, can make chip maximum in the density that three-dimensional piles up; Physical dimension is minimum, and improves the performance of chip speed and reduce power consumption greatly.Therefore, managining director doctor Tang Heming of research and development centre of day moonlight consortium on the Chartered2007 technical seminar TSV is called after line bonding (Wire Bonding), carrier band weld (TAB) and flip-chip (FC) automatically the 4th generation encapsulation technology.

In order to realize the TSV wafer-level packaging of IC device, need to accomplish the exploitation of several important process technology.(1) through hole preparation adopts DRIE on wafer, to prepare the Si through hole of high aspect ratio; (2) the electroplates in hole, deposit SiO on through-hole side wall ₂Behind the insulation layer, make through Seed Layer plated metal Cu to be full of whole Si through hole; (3) chemically machinery polished (CMP) is adopted CMP that excessive Cu is ground away continued grinding wafer and can be obtained different thickness TSV disk; (4) bonding technology after accurate aligning the between disk and disk or chip and the disk.In the middle of above-mentioned several important process, the etching of TSV is a very crucial operation.Consider cost, factors such as precision control are generally tended to use dry etching to make TSV.The etching process more complicated, distributing position, density and the size of through hole (comprising hole depth and aperture) are different among the different three-dimensional IC.The through hole Technology Need can satisfy the control (comprising control obliquity, shape, roughness, over etching etc.) to outline shape, requires technology can have safety, practicality and repeatability again simultaneously, and last, cost is also wanted can be by control rationally.BOSCH technology etching is generally used in the making of TSV, and this is a kind of dark silicon etching process based on plasma etching.In etching process, switch etching and deposition through Rapid Cycle, promptly in each etching loop cycle, the silicon of exposure is by isotropic etching; Deposit one layer of polymeric protection again, the polymkeric substance removal that is decomposed then, the silicon of exposure is etched again; Go round and begin again, until EP.Thereby the realization deep etching, and the through hole side is very vertical.Rectilinear through hole helps promoting the quantity and the density of through hole; But for this structure of TSV with vertical side wall, high aspect ratio; The deposition of follow-up insulation layer, blocking layer and Seed Layer; And the TSV electroplating technology all is difficult to reach requirement, has high technology difficulty, increased cost of manufacture.The difficult control of subsequent deposition process.Such as depositing of thin film, because the TSV aperture of vertical-type is very little, the degree of depth is very big, and therefore traditional depositing operation can only be deposited on the TSV opening part, and is difficult to deposit than the sidewall and the bottom of depths at TSV; Aspect the TSV plating, because the Cu of electroplate liquid ²⁺Obviously greater than the speed at TSV hole depth place, so the difference of electroplating velocity makes and the more opening parts that are deposited on vertical TSV of copper blocks, and form empty in the hole in more thereby cause the TSV opening to be filled by copper in the opening part of TSV diffusion translational speed.

Summary of the invention

In order to reduce the manufacture craft difficulty of TSV; The realization of the subsequent technique after the solution TSV etching; The object of the present invention is to provide the process method of a kind of making taper (trapezoidal) TSV, described taper is actual to be trapezoidal, above promptly big below little a kind of taper.

Technical scheme of the present invention is: the etching of making taper TSV at first deposits the SiO of one deck 1.5-3 μ m in two steps ₂Layer is with SiO after the photoetching ₂As etch mask, carry out the first step etching then, promptly adopt the BOSCH etching technics to form the deep hole of vertical side wall, the method for BOSCH technology is at first to carry out passivation, feeds the amount C of a constant current ₄F ₄6 seconds of gas form passivation layer, feed the gas SF of certain flow then ₆, remove passivation layer 5 seconds, and carry out the etching of Si base material, in the step of etching, attached to the partial sidewall polymkeric substance on the previous adhesion layer, just previous C ₄F ₄The C that produces after the gas ionizing, CF ₂Or C ₂F ₄On particle, at silicon face formation of deposits polymkeric substance, and the polymkeric substance that forms is a kind of adjustable sidewall passivation layer, and this passivation layer breaks away from sidewall and moves once more under the influence of non-perpendicular ion impact sidewall, on darker sidewall, adheres to again.Like this, the polymeric film on the sidewall is constantly driven downwards to be adhered to, thereby forms a partial anisotropic etching.The BOSCH technology is exactly to hocket through passivation/etching to realize the etching of vertical long hole; Whole processing parameter is provided with on the STS dry etching machine; The time that BOSCH technology is carried out has determined passivation/etching alternative number of times, and proportional with the deep hole degree of depth of etching.Carry out the second step etching then, only feed etching gas SF ₆, opening part reduces to the hole bottom direction gradually along the hole owing to etching gas content, along with the difference of etching time, can realize the taper pattern of different ratios.

Beneficial effect of the present invention: this invented technology simply can realize follow-up high-quality thin film deposition and electroplating technology; Avoided above-mentioned technology because vertical side wall TSV and the costs of a large amount of again research and development; And this invented technology is workable; Be suitable for suitability for industrialized production, not only reduce the technology cost of making wafer TSV, and improved the yield rate of the plating filling of TSV.

Description of drawings

Fig. 1 is SiO ₂Be mask, the preceding silicon chip cross-sectional configuration figure of etching.

Fig. 2 has been the silicon chip cross-sectional configuration figure that obtains vertical long hole after the first step etching.

Fig. 3 has been the silicon chip cross-sectional configuration figure that obtains tapered hole after second etching.

Embodiment

For advantage of the present invention and positively effect are found full expression, the present invention is explained further below in conjunction with accompanying drawing and embodiment.

In Fig. 1, at silicon chip 101 positive deposition one deck SiO ₂Layer 102, thickness 1.5-3 μ m, SiO ₂The thickness of layer depends on the degree of depth 50-200 μ m of the deep hole that needs etching, and photoetching picture then is with the SiO that exposes after the photoetching ₂Remove through the RIE etching, expose following silicon.

In Fig. 2, put into STS etching machine, the first step etching is carried out in silicon chip 101 fronts, etching the degree of depth is the deep hole 103 of 50-200 μ m, the concrete parameter of etching is:

1. etch stages: SF ₆Gas flow be 130sccm; O ₂Gas flow be 13sccm; The power of Coil is 600W; The power of Platen is 20W; Pressure is 26mt; The time of etch stages is 6s.

2. passivation stage: SF ₆Gas flow be 0; C ₄F ₈Gas flow be 85sccm; The power of Coil is 600W; The power of Platen is 0W; Pressure is 17mt; The time in passivation stage is 5s.

Etch stages and passivation stage hocket in this step, and the total time of the first step is 30min-140min, can obtain the TSV of the 50-200 μ m degree of depth, and the processing parameter in this step is applicable to the TSV in various different apertures.

In Fig. 3, the second step etching is carried out in silicon chip 101 fronts, etch tapered hole 104, the concrete parameter of etching is:

SF ₆Gas flow be 130sccm; O ₂Gas flow be 13sccm; The power of Coil is 700W; The power of Platen is 20W; Pressure is 12mt; The total time in second step is 5-17min, can realize the taper pattern of different ratios, and the 5min etching time can realize that the last aperture of TSV is 1.2-1.3 a times of aperture under it; Along with the prolongation of etching time, its ratio increases, and reaches 17min until etching time; Ratio increases to peak 2-2.2 doubly; Etching time continues to prolong, and the taper pattern basically no longer changes, and the processing parameter in this step is applicable to the TSV in various different apertures.

Claims

1. make the lithographic method that adopts when the silicon through hole is worn in taper for one kind, it is characterized in that at first at the positive deposition of silicon chip one deck SiO ₂, the SiO in the figure is removed in photoetching then ₂, expose following silicon.Put into STS etching machine, the first step etching is carried out in the silicon chip front, etch stages and passivation stage hocket in the process of the first step etching, thereby obtain out the vertical long hole that the degree of depth is 50-200 μ m; Then the second step etching is carried out in the silicon chip front, etch deep hole with the taper of falling trapezoid pattern.

2. by the described method of claim 1, concrete steps are:

(1) at the positive deposition of silicon chip one deck SiO ₂, thickness 1.5-3 μ m, photoetching then is with the SiO that exposes after the photoetching ₂Remove through the RIE etching, expose following silicon.

(2) then silicon chip is put into STS etching machine; The first step etching is carried out in the silicon chip front; Etch the deep hole that the degree of depth is 50-200 μ m; Etch stages and passivation stage hocket in described this step, and the total time of the first step is 40min-140min, obtain the TSV of the 50-200 μ m degree of depth.

(3) the second step etching is carried out in the silicon chip front, etch tapered hole, the concrete parameter of etching is: SF ₆Gas flow be 130sccm; O ₂Gas flow be 13sccm; The power of Coil is 700W; The power of Platen is 20W; Pressure is 12mt; The total time in second step is 5-17min, and the last aperture of realizing TSV is 1.2-2.2 a times of aperture under it.

3. by the described method of claim 2, the concrete parameter of etching is when it is characterized in that the described the first step etching that the silicon chip front is carried out:

1. etch stages: SF ₆Gas flow be 130sccm; O ₂Gas flow be 13sccm; The power of Coil is 600W; The power of Platen is 20W; Pressure is 26mt; The time of etch stages is 6s;

4. by the described method of claim 2, it is characterized in that for second step during etching, the 5min etching time realizes that the last aperture of TSV is its 1.2-1.3 times of aperture down; Prolong with etching time, its ratio increases, and reaches 17min until etching time, and the last aperture of TSV increases to peak 2-2.2 doubly with the ratio in following aperture; Etching time continues to prolong, and the taper pattern basically no longer changes.

5. by claim 1 or 2 described methods, it is characterized in that the first step etching process adopts the BOSCH etching technics to form the deep hole of vertical side wall.