CN102354681A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN102354681A CN102354681A CN2011103353618A CN201110335361A CN102354681A CN 102354681 A CN102354681 A CN 102354681A CN 2011103353618 A CN2011103353618 A CN 2011103353618A CN 201110335361 A CN201110335361 A CN 201110335361A CN 102354681 A CN102354681 A CN 102354681A
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Abstract
The invention discloses a method for manufacturing a semiconductor device. The method has the following beneficial effects: the depths of a dummy metal slot and supporting graphic dummy metal slot are smaller than the depth of a metal conductor slot; therefore the heights of the finally formed dummy metal wire and supporting graphic dummy metal wire are smaller than the height of a metal conductor; and compared with the prior art, the thicknesses (heights) of the dummy metal wire and supporting graphic dummy metal wire are reduced, the photoetching process window can be effectively expanded and the coupling capacitances which are introduced during filling the dummy metal wire and the supporting graphic dummy metal wire, in the metal layers and among the metal layers are reduced.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of manufacturing method of semiconductor device.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain through etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts is the embedding technique that is called Damascus technics now.This Damascus technics comprises single Damascus technics of only making plain conductor and makes the dual damascene process of through hole (also claiming contact hole) and plain conductor simultaneously.Specifically; Single damascene structure (also claiming single inlay structure) only is that the production method of single-layer metal lead is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled); Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half via-first method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; In dielectric layer 110, form metallic channel through photoetching and etching technics then; Depositing metal layers subsequently, said metal level are filled in the metallic channel and on said dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technology and remove the metal on the said dielectric layer 110, thereby in said metallic channel, processed plain conductor 140.
As stated, in Damascus technics, need utilize chemical mechanical milling tech, be embedded in the plain conductor 140 in the dielectric layer 110 with final formation.Yet,, therefore can cause the depression of not expecting (dishing) and corrode (erosion) phenomenon the selectivity of grinding because the rate that removes of metal and dielectric layer material is generally inequality.Depression occurs in metal often and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is thin excessively.Depression and erosion are subject to the structure of figure and the density influence of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, the method for solution is to fill the pattern density homogenizing that redundant metal line pattern makes domain at the white space of domain, thereby also forms redundant metal wire (dummy metal) 150 when in dielectric layer 110, forming plain conductor 140, as shown in Figure 2.But,, but introduced in the extra metal level inevitably and the coupling capacitance of metal interlevel though redundant metal wire has improved the uniformity of pattern density.
In order to reduce the negative effect that extra coupling capacitance brings device, when the redundant metal of design, to reduce the filling quantity of redundant metal as far as possible, and make main graphic (plain conductor figure) big as far as possible with redundant intermetallic distance.Yet the excessive pattern density of regional area that can cause again of the spacing of main graphic and redundant metal is inhomogeneous, influences the regional area flatness of chemical mechanical milling tech.Under given live width condition, the depth of focus of various bargraphss (DOF) process window has following relationship: intensive lines＞half intensive lines＞isolated lines.Utilize this relation, increase the process window that auxiliary pattern can enlarge half intensive lines and isolated lines at half intensive lines and isolated lines side.That is, auxiliary pattern can enlarge the lithographic process window of half intensive lines and isolated lines, improves the regional area flatness of the cmp of metal, but also can cause in the bigger metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor device, to enlarge lithographic process window effectively and to reduce redundant metal wire and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms etching barrier layer;
On said first dielectric layer and etching barrier layer, form second dielectric layer;
Said second dielectric layer of etching, first dielectric layer and etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said etching barrier layer is less than the etch rate of said first dielectric layer and second dielectric layer, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on second dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
Optional, form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: said second dielectric layer of etching and first dielectric layer form through hole with the correspondence position at said metallic channel.The material of said etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Said first dielectric layer and second dielectric layer are the low k dielectric layer.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms etching barrier layer;
On said first dielectric layer and etching barrier layer, form second dielectric layer;
On said second dielectric layer, form hard mask layer; And the said hard mask layer of etching; On redundant metal area, to form the redundant groove of hard mask, on the redundant metal area of auxiliary pattern, form hard mask auxiliary pattern groove, on the nonredundancy metal area, form hard mask metallic channel;
Said second dielectric layer of etching, first dielectric layer and etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said etching barrier layer is less than the etch rate of said first dielectric layer and second dielectric layer, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on second dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
Optional, form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: said second dielectric layer of etching and first dielectric layer form through hole with the correspondence position at said metallic channel.The material of said etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Said first dielectric layer and second dielectric layer are the low k dielectric layer.
The present invention provides a kind of manufacturing method of semiconductor device again, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms first etching barrier layer;
On said first dielectric layer and first etching barrier layer, form second dielectric layer;
Second dielectric layer surface on said redundant metal area or the redundant metal area of auxiliary pattern forms second etching barrier layer;
On said second etching barrier layer and second dielectric layer, form the 3rd dielectric layer;
Said the 3rd dielectric layer of etching, second etching barrier layer, second dielectric layer, first dielectric layer and first etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said first etching barrier layer and second etching barrier layer is less than the etch rate of said first dielectric layer, second dielectric layer and the 3rd dielectric layer; The degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel, and the degree of depth of the degree of depth of the redundant metallic channel of said auxiliary pattern and redundant metallic channel is inequality;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the 3rd dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said the 3rd dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
Optional, form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: said the 3rd dielectric layer of etching, second dielectric layer and first dielectric layer form through hole with the correspondence position at said metallic channel.The material of said first etching barrier layer and second etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Said first dielectric layer, second dielectric layer and the 3rd dielectric layer are the low k dielectric layer.
The present invention is through forming the etching barrier layer of etch rate less than dielectric layer; Make the degree of depth of the degree of depth of the redundant metallic channel of redundant metallic channel and auxiliary pattern less than metallic channel; The height of therefore final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor; Compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern; Can enlarge lithographic process window effectively, and reduce the redundant metal wire of redundant metal wire and auxiliary pattern and fill in the metal level of introducing the coupling capacitance with metal interlevel.
In addition; The present invention makes the degree of depth of the degree of depth of redundant metallic channel less than the redundant metallic channel of auxiliary pattern; Thereby the height of redundant metal wire that makes formation is less than the height of the redundant metal wire of auxiliary pattern, further reduces the redundant metal wire of auxiliary pattern and fills in the metal level of introducing the coupling capacitance with metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 A～3G is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention one;
Fig. 4 A～4H is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention two;
Fig. 5 A～5H is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention three;
Fig. 6 A～6I is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention four.
Embodiment
Mention that in background technology though the redundant metal wire of redundant metal wire and auxiliary pattern has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows that the relative area that reduces metal can reduce electric capacity with increase intermetallic distance.In view of this; The present invention makes the degree of depth of the degree of depth of redundant metallic channel and the redundant metallic channel of auxiliary pattern less than metallic channel; The height of therefore final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor; Compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern, can enlarge lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment one
Introduce the manufacturing process of single Damascus metal interconnect structure in detail below in conjunction with Fig. 3 A～3G; The redundant metallic channel that present embodiment forms is identical with the degree of depth of the redundant metallic channel of auxiliary pattern, thereby makes the redundant metal wire of formation identical with the height of the redundant metal wire of auxiliary pattern.
Shown in Fig. 3 A; Semiconductor substrate 300 is provided; Said Semiconductor substrate comprises redundant metal area 302, the redundant metal area 303 of auxiliary pattern and nonredundancy metal area 301; That is, the semiconductor substrate region except the redundant metal area 303 of redundant metal area 302 and auxiliary pattern is a nonredundancy metal area 301.Wherein, Be formed with metal line in the said Semiconductor substrate 300; Because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 300, forms metal line, but those skilled in the art are still this and know.
Shown in Fig. 3 B, on said Semiconductor substrate 300, form first dielectric layer 311.
Shown in Fig. 3 C, first dielectric layer, 311 surfaces on said redundant metal area 302 and the redundant metal area 303 of auxiliary pattern form etching barrier layers 330.
Shown in Fig. 3 D, on first dielectric layer 311 and etching barrier layer 330, form second dielectric layer 312, the gross thickness of said first dielectric layer 311 and second dielectric layer 312 is the degree of depth of the follow-up metallic channel 311a that will form.
Shown in Fig. 3 E; Said second dielectric layer 312 of etching, first dielectric layer 311 and etching barrier layer 330; To form redundant metallic channel 312a, the redundant metallic channel 313a of auxiliary pattern and metallic channel 311a; Because the etch rate of said etching barrier layer 330 is less than the etch rate of said first dielectric layer 311 and second dielectric layer 312; Therefore; Although be etching simultaneously, the degree of depth of final auxiliary pattern redundancy metallic channel 313a that forms and redundant metallic channel 312a will be less than the degree of depth of said metallic channel 311a.The degree of depth of the redundant metallic channel 313a of said auxiliary pattern and redundant metallic channel 312a and metallic channel 311a poor; Can be by the difference decision of the etch rate of etching barrier layer 330 and first dielectric layer 311 and second dielectric layer 312; Those skilled in the art are known technological parameter particularly according to experiment, repeat no more at this.
Preferably; The material of said etching barrier layer 330 is a kind of or its combinations in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide; Said first dielectric layer 311 and second dielectric layer 312 are the low k dielectric layer; Resistance capacitance to reduce its parasitic capacitance and metallic copper postpones, and satisfies the requirement of conduction fast.Preferable; It is black diamond (black diamond that said first dielectric layer 311 and second dielectric layer 312 all adopt the trade mark of Material Used (Applied Materials) company; BD) silicon oxide carbide; Perhaps adopt the Coral material of Novellus company; Perhaps adopting utilizes spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc. again.
Shown in Fig. 3 F, depositing metal layers 320 in said redundant metallic channel 312a, the redundant metallic channel 313a of auxiliary pattern and metallic channel 311a and on second dielectric layer 312.
Shown in Fig. 3 G; Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer 312; In redundant metallic channel 312a, to form redundant metal wire 322; In the redundant metallic channel 313a of auxiliary pattern, form the redundant metal wire 323 of auxiliary pattern; In metallic channel 311a, form plain conductor 321; Because the degree of depth of redundant metallic channel 313a of said auxiliary pattern and redundant metallic channel 312a is less than the degree of depth of metallic channel 311a; Therefore; The height of redundant metal wire 323 of auxiliary pattern and redundant metal wire 322 is less than the height of plain conductor 321; The present invention has compared with prior art reduced the thickness (highly) of redundant metal wire and the redundant metal wire of auxiliary pattern; Can enlarge lithographic process window effectively, and reduce the redundant metal wire of redundant metal wire and auxiliary pattern and fill in the metal level of introducing the coupling capacitance with metal interlevel.
Embodiment two
Present embodiment combines Fig. 4 A～4H to introduce the manufacturing process of the dual damascene metal interconnect structure of through hole elder generation etching in detail; The redundant metallic channel that present embodiment forms is identical with the degree of depth of the redundant metallic channel of auxiliary pattern, thereby makes the redundant metal wire of formation identical with the height of the redundant metal wire of auxiliary pattern.
Shown in Fig. 4 A, Semiconductor substrate 400 is provided, said Semiconductor substrate comprises redundant metal area 402, the redundant metal area 403 of auxiliary pattern and nonredundancy metal area 401.
Shown in Fig. 4 B, on said Semiconductor substrate 400, form first dielectric layer 411.
Shown in Fig. 4 C, first dielectric layer, 411 surfaces on said redundant metal area 402 and the redundant metal area 403 of auxiliary pattern form etching barrier layers 430.
Shown in Fig. 4 D, the gross thickness that on first dielectric layer 411 and etching barrier layer 430, forms second dielectric layer, 412, the first dielectric layers 411 and second dielectric layer 412 is the thickness of the follow-up metallic channel that will form.
Shown in Fig. 4 E, said second dielectric layer 412 of etching, to form through hole 412b at the follow-up correspondence position that will form metallic channel, certainly, in other embodiments, this step also can require first dielectric layer 411 of etched portions thickness according to actual process.
Shown in Fig. 4 F; Said second dielectric layer 412 of etching, first dielectric layer 411 and etching barrier layer 430; To form redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern; And form metallic channel 411a in through hole 412b corresponding position; Because the etch rate of said etching barrier layer 430 is less than the etch rate of said first dielectric layer 411 and second dielectric layer 412, so the degree of depth of redundant metallic channel 413a of auxiliary pattern and redundant metallic channel 412a will be less than the degree of depth of said metallic channel 411a.
Shown in Fig. 4 G, depositing metal layers 420 in said redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern and metallic channel 411a and on second dielectric layer 412.
Shown in Fig. 4 H; Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer 412; In redundant metallic channel 412a, to form redundant metal wire 422; In the redundant metallic channel 413a of auxiliary pattern, form the redundant metal wire 423 of auxiliary pattern; In metallic channel 411a, form plain conductor 421; Because the degree of depth of redundant metallic channel 413a of said auxiliary pattern and redundant metallic channel 412a is less than the degree of depth of said metallic channel 411a; Therefore; The height of redundant metal wire 423 of auxiliary pattern and redundant metal wire 422 is less than the height of said plain conductor 421; Compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern; Can enlarge lithographic process window effectively, and reduce the redundant metal wire of redundant metal wire and auxiliary pattern and fill in the metal level of introducing the coupling capacitance with metal interlevel.
Compare with embodiment one; Present embodiment forms through hole 412b earlier and then forms redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern and metallic channel 411a; Reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern, can enlarge lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment three
Shown in Fig. 5 A, Semiconductor substrate 500 is provided, said Semiconductor substrate 500 comprises redundant metal area 502, the redundant metal area 503 of auxiliary pattern and nonredundancy metal area 501.
Shown in Fig. 5 B, on said Semiconductor substrate 500, form first dielectric layer 511.
Shown in Fig. 5 C, first dielectric layer, 511 surfaces on said redundant metal area 502 and the redundant metal area 503 of auxiliary pattern form etching barrier layers 530.
Shown in Fig. 5 D, on first dielectric layer 511 and etching barrier layer 530, form second dielectric layer 512.
Shown in Fig. 5 E; On said second dielectric layer 512, form hard mask layer; And the said hard mask layer of etching; On redundant metal area 502, form the redundant groove 542a of hard mask; On the redundant metal area 503 of auxiliary pattern, form hard mask auxiliary pattern groove 543a, on nonredundancy metal area 501, form hard mask metallic channel 541a.
Shown in Fig. 5 F; Said second dielectric layer 512 of etching; First dielectric layer 511 and etching barrier layer 530; To form redundant metallic channel 512a; Redundant metallic channel 513a of auxiliary pattern and metallic channel 511a; Because the etch rate of said etching barrier layer 530 is less than the etch rate of first dielectric layer 511 and second dielectric layer 512; Therefore the degree of depth of redundant metallic channel 513a of auxiliary pattern and redundant metallic channel 512a is less than the degree of depth of said metallic channel 511a; Wherein, The redundant groove 542a of said hard mask; Hard mask auxiliary pattern groove 543a and hard mask metallic channel 541a can play self aligned effect in etching process; Can be etched away together in this etch step, perhaps utilize an other etching step to remove this hard mask layer.
Shown in Fig. 5 G, depositing metal layers 520 in said redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern and metallic channel 511a and on second dielectric layer 512.
Shown in Fig. 5 H; Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer 512; To form redundant metal wire 522, the redundant metal wire 523 of auxiliary pattern and plain conductor 521, the height of redundant metal wire 523 of said auxiliary pattern and redundant metal wire 522 is less than the height of plain conductor 521.
Present embodiment has been introduced the manufacturing process of the hard mask list of autoregistration formula Damascus metal interconnect structure in detail; Be understandable that; In other specific embodiment; Before forming redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern and metallic channel 511a; All right said second dielectric layer 512 of etching and first dielectric layer 511; To form through hole, can form the hard mask dual damascene of autoregistration formula metal interconnect structure thus in the position that will form metallic channel.
Embodiment four
Shown in Fig. 6 A, at first, Semiconductor substrate 600 is provided, said Semiconductor substrate 600 comprises redundant metal area 602, the redundant metal area 603 of auxiliary pattern and nonredundancy metal area 601.
Shown in Fig. 6 B, on said Semiconductor substrate 600, form first dielectric layer 611.
Shown in Fig. 6 C, first dielectric layer surface on said redundant metal area 602 and the redundant metal area 603 of auxiliary pattern forms first etching barrier layer 631.
Shown in Fig. 6 D, on said first dielectric layer 611 and first etching barrier layer 631, form second dielectric layer 612.
Shown in Fig. 6 E, second dielectric layer surface on the redundant metal area 603 of auxiliary pattern forms second etching barrier layer 632.Wherein, the material of said first etching barrier layer 631 and second etching barrier layer 632 is a kind of or its combinations in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Certainly, in other embodiments, also can form second etching barrier layer on the surface of second dielectric layer on the said redundant metal area 602.
Shown in Fig. 6 F; On second etching barrier layer 632 and second dielectric layer 612, form the 3rd dielectric layer 613; Wherein, First dielectric layer 611, second dielectric layer 612 and the 3rd dielectric layer 613 are preferably the low k dielectric layer; Preferable, first dielectric layer 611, second dielectric layer 612 are identical with the 3rd dielectric layer 613 materials.
Shown in Fig. 6 G; Said the 3rd dielectric layer 613 of etching; Second etching barrier layer 632; Second dielectric layer 612; First dielectric layer 611; First etching barrier layer 631 and second etching barrier layer 632; To form redundant metallic channel 612a; Redundant metallic channel 613a of auxiliary pattern and metallic channel 611a; Because the etch rate of said first etching barrier layer 631 and second etching barrier layer 632 is less than said first dielectric layer 611; The etch rate of second dielectric layer 612 and the 3rd dielectric layer 613; The degree of depth of redundant metallic channel 613a of therefore said auxiliary pattern and redundant metallic channel 612a is less than the degree of depth of said metallic channel 611a; And because the existence of second etching barrier layer 632, the degree of depth of the redundant metallic channel 613a of auxiliary pattern is less than the degree of depth of redundant metallic channel 612a.
Shown in Fig. 6 H, depositing metal layers 620 in said redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a and on the 3rd dielectric layer 613.
Shown in Fig. 6 I; Carrying out chemical mechanical milling tech until the surface that exposes said the 3rd dielectric layer 613; To form redundant metal wire 622, the redundant metal wire 623 of auxiliary pattern and plain conductor 621; The height of redundant metal wire 623 of said auxiliary pattern and redundant metal wire 622 is less than the height of plain conductor 621, and the height of the redundant metal wire 623 of auxiliary pattern is less than the height of redundant metal wire 622.
In other specific embodiment; Before forming redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a; Can also etching institute said the 3rd dielectric layer 613 of etching, second dielectric layer 612 and first dielectric layer 611; To form through hole, can form the redundant metal wire of the auxiliary pattern dual damascene metal interconnect structure different thus with redundant height of line in the position that will form metallic channel.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses all is the difference with other embodiment, the reference mutually of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for the purpose of convenience, each embodiment of aid illustration the present invention lucidly.
In addition, although abovely describe the present invention in detail with a plurality of embodiment respectively, those skilled in the art can also carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms etching barrier layer;
On said first dielectric layer and etching barrier layer, form second dielectric layer;
Said second dielectric layer of etching, first dielectric layer and etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said etching barrier layer is less than the etch rate of said first dielectric layer and second dielectric layer, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on second dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
2. manufacturing method of semiconductor device as claimed in claim 1; It is characterized in that; Form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: said second dielectric layer of etching and first dielectric layer form through hole with the correspondence position at said metallic channel.
3. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the material of said etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
4. like the manufacture method of any described semiconductor device in the claim 1 to 3, it is characterized in that said first dielectric layer and second dielectric layer are the low k dielectric layer.
5. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms etching barrier layer;
On said first dielectric layer and etching barrier layer, form second dielectric layer;
On said second dielectric layer, form hard mask layer; And the said hard mask layer of etching; On redundant metal area, to form the redundant groove of hard mask, on the redundant metal area of auxiliary pattern, form hard mask auxiliary pattern groove, on the nonredundancy metal area, form hard mask metallic channel;
Said second dielectric layer of etching, first dielectric layer and etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said etching barrier layer is less than the etch rate of said first dielectric layer and second dielectric layer, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on second dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said second dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
6. manufacturing method of semiconductor device as claimed in claim 5; It is characterized in that; Form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: said second dielectric layer of etching and first dielectric layer form through hole with the correspondence position at said metallic channel.
7. manufacturing method of semiconductor device as claimed in claim 5 is characterized in that, the material of said etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
8. like the manufacture method of any described semiconductor device in the claim 5 to 7, it is characterized in that said first dielectric layer and second dielectric layer are the low k dielectric layer.
9. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form first dielectric layer;
First dielectric layer surface on said redundant metal area and the redundant metal area of auxiliary pattern forms first etching barrier layer;
On said first dielectric layer and first etching barrier layer, form second dielectric layer;
Second dielectric layer surface on said redundant metal area or the redundant metal area of auxiliary pattern forms second etching barrier layer;
On said second etching barrier layer and second dielectric layer, form the 3rd dielectric layer;
Said the 3rd dielectric layer of etching, second etching barrier layer, second dielectric layer, first dielectric layer and first etching barrier layer; To form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel; The etch rate of said first etching barrier layer and second etching barrier layer is less than the etch rate of said first dielectric layer, second dielectric layer and the 3rd dielectric layer; The degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel, and the degree of depth of the degree of depth of the redundant metallic channel of said auxiliary pattern and redundant metallic channel is inequality;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the 3rd dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said the 3rd dielectric layer; To form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
10. manufacturing method of semiconductor device as claimed in claim 9; It is characterized in that; Form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel; Also comprise: said the 3rd dielectric layer of etching, second dielectric layer and first dielectric layer form through hole with the correspondence position at said metallic channel.
11. manufacturing method of semiconductor device as claimed in claim 9; It is characterized in that the material of said first etching barrier layer and second etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
12. the manufacture method like any described semiconductor device in the claim 9 to 11 is characterized in that, said first dielectric layer, second dielectric layer and the 3rd dielectric layer are the low k dielectric layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531578A (en) * | 2012-07-02 | 2014-01-22 | 台湾积体电路制造股份有限公司 | Semiconductor devices and methods of manufacture thereof |
| CN103531578B (en) * | 2012-07-02 | 2016-11-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103531578A (en) * | 2012-07-02 | 2014-01-22 | 台湾积体电路制造股份有限公司 | Semiconductor devices and methods of manufacture thereof |
| CN103531578B (en) * | 2012-07-02 | 2016-11-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
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