CN102354691A - Quad flat non-lead (QFN) package with high density and manufacturing method - Google Patents
Quad flat non-lead (QFN) package with high density and manufacturing method Download PDFInfo
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- CN102354691A CN102354691A CN201110344522XA CN201110344522A CN102354691A CN 102354691 A CN102354691 A CN 102354691A CN 201110344522X A CN201110344522X A CN 201110344522XA CN 201110344522 A CN201110344522 A CN 201110344522A CN 102354691 A CN102354691 A CN 102354691A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/3011—Impedance
Abstract
The invention discloses a quad flat non-lead (QFN) package with high density and a manufacturing method. The package comprises a lead frame 201, metal material layers 25, an IC chip 27, insulating filling materials 23, bonding materials 26, metal conductors 28 and plastic package materials 29, wherein the lead frame comprises a chip carrier 202 and a plurality of leads 203 arranged in multiple circles around the chip carrier; the metal material layers are arranged on the upper and lower surfaces of the lead frame; the IC chip is arranged on a metal material layer on the upper surface of the lead frame; the insulating filling materials are arranged below stepped structures 22b of the lead frame; the bonding materials are arranged between the IC chip and the metal material layer on the upper surface of the lead frame; the IC chip is connected to the inner leads of the multiple circles of leads and the upper surface of the chip carrier respectively by the metal conductors; the plastic package materials wrap and seal the IC chip, the bonding materials, the metal conductors, partial regions of the lead frame and partial metal material layers; and the chip carrier and the outer leads exposed out of the bottom surface of a package structure, are provided with raised parts. The package and the manufacturing method have the following beneficial effects: the bottleneck of low I/O quantity is broken through and the package reliability is improved.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field, refer more particularly to and have the encapsulation of high density four limit flat non-pins, the present invention also comprises the manufacturing approach of this packaging part.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization; Portable; Ultra-thinization, multimedization and satisfy popular needed low-cost direction and develop, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA; Kuai Sufazhan novel encapsulated technology in recent years; I.e. four limit flat non-pin QFN (Quad Flat Non-lead Package) encapsulation; Because have good hot property and electrical property, size is little, cost is low and numerous advantages such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively the structure of the conventional rear schematic QFN package along
a schematic cross section taken along the QFN package structure comprises a lead frame 11, a plastic material 12, adhesive sheet material 13, IC chip 14, a metal wire 15, wherein the lead frame 11 includes a chip carrier 111 and 111 around the perimeter array chip carrier pin 112, IC chip 14 through the adhesive sheet material 13 is fixed on the chip carrier 111, IC chips 13 are arranged with the surrounding pin 112 are electrically connected to metal wires 15, plastic material 12 to the IC chip 14, a metal wire 15 and the lead frame 11 is encapsulated in order to protect and support the role of pin 112 exposed on the bottom surface of plastic material 12, such as the PCB by soldering the circuit board with the outside in order to achieve electrical connection.The exposed chip carrier in bottom surface 111 is welded on through scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.Compare with traditional T SOP and SOIC encapsulation, the QFN encapsulation does not have gull wing lead-in wire, and conductive path is short, and coefficient of self-inductance and impedance are low, thereby good electrical properties can be provided, and can satisfy at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
Along with the raising of IC integrated level and the continuous enhancing of function; The I/O number of IC increases thereupon; The also corresponding increase of I/O number of pins of corresponding Electronic Packaging; But four traditional limit flat non-pin packaging parts; The pin of individual pen is periphery around chip carrier and arranges; Limited the raising of I/O quantity, do not satisfied high density, have the needs of the IC of more I/O numbers.Traditional lead frame does not have the staircase structural model design; Can't effectively pin plastic material; Cause lead frame and capsulation material bond strength low; Be easy to cause the layering of lead frame and capsulation material even coming off of pin or chip carrier; And can't effectively stop moisture to be diffused into Electronic Packaging inside, thereby had a strong impact on the reliability of packaging body along lead frame and capsulation material combination interface.The chip carrier of traditional Q FN product does not have certain bossing with outer pin; The area coverage of scolder is limited when surface mount; And the thinner thickness of scolder; Cause the fatigue life of plate level encapsulation shorter; And thin weld layer is because the thermal strain that thermal mismatching causes is bigger; Cause fracture, the layering of weld layer to be lost efficacy easily, influenced the reliability of weld layer.Traditional Q FN product needs in advance at the lead frame back side Continuous pressing device for stereo-pattern to treat also need remove cleanings such as adhesive tape, plastic packaging material overlap behind the plastic packaging to prevent the flash phenomenon when plastic package process, has increased packaging cost and has increased.Use four traditional limit flat non-pin packaging parts of cutter cutting and separating; Cutter also can cut to the lead frame metal in the cutting capsulation material; Not only can cause the reduction and the shortening in cutting blade life-span of cutting efficiency; And can produce metallic bur power, influenced the reliability of packaging body.Therefore, for the bottleneck of the low I/O quantity that breaks through traditional Q FN, the reliability that improves packaging body with reduce packaging cost, be badly in need of the QFN encapsulation and the manufacturing approach thereof of a kind of high reliability of research and development, low cost, high I/O density.
Summary of the invention
The invention provides a kind of high density, enclose the QFN encapsulation and the manufacturing approach thereof of pin arrangements, more with the purpose of bottleneck that reaches the low I/O quantity that breaks through traditional Q FN and the reliability that improves packaging body.
To achieve these goals, the present invention adopts following technical proposals:
The present invention proposes a kind of high density four limit flat non-pin package structures, comprises lead frame, metal material layer, IC chip, insulation filling material, adhesive material, plain conductor and capsulation material.Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface.Lead frame comprises chip carrier and a plurality of pin that is many circle arrangements around chip carrier.Chip carrier is disposed at the lead frame central part, the rectangular shape of shape of cross section, and edge, chip carrier four limit has staircase structural model along thickness direction.To be the shape of cross section that encloses the pin of arranging around chip carrier rounded or rectangular-shaped more, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface.Metal material layer is disposed at the upper surface position and the lower surface position of lead frame.The IC chip configuration is in the metal material layer position of lead frame upper surface, and is disposed at the central part of chip carrier.Insulation filling material is disposed under the staircase structural model of lead frame, supports, protects lead frame.Adhesive material is disposed in the middle of the metal material layer of IC chip and lead frame upper surface, and fixedly the IC chip is on chip carrier.A plurality of bonding welding pads on the IC chip are connected to a plurality of interior pins and the upper surface that disposes the chip carrier of metal material layer that dispose metal material layer through plain conductor, to realize electrical interconnection.Capsulation material coats sealing IC chip, adhesive material, plain conductor, lead frame subregion and part metals material layer, exposes the metal material layer that is disposed at the lead frame lower surface.The chip carrier that disposes metal material layer that exposes the package structure bottom surface has bossing with outer pin.
According to embodiments of the invention, nead frame has a plurality of pins that are three circle arrangements around chip carrier.
According to embodiments of the invention, comprise chip carrier and be three lead frames that enclose the pin of arranging to have staircase structural model around chip carrier.
According to embodiments of the invention, be the rounded shape of shape of cross section of the pin of three circle arrangements around chip carrier.
According to embodiments of the invention, be the shape of cross section rectangular shaped of the pin of three circle arrangements around chip carrier.
According to embodiments of the invention, the pin arrangements mode on the every limit of chip carrier is for being arranged in parallel.
According to embodiments of the invention, the pin arrangements mode on the every limit of chip carrier is for being staggered.
According to embodiments of the invention, lead frame upper surface and lower surface dispose metal material layer.
According to embodiments of the invention, the metal material layer of lead frame upper surface and lower surface configuration comprises nickel (Ni), palladium (Pd), gold (Au) metal material.
According to embodiments of the invention, the chip carrier that disposes metal material layer exposes the package structure bottom surface with outer pin, and has certain bossing.
According to embodiments of the invention, with adhesive materials such as the epoxy resin of argentiferous particle or adhesive tapes with the IC chip configuration in the chip carrier central part.
According to embodiments of the invention, the lead frame staircase structural model is the configuration insulation filling material down.
According to embodiments of the invention, lead frame staircase structural model configuration insulation filling material kind down is the thermosetting capsulation material, perhaps materials such as plug socket resin, printing ink and resistance weldering green oil.
According to embodiments of the invention, the peripheral position of chip carrier is connected to the bonding welding pad on the chip as the ground area through plain conductor.
The present invention proposes a kind of high density four limit flat non-pin packaging part manufacture methods, may further comprise the steps:
Step 1: configuration mask material layer
The thin plate base material is cleaned and preliminary treatment, at the upper surface and the lower surface configuration mask material layer pattern of thin plate base material.
Step 2: form the etching window
Mask material layer to being disposed at thin plate base material lower surface carries out exposure imaging, forms the etching window.
Step 3: the lower surface selectivity is partially-etched
As resist layer, it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove with mask material layer with etching window.
Step 4: remove the mask material layer
Remove the mask material layer that is disposed at thin plate base material lower surface with chemical treatment method or mechanical means.
Step 5: configuration insulation filling material
At thin plate base material lower surface fill insulant in the groove of the partially-etched formation of selectivity.
Step 6: form the etching window
Mask material layer to thin plate base material upper surface carries out exposure imaging, forms the etching window.
Step 7: the upper surface selectivity is partially-etched
As resist layer, it is partially-etched that thin plate base material upper surface is carried out selectivity, forms the lead frame with staircase structural model, comprises the chip carrier and many circle pins of separation with mask material layer with etching window.
Step 8: remove the mask material layer
Remove the mask material layer that is disposed at thin plate base material lower surface with chemical treatment method or mechanical means.
Step 9: configuration metal material layer
Upper surface, lower surface configuration metal material layer at the lead frame that forms.
Step 10: configuration IC chip
Adhesive materials such as epoxy resin resin through the argentiferous particle or adhesive tape with the IC chip configuration in the chip carrier central part.
Step 11: the plain conductor bonding connects
A plurality of bonding welding pads on the IC chip are connected to a plurality of interior pins that dispose metal material layer and dispose on the chip carrier of metal material layer through plain conductor, to realize electrical interconnection and ground connection.
Step 12: plastic packaging
Coat sealing IC chip, adhesive material, plain conductor, part lead frame and part metals material layer with capsulation material.
Step 13: solidify the back
Carrying out the back according to the back solidifying requirements of selected capsulation material solidifies.
Step 14: print
Product array behind the plastic packaging is carried out laser printing.
Step 15: cutting and separating product
The cutting and separating product forms independently single package.
According to embodiments of the invention, through chemical plating method configuration metal material layer.
According to embodiments of the invention, as resist layer, select for use the etching solution of etched sheet base material only partially-etched to thin plate base material upper surface and lower surface selectivity with the mask material layer.
According to embodiments of the invention, insulation filling material is configured in through methods such as silk screen printing or coatings and etches partially in the groove.
According to embodiments of the invention, select method cutting and separating products such as blade cuts, laser cutting or the cutting of water cutter for use, and only cut capsulation material and insulation filling material, not the cutting lead framework.
Based on above-mentioned; According to the present invention; High density four limit flat non-pin encapsulation have the pin that multi-turn is arranged; Therefore has high I/O density; The staircase structural model of lead frame has increased the bonded area with capsulation material and insulation filling material; Has the effect that locks each other with capsulation material and insulation filling material; Can effectively prevent the lead frame and the layering of capsulation material and insulation filling material and coming off of pin or chip carrier; Effectively stop moisture from the package structure outside to diffusion inside; The generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount; The metal material layer of lead frame upper surface and lower surface configuration can effectively improve metal lead wire bonding quality and surface mount quality; Have the chip carrier of certain bossing and outer pin has increased scolder when surface mount wetted area; And the thickness of scolder; Increased the fatigue life of plate level encapsulation; Increased the bond strength of chip carrier simultaneously with outer pin and scolder; Alleviated the thermal strain that causes by thermal mismatching; Owing to only link to each other with insulation filling material between the single packaging body by capsulation material; Therefore when using cutter cutting and separating product; Can not cut to the lead frame metal material; Thereby improved cutting efficiency; Prolonged the life-span of cutter; Prevented the generation of metallic bur power; Saved simultaneously and removed technologies such as glued membrane and plastic packaging material overlap after glued membrane, plastic packaging are pasted in the lead frame back side before the plastic packaging in the traditional Q FN encapsulation flow process, reduced packaging cost.
Hereinafter special act embodiment, and conjunction with figs. elaborates to above-mentioned feature and advantage of the present invention.
Description of drawings
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B Figure 1A along the
a schematic cross-sectional profiles;
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high density QFN encapsulating structure that is arranged in parallel;
Fig. 2 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high density QFN encapsulating structure that is arranged in parallel;
Fig. 3 A is circle according to the pin cross section that embodiments of the invention are drawn, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered high density QFN encapsulating structure;
Fig. 3 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered high density QFN encapsulating structure;
Fig. 4 is the generalized section along the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 5 A to Fig. 5 N is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of the high density QFN encapsulating structure of embodiments of the invention drafting.
Label among the figure: 100. traditional four limit flat non-leaded packages, 11. nead frames, 111. chip carriers; 112. pin, 12. capsulation materials, 13. bonding die materials; 14.IC chip, 15. plain conductors, 200; 200a; 200b; 200c; 200d. high density four limit flat non-pin package structures; 201. lead frame; 202. chip carrier, 203. pins, 20. thin plate base materials; 20a. thin plate base material upper surface; The lead frame upper surface; 20b. thin plate base material lower surface; The lead frame lower surface, 21a; 21b. the mask material layer, 22. grooves; 22a. staircase structural model is surperficial; 22b. staircase structural model, 23. insulation filling materials, 23a. insulation filling material surface; 24; 25. metal material layer; 24a; 25a. the metal material laminar surface, 26. adhesive materials, 27.IC chip; 28. plain conductor, 29. capsulation materials.
Embodiment
Below in conjunction with accompanying drawing the present invention is elaborated:
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high density QFN encapsulating structure that is arranged in parallel.Fig. 2 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high density QFN encapsulating structure that is arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 A-B; In the present embodiment; The lead frame 201 of high density QFN encapsulating structure 200a and 200b comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; And the arrangement mode of the pin 203 on chip carrier 202 every limits is for being arranged in parallel; Dispose metal material layer 25 at lead frame 201 lower surfaces, in lead frame 201, dispose insulation filling material 23.Difference is pin cross section in the high density four limit flat non-pin package structures of Fig. 2 A for circular, and the pin cross section in the high density four limit flat non-pin package structures of Fig. 2 B is a rectangle.
Fig. 3 A is circle according to the pin cross section that embodiments of the invention are drawn, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered high density QFN encapsulating structure.Fig. 3 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered high density QFN encapsulating structure.
Can find out with reference to above-mentioned Fig. 3 A-B; In the present embodiment; The lead frame 201 of high density QFN encapsulating structure 200c and 200d comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; And the arrangement mode of the pin 203 on chip carrier 202 every limits is for being staggered; Dispose metal material layer 25 at lead frame 201 lower surfaces, in lead frame 201, dispose insulation filling material 23.Difference is pin cross section in the high density four limit flat non-pin package structures of Fig. 3 A for circular, and the pin cross section in the high density four limit flat non-pin package structures of Fig. 3 B is a rectangle.
Fig. 4 is the generalized section along the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 4; In the present embodiment, high density QFN encapsulating structure 200 comprises lead frame 201, insulation filling material 23, metal material layer 24, metal material layer 25, adhesive material 26, IC chip 27, plain conductor 28 and capsulation material 29.
In the present embodiment; Lead frame 201 is as the passage of conduction, heat radiation, connection external circuit; Have staircase structural model 22b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 22a of staircase structural model 22b.Lead frame 201 comprises chip carrier 202 and is the pins 203 that many circles are arranged around chip carrier 202, chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and all have staircase structural model 22b.Chip carrier 202 is disposed at lead frame 201 central parts, the rectangular shape of its shape of cross section, and edge, chip carrier 202 4 limit has staircase structural model 22b along thickness direction.A plurality of pins 203 are disposed at around the chip carrier 202; Being many circles around chip carrier 202 arranges; And has ledge structure 22b along thickness direction; Its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
To describe a kind of manufacturing process of high density four limit flat non-pin packaging parts with Fig. 5 A to Fig. 5 N in detail below.
Fig. 5 A to Fig. 5 N is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of the high density QFN encapsulating structure of embodiments of the invention drafting.
Please with reference to Fig. 5 A; Provide to have upper surface 20a and with respect to the thin plate base material 20 of the lower surface 20b of upper surface 20a, the material of thin plate base material 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to the metal material of making lead frame.The thickness range of thin plate base material 20 is 0.1mm-0.25mm, for example is 0.127mm, 0.152mm, 0.203mm.Upper surface 20a and lower surface 20b to thin plate base material 20 clean and preliminary treatment, for example use plasma water degreasing, dust etc., with the upper surface 20a of realization thin plate base material 20 and the purpose of lower surface 20b cleaning.
Please with reference to Fig. 5 B; On the upper surface 20a of thin plate base material 20 and lower surface 20b, dispose mask material layer 21a and mask material layer 21b respectively, mask material layer 21a and mask material layer 21b require to combine firmly have thermal stability with thin plate base material 20; As the erosion resistant layer, has etch-resistance.Mask material layer 21a and mask material layer 21b can make through on the upper surface 20a of thin plate base material 20 and lower surface 20b, being coated with chemical photosensitive materials such as wet film respectively; Coating process can be curtain coating, roller coating and spraying etc., perhaps on the upper surface 20a of thin plate base material 20 and lower surface 20b, pastes chemical photosensitive material such as photic dry film respectively and makes.
Please with reference to Fig. 5 C; Mask material layer 21b on the thin plate base material lower surface 20b carries out exposure imaging technology; Form the etching window; Etching window described here is meant after exposure imaging technology not by the subregion of the thin plate base material 20 of mask material layer 21b covering; Will be in the processing step of back to not carried out etching by the subregion of the thin plate base material 20 of mask material layer 21b covering, mask material layer 21b protection is not etched by the zone of the thin plate base material 20 of its covering.Mask material layer 21b on the thin plate base material lower surface 20b is exposed under certain light source; Like ultraviolet light, electron beam or X-ray; Utilize the light sensitive characteristic of chemical photosensitive materials such as photic wet film and photic dry film; Photic wet film or photic dry film are optionally made public; Mask plate patterns is duplicated on photic wet film or the photic dry film the final mask material layer 21b that on thin plate base material lower surface 20b, form after using developer solution to carry out developing process with etching window.
Please with reference to Fig. 5 D; With the mask material layer 21b that have the etching window on the thin plate base material lower surface 20b as etched resist layer; Select the only etching solution of etched sheet base material 20 for use; It is partially-etched to adopt the spray mode that thin plate base material 20 lower surface 20b are carried out selectivity; Form groove 22 and staircase structural model surface 22a, the etch depth scope can be the 40%-90% that accounts for the thickness of thin plate base material 20.In the present embodiment; The preferential spray mode that goes up that adopts of spray mode; And can in etching solution, add organic matters; Reducing the lateral erosion effect of etching solution to thin plate base material 20, because mask material layer 21b is the polymeric materials such as wet film or dry film with light sensitive characteristic, acid resistance is alkali resistance not; As etched resist layer; Etching solution is preferentially selected acidic etching liquid, like acid chlorization copper etchant solution, iron chloride etching solution, to reduce the destruction of etching solution to mask material layer 21b.
Please with reference to Fig. 5 E; Mask material layer 21b on the thin plate base material lower surface 20b removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means; Chemical reaction method is an alkaline solution of selecting solubility for use; For example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21b on mode such as spray and the thin plate base material lower surface 20b to carry out chemical reaction; Thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21b removed.
Please with reference to Fig. 5 F, in the groove 22 of the partially-etched formation of selectivity, fill insulation filling material 23 at thin plate base material lower surface 20b, insulation filling material 23 has surperficial 23a, and this surface and thin plate base material lower surface 20b are on the same horizontal plane.In the present embodiment; Insulation filling material 23 can be the thermosetting capsulation material; Plug socket resin; Insulating material such as printing ink and resistance weldering green oil; Insulation filling material 23 has enough acidproof; Alkali resistance; To guarantee that follow-up technology can not damage forming insulation filling material 23; The fill method of insulation filling material 23 can be to be filled in the groove 22 through methods such as injection moulding or silk screen printings; Solidify to form the insulation filling material 23 of suitable hardness after the filling; Need carry out ultraviolet exposure for photocuring insulation filling material 23; Insulation filling material 23 after the sclerosis has certain intensity; Has the effect of mutual locking with thin plate base material 20; Remove too much insulation filling material 23 with mechanical grinding method or chemical treatment method; To eliminate the flash of insulation filling material 23; The surperficial 23a and the thin plate base material lower surface 20b of insulation filling material 23 are on the same horizontal plane; For insulation filling materials 23 such as photosensitive type resistance weldering green oils, remove flash through developing method.
Please with reference to Fig. 5 G; Mask material layer 21a on the thin plate base material upper surface 20a carries out exposure imaging technology; Form the etching window; Etching window described here is meant after exposure imaging technology not by the subregion of the thin plate base material 20 of mask material layer 21a covering; Will be in the processing step of back to not carried out etching by the subregion of the thin plate base material 20 of mask material layer 21a covering, mask material layer 21a protection is not etched by the zone of the thin plate base material 20 of its covering.Mask material layer 21a on the thin plate base material lower surface 20a is exposed under certain light source; Like ultraviolet light, electron beam or X-ray; Utilize the light sensitive characteristic of chemical photosensitive materials such as photic wet film and photic dry film; Photic wet film or photic dry film are optionally made public; Mask plate patterns is duplicated on photic wet film or the photic dry film the final mask material layer 21a that on thin plate base material lower surface 20a, form after using developer solution to carry out developing process with etching window.
Please with reference to Fig. 5 H; With the mask material layer 21a that have the etching window on the thin plate base material upper surface 20a as etched resist layer; Select the only etching solution of etched sheet base material 20 for use; It is partially-etched to adopt the spray mode that thin plate base material 20 upper surface 20a are carried out selectivity; Be etched to staircase structural model surface 22a, expose insulation filling material 23.Form lead frame 201; Lead frame 201 comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; Dispose insulation filling material 23 in the lead frame 201, i.e. chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and be fixed together through insulation filling material 23.In the pin 203 of the separation that after selectivity is partially-etched, forms has pin with outside pin, interior pin is connected to the bonding welding pad of IC chip 27 by plain conductor 28 in follow-up lead key closing process, outer pin is as the passage of connection external circuit.Form staircase structural model 22b, staircase structural model 22b has staircase structural model surface 22a.In the present embodiment; The preferential spray mode that goes up that adopts of the spray mode of etching solution; And can in etching solution, add organic matters; To reduce the lateral erosion effect of etching solution to thin plate base material 20; Because mask material layer 21a is the polymeric materials such as wet film or dry film with light sensitive characteristic; Acid resistance is alkali resistance not; As etched resist layer; Etching solution is preferentially selected acidic etching liquid; Like acid chlorization copper etchant solution, iron chloride etching solution, to reduce the destruction of etching solution to mask material layer 21a.
Please with reference to Fig. 5 I; Mask material layer 21a on the thin plate base material upper surface 20a removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means; Chemical reaction method is an alkaline solution of selecting solubility for use; For example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21a on mode such as spray and the thin plate base material lower surface 20a to carry out chemical reaction; Thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21a removed.
Please with reference to Fig. 5 J; Configuration metal material layer 24 on the upper surface 20a of lead frame 201; Metal material layer 24 has surperficial 24a; Configuration metal material layer 25 on the lower surface 20b of lead frame 201; Metal material layer 25 has surperficial 25a; Metal material layer 24 has the same size size with the interior pin of pin 203, and metal material layer 25 has the same size size with the outer pin of pin 203.The collocation method of metal material layer 24 and metal material layer 25 can be methods such as chemical plating, evaporation, sputter; And can form by the different metallic material; In the present embodiment, preferentially select the collocation method of chemical plating as metal material layer 24 and metal material layer 25.The material of metal material layer 24 and metal material layer 25 can be nickel (Ni); Palladium (Pd); Gold (Au); Silver (Ag); Tin metal material and alloys thereof such as (Sn); In the present embodiment; Metal material layer 24 for example is nickel-palladium-gold plate with metal material layer 25; For metal material layer 24; The gold plate of outside is to guarantee bonding property and the bonding quality of plain conductor 28 on lead frame 201 with middle palladium coating; The nickel coating of the inside is as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction; Blocked up cocrystalization compound influences the reliability in bonding zone; For metal material layer 25; But the gold plate of outside is to guarantee the wettability of scolder at lead frame 201 with middle palladium coating; Improve the quality that packaging body mounts at circuit board upper surfaces such as PCB; The nickel coating of the inside is that blocked up cocrystalization compound influences the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction.
Please with reference to Fig. 5 K; IC chip 27 is disposed at metal material layer 24 positions of lead frame upper surface 20a through adhesive material 26; And be fixed in the central part of chip carrier 202; In the present embodiment; Adhesive material 26 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle; Behind the configuration IC chip 27, need that adhesive material 26 is carried out high-temperature baking and solidify, with the bond strength of enhancing with IC chip 27, metal material layer 24.
Please with reference to Fig. 5 L; A plurality of bonding welding pads on the IC chip 27 are connected to a plurality of interior pins that dispose metal material layer 24 and dispose on the chip carrier 202 of metal material layer 24 through plain conductor 28; To realize electrical interconnection and ground connection; In the present embodiment, plain conductor 28 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please with reference to Fig. 5 M; Adopt injection moulding process; Pass through heat; Use low water absorption; The environment-friendly type plastic closure material 29 of low stress coats sealing IC chip 27; Adhesive material 26; Plain conductor 28; The subregion of lead frame 201 and metal material layer 24; In the present embodiment; Capsulation material 29 can be materials such as thermosetting polymer; The insulation filling material 23 of being filled has the physical property similar with capsulation material 29; Thermal coefficient of expansion for example; To reduce the product failure that causes by thermal mismatching; Improve reliability of products, insulation filling material 23 can be a commaterial with capsulation material 29.Toasting the back behind the plastic packaging solidifies; Capsulation material 29 has mutual lock function with insulation filling material 23 and the lead frame 201 with staircase structural model 22b; Can effectively prevent lead frame 201 and capsulation material 29 and the layering of insulation filling material 23 and coming off of pin 203 or chip carrier 202; And effectively stop moisture to be diffused into package interior along the combination interface of lead frame 201 and capsulation material 29 and insulation filling material 23, improved the reliability of packaging body.The chip carrier that disposes metal material layer 25 exposes the package structure bottom surface with outer pin; And has certain bossing; Increased the wetted area of scolder; And the thickness of scolder; Increased the fatigue life of plate level encapsulation; Increased the bond strength of chip carrier, alleviated the thermal strain that causes by thermal mismatching with outer pin and scolder.After treating that the back is solidified, product array is carried out laser printing.
Please with reference to Fig. 5 N; Cutting high density QFN products of separated array; Thoroughly cutting and separating capsulation material 29 forms single high density QFN packaging part 200 with insulation filling material 23; In the present embodiment; Single product separation method can be methods such as blade cuts, laser cutting or the cutting of water cutter; And only cut capsulation material 29 and insulation filling material 23, cutting lead framework metal material is not only drawn out 2 high density QFN packaging parts 200 after the cutting and separating among Fig. 5 N.
Description to embodiments of the invention is from effectively illustrating and describe the object of the invention; Be not in order to limit the present invention; Those skilled in the art is to be understood that under any: under the condition that does not break away from inventive concept of the present invention and scope, can change the foregoing description.So the present invention is not limited to the specific embodiment that disclosed, but cover defined essence of the present invention of claim and the interior modification of scope.
Claims (10)
1. high density four limit flat non-pin package structures is characterized in that comprising:
Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and wherein lead frame comprises chip carrier, a plurality of pin:
Chip carrier is disposed at the lead frame central part, the rectangular shape of shape of cross section, and edge, chip carrier four limit has staircase structural model along thickness direction, and
A plurality of pins are disposed at around the chip carrier, are many circles around chip carrier and arrange, and have staircase structural model along thickness direction, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
Metal material layer is disposed at the upper surface and the lower surface position of lead frame;
The IC chip is disposed on the metal material layer of lead frame upper surface position, and is disposed at the central part of chip carrier;
Insulation filling material is disposed under the staircase structural model of lead frame;
Adhesive material is disposed in the middle of the metal material layer of IC chip and lead frame upper surface, and fixedly the IC chip is on chip carrier;
Plain conductor, a plurality of bonding welding pads on the IC chip are connected to a plurality of interior pins and the upper surface that disposes the chip carrier of metal material layer that dispose metal material layer respectively through plain conductor;
Capsulation material coats the subregion and the part metals material layer that seal above-mentioned IC chip, adhesive material, plain conductor, lead frame, exposes the metal material layer that is disposed at the lead frame lower surface.
2. according to the said a kind of high density four limit flat non-pin package structures of claim 1, it is characterized in that above-mentioned lead frame has a plurality of chip carriers that center on and is the pins that many circles are arranged, the arrangement number of turns is individual pen, Shuan Quan, more than three circles or three enclose.
3. a kind of many circle pin arrangements four limit flat non-pin package structures according to claim 1 is characterized in that enclose the pin shape of cross section is circle or rectangle more.
4. a kind of high density four limit flat non-pin package structures according to claim 1 is characterized in that many circles pin arrangements mode on the every limit of chip carrier is for being arranged in parallel or being staggered.
5. a kind of high density four limit flat non-pin package structures according to claim 1 is characterized in that, the chip carrier with metal material layer exposes the package structure bottom surface with outer pin, and has bossing.
6. the manufacturing approach of a kind of high density four limit flat non-pin package structures according to claim 1 is characterized in that comprising:
Configuration mask material layer is at the upper surface and the lower surface configuration mask material layer of thin plate base material;
Form the etching window, the mask material layer of thin plate base material lower surface is carried out exposure imaging technology, form the etching window;
The lower surface selectivity is partially-etched, and as resist layer, it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove with mask material layer with etching window;
Remove the mask material layer that is disposed at thin plate base material lower surface;
The configuration insulation filling material is at thin plate base material lower surface fill insulant in the groove of the partially-etched formation of selectivity;
Form the etching window, the mask material layer of thin plate base material upper surface is carried out exposure imaging, form the etching window;
The upper surface selectivity is partially-etched, and as resist layer, it is partially-etched that thin plate base material upper surface is carried out selectivity, forms the lead frame with staircase structural model, comprises the chip carrier and many circle pins of separation with mask material layer with etching window;
Remove the mask material layer, remove the mask material layer that is disposed at thin plate base material upper surface;
The configuration metal material layer is at upper surface, the lower surface configuration metal material layer of the lead frame that forms;
Configuration IC chip with the metal material layer position of IC chip configuration in the lead frame upper surface, and is fixed in the central part of chip carrier through adhesive material;
The plain conductor bonding connects, and a plurality of bonding welding pads on the IC chip are connected to a plurality of interior pins that dispose metal material layer respectively and dispose on the chip carrier of metal material layer through plain conductor;
Form plastic-sealed body, coat sealing IC chip, adhesive material, plain conductor, lead frame subregion and part metals material layer, toast the back behind the plastic packaging and solidify with capsulation material;
Cutting and separating forms single package, and cutting and separating forms independently single package.
7. method according to claim 6 is characterized in that, above-mentioned configuration has the mask material layer of window, through being coated with photic wet film or pasting photic dry film, makes forming through photosensitive imaging.
8. method according to claim 6 is characterized in that, lead frame is to be resist layer with the mask material layer, and thin plate base material upper surface and the partially-etched making of lower surface selectivity are formed.
9. method according to claim 6 is characterized in that, the chip carrier of the separation that forms through this etching is connected by insulation filling material with many circle pins to be fixed.
10. method according to claim 6 is characterized in that, cutting and separating forms single package, is with blade cuts, laser cutting or the cutting of water cutter cutting method, and only cuts capsulation material and insulation filling material.
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| CN201110344522XA CN102354691B (en) | 2011-11-04 | 2011-11-04 | Quad flat non-lead (QFN) package with high density and manufacturing method |
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| CN201110344522XA CN102354691B (en) | 2011-11-04 | 2011-11-04 | Quad flat non-lead (QFN) package with high density and manufacturing method |
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| CN102354691B (en) | 2013-11-06 |
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