CN102364877A - Field programmable gate array (FPGA)-based hardware phase discrimination circuit - Google Patents
Field programmable gate array (FPGA)-based hardware phase discrimination circuit Download PDFInfo
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- CN102364877A CN102364877A CN2011103665713A CN201110366571A CN102364877A CN 102364877 A CN102364877 A CN 102364877A CN 2011103665713 A CN2011103665713 A CN 2011103665713A CN 201110366571 A CN201110366571 A CN 201110366571A CN 102364877 A CN102364877 A CN 102364877A
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Abstract
The invention relates to a field programmable gate array (FPGA)-based hardware phase discrimination circuit, which comprises two D triggers, four NAND gates and four NOT gates. All circuit function units are realized by combining FPGA internal logic gates, and can be modified by software programming. The circuit has only one path of output, the path of output comprises a phase difference between two paths of signals and the direction of the phase difference, and the positiveness and negativeness of the direction correspond to the two conditions of signal lead and signal lag. When the lead and lag of the two paths of signals are inconstant, the circuit cannot accurately extract the phase difference of the two paths of signals. However, the lead and the lag can be effectively ensured to be constant by regulating an initial phase difference between the two paths of signals to be equal to 180 degrees, thereby accurately extracting the magnitude and direction of the phase difference between the two paths of signals by utilizing the phase discrimination circuit. The circuit has the advantages of simple structure, ingenious design and high stability; and when used for FPGA application, the circuit provided by the invention can rapidly and accurately discriminate the phase difference between the two paths of signals.
Description
Technical field
The present invention relates to a kind of measuring technique, particularly a kind of hardware phase discriminator based on FPGA.
Background technology
At present, based on the phase discriminator of FPGA two kinds of methods are arranged generally, all adopt two-way output: a kind of is one road outbound course, one tunnel output pulse; Another kind is one tunnel output direct impulse, one tunnel output reverse impulse.The circuit design relative complex, circuit output is not enough to be simplified.
Summary of the invention
The present invention be directed to the frequency multiplier circuit complicated problems of Photoelectric angular position transducer FPGA, proposed a kind of hardware phase discriminator, the phase difference size and Orientation of two paths of signals is exported as one road signal simultaneously, simplify output, optimize circuit based on FPGA.
Technical scheme of the present invention is: a kind of hardware phase discriminator based on FPGA; Comprise four not gates, four NAND gates and two d type flip flops; Two input signal ends are connected to input 1 pin of first not gate and input 1 pin of second not gate respectively; Output 2 pin of first not gate are connected to input 2 pin with second not gate; With output 3 pin of first not gate be connected to respectively with input 1 pin of the 3rd not gate and first d type flip flop put 1 end, 3 pin; Input 1 pin and input end of clock 2 pin of first d type flip flop are held GND with being connected to; Output 4 pin of first d type flip flop be connected to respectively the 3rd not gate input 1 pin and with input 2 pin of the 3rd not gate, put 1 end, 3 pin with output 3 pin of the 3rd not gate are connected to second d type flip flop, input 1 pin and input end of clock 2 pin of second d type flip flop are held GND with being connected to; Output 4 pin of second d type flip flop be connected to respectively the 4th not gate input 1 pin, with input 2 pin and the lead-out terminal EPD of second not gate; Output 2 pin of the 4th not gate are connected to input 1 pin with first not gate, and output 2 pin of second not gate are connected to input 1 pin with second not gate, with output 3 pin of second not gate be connected to respectively first d type flip flop clear terminal 5 pin and with input 2 pin of the 4th not gate; Be connected to output 2 pin of the 3rd not gate with input 1 pin of the 4th not gate, be connected to clear terminal 5 pin of second d type flip flop with output 3 pin of the 4th not gate.
Beneficial effect of the present invention is: the present invention is based on the hardware phase discriminator of FPGA, the phase difference size and Orientation of two paths of signals exported as one road signal, simplify output, have simple in structure, design is ingenious, the advantage of good stability.
Description of drawings
Fig. 1 is the hardware phase discriminator figure that the present invention is based on FPGA.
Embodiment
As shown in Figure 1; A kind of hardware phase discriminator based on FPGA; Input signal terminal PA, PB are connected to the input 1 of not gate A1 and the input 1 of not gate A2 respectively, and the output 2 of not gate A1 is connected to the input 2 of NAND gate B1, the output 3 of NAND gate B1 be connected to respectively NAND gate B3 input 1 and d type flip flop C1 put 1 end 3; Input 1 and the input end of clock 2 of d type flip flop C1 are held GND with being connected to; The output 4 of d type flip flop C1 is connected to the input 1 of not gate A3 and the input 2 of NAND gate B3 respectively, and the output 3 of NAND gate B3 is connected to 1 end 3 of putting of d type flip flop C2, and input 1 and the input end of clock 2 of d type flip flop C2 are held GND with being connected to; The output 4 of d type flip flop C2 is connected to the input 1 of not gate A4, input 2 and the lead-out terminal EPD of NAND gate B2 respectively; The output 2 of not gate A4 is connected to the input 1 of NAND gate B1, and the output 2 of not gate A2 is connected to the input 1 of NAND gate B2, and the output 3 of NAND gate B2 is connected to the clear terminal 5 of d type flip flop C1 and the input 2 of NAND gate B4 respectively; The input 1 of NAND gate B4 is connected to the output 2 of not gate A3, and the output 3 of NAND gate B4 is connected to the clear terminal 5 of d type flip flop C2.
All circuit function unit all have the combination of FPGA internal logic door to realize, and can revise through software programming.Have only one tunnel output, wherein, both comprised the phase difference size of two paths of signals, comprise the phase difference direction again, the leading and two kinds of situation of signal lag of the positive and negative respective signal on the direction.Leading when two paths of signals, when lagging behind not fixedly, this circuit can't accurately extract the phase difference of two paths of signals.But through the first phase potential difference of adjustment two paths of signals, make it to equal 180 degree, it is fixing to guarantee effectively in advance, lag behind, thereby utilizes this phase discriminator accurately to extract the phase difference size and Orientation of two paths of signals.
Claims (1)
1. hardware phase discriminator based on FPGA; It is characterized in that; Comprise four not gates, four NAND gates and two d type flip flops; Two input signal ends are connected to input 1 pin of first not gate and input 1 pin of second not gate respectively; Output 2 pin of first not gate are connected to input 2 pin with second not gate; With output 3 pin of first not gate be connected to respectively with input 1 pin of the 3rd not gate and first d type flip flop put 1 end, 3 pin, input 1 pin and input end of clock 2 pin of first d type flip flop are held GND with being connected to, output 4 pin of first d type flip flop be connected to respectively the 3rd not gate input 1 pin and with input 2 pin of the 3rd not gate; Put 1 end, 3 pin with output 3 pin of the 3rd not gate are connected to second d type flip flop; Input 1 pin and input end of clock 2 pin of second d type flip flop are held GND with being connected to, output 4 pin of second d type flip flop be connected to respectively input 1 pin of the 4th not gate, with input 2 pin and the lead-out terminal EPD of second not gate, output 2 pin of the 4th not gate are connected to input 1 pin with first not gate; Output 2 pin of second not gate are connected to input 1 pin with second not gate; With output 3 pin of second not gate be connected to respectively first d type flip flop clear terminal 5 pin and with input 2 pin of the 4th not gate, be connected to output 2 pin of the 3rd not gate with input 1 pin of the 4th not gate, be connected to clear terminal 5 pin of second d type flip flop with output 3 pin of the 4th not gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110366571 CN102364877B (en) | 2011-11-18 | 2011-11-18 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
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| CN 201110366571 CN102364877B (en) | 2011-11-18 | 2011-11-18 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
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| CN102364877A true CN102364877A (en) | 2012-02-29 |
| CN102364877B CN102364877B (en) | 2013-08-28 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3599102A (en) * | 1970-01-26 | 1971-08-10 | Cincinnati Milacron Inc | Digital phase detector |
| US3714463A (en) * | 1971-01-04 | 1973-01-30 | Motorola Inc | Digital frequency and/or phase detector charge pump |
| CN1345123A (en) * | 2001-09-07 | 2002-04-17 | 清华大学 | Signal phase discriminating method in state transferring sequential logic |
| CN1146112C (en) * | 1999-11-26 | 2004-04-14 | 华为技术有限公司 | Reliable clock phase detecting logic circuit |
| KR20100054582A (en) * | 2008-11-14 | 2010-05-25 | 주식회사 동부하이텍 | Phase detector |
| CN202309650U (en) * | 2011-11-18 | 2012-07-04 | 中国船舶重工集团公司第七0四研究所 | Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) |
-
2011
- 2011-11-18 CN CN 201110366571 patent/CN102364877B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3599102A (en) * | 1970-01-26 | 1971-08-10 | Cincinnati Milacron Inc | Digital phase detector |
| US3714463A (en) * | 1971-01-04 | 1973-01-30 | Motorola Inc | Digital frequency and/or phase detector charge pump |
| CN1146112C (en) * | 1999-11-26 | 2004-04-14 | 华为技术有限公司 | Reliable clock phase detecting logic circuit |
| CN1345123A (en) * | 2001-09-07 | 2002-04-17 | 清华大学 | Signal phase discriminating method in state transferring sequential logic |
| KR20100054582A (en) * | 2008-11-14 | 2010-05-25 | 주식회사 동부하이텍 | Phase detector |
| CN202309650U (en) * | 2011-11-18 | 2012-07-04 | 中国船舶重工集团公司第七0四研究所 | Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) |
Non-Patent Citations (1)
| Title |
|---|
| 倪昔东，胡巍: "基于MSP430的热量表流量测量设计", 《机电设备》, no. 3, 31 March 2007 (2007-03-31), pages 19 - 21 * |
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