CN102386182A - Device and method for integration of sense FET into discrete power MOSFET - Google Patents
Device and method for integration of sense FET into discrete power MOSFET Download PDFInfo
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- CN102386182A CN102386182A CN2011102000411A CN201110200041A CN102386182A CN 102386182 A CN102386182 A CN 102386182A CN 2011102000411 A CN2011102000411 A CN 2011102000411A CN 201110200041 A CN201110200041 A CN 201110200041A CN 102386182 A CN102386182 A CN 102386182A
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Abstract
The invention relates to a power device for integration of one or more sense main field effect transistors (FET) into a discrete power MOSFET and a preparation method thereof under the condition of no increase of mask layers or numbers of preparation technological procedures. The semiconductor device includes an FET and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.
Description
Technical field
Embodiments of the invention relate generally to semiconductor device, or rather, are about comprising sensing metal-oxide-semiconductor field effect transistor that MOS field effect tube and one or more has common gate and drain electrode end and discrete source terminal at interior semiconductor device.
Background technology
In circuit, confirm that flow through one of the method for load of electric current just is to use metal oxide semiconductor field effect tube (metal-oxide-semiconductor field effect transistor), is used for current sense.Traditional current sense MOS field effect tube comprises thousands of the transistor units that are connected in parallel usually, shares common drain, source electrode and gate electrode.Each transistor unit or element in the device all are identical, and the electric current of device drain end is also identical between them.Situation common in this design is that wherein some transistorized source electrode separates with remaining source electrode, is connected on the source terminal of a separation.Therefore, the current sense metal-oxide-semiconductor field effect transistor that is produced can be regarded the transistor that is equivalent to two or more parallel connections as, has common gate and drain electrode end, and discrete source terminal.First in these transistors comprises the most transistor unit in the current sense MOS field effect tube, is commonly referred to home court effect pipe.Second portion comprises a plurality of transistor units with discrete source terminal, is called the sensing FET.
In use; The sensing FET only conducts the sub-fraction electric current on the common drain end; This sub-fraction electric current is inversely proportional to than n with sensing, and wherein n is a current ratio, depends on the ratio of the transistor unit quantity in transistor unit quantity and the sensing FET in the effect pipe of home court.The definition sensing is to conduct for the source terminal that makes sensing FET and home court effect pipe remains under the same electromotive force than n.When sensing when known; The flow through total current of device; And the load current in the load that device connected, can calculate through measuring source current on the sensing FET (promptly between drain electrode and source electrode, the electric current of the current path of the sensing of flowing through FET).
U.S. Patent number is that 5,079,456 patent has proposed a kind ofly to be used for measuring also/or the method and apparatus of the current class of control sensing FET, and wherein the sensing FET contains a power transistor and a sensing transistor.With these two transistor biasings, work under linear model, the source electrode of sensing transistor-drain voltage V
Ds, with the preset that part of V of power transistor
DsMake comparisons.The control signal that is produced is represented the result of comparison, and in one embodiment, this control signal is used in the feedback device, is used for the V with sensing transistor
Ds, be driven into the predetermined fraction V of power transistor
DsTherefore, the grade of the electric current that makes on the sensing transistor to be carried equates with the predetermined fraction of the electric current that is carried on the power transistor.
U.S. Patent number is that 5,408,141 patent has proposed a kind of integrated power device, comprises a power transistor and five sensing transistors.Wherein four sensing transistors are all proportional with power transistor dimensionally, and the utilization preparation process identical with the part of power transistor, are manufactured near the outer peripheral areas of active area of power transistor.The 5th sensing transistor is positioned at the active area inside of power transistor, utilizes second grade of metal interconnection, is connected on the 5th source area that sensing transistor is required, to form the source electrode contact.
U.S. Patent number is 5; 962,912 patent has proposed a kind of power semiconductor part with transistor unit structure, and this part contains a metallic resistance to be followed the trail of; Through a non-conductive layer, with the semiconductor body and the control electrode insulation of power semiconductor part.This resistance is followed the trail of in the horizontal zone between power semiconductor units.Utilize resistance to follow the trail of, the active area of part can not done forr a short time, prepares the metal level of resistance tracking and part simultaneously, and the metal level of part provides with the main electrode of power semiconductor and contacts, and therefore increasing the resistance tracking does not need extra preparation process.
Yet, the performance during the wire-bonded between sensing FET and the home court effect pipe can influence.In addition, under the prerequisite of the quantity that does not increase mask layer and preparation technology's program, be necessary to research and develop a kind of in the MOS field effect tube of a separation power device of integrated one or more sensing FETs.Under this prerequisite, various embodiment of the present invention has been proposed just.
Summary of the invention
The objective of the invention is, under the prerequisite of the quantity that does not increase mask layer and preparation technology's program, provide a kind of in the MOS field effect tube of a separation power device and preparation method thereof of integrated one or more sensing FETs.
Technical scheme of the present invention provides a kind of semiconductor device, comprises:
A home court effect pipe that contains source electrode, body and grid;
A sensing FET that contains source electrode, body and grid, wherein the transistor part of sensing FET is surrounded by the transistor of home court effect pipe, and is positioned near the transistor of home court effect pipe;
A sensing FET source pad that is positioned at the semiconductor device edge place, wherein sensing FET source pad is separated with the transistor part of sensing FET, and through sensing FET probe metal, is connected to the transistor part of sensing FET; And
An electrically insulated structures makes the source electrode of home court effect pipe and the source electrode and the body electric insulation of body and sensing FET,
Wherein home court effect pipe, sensing FET and electrically insulated structures are formed in the independent semiconductor wafer; Make the transistor part of sensing FET and active area that sensing FET source pad is positioned at home court effect pipe outside through the configuration insulation system
Wherein semiconductor device is the vertical field-effect pipe of a separation.
Wherein sensing FET probe metal, home court effect pipe source metal and gate metal all are divided portion in the same independent metal level.
Wherein sensing FET probe metal is not a resistance.
Wherein the transistor part of sensing FET is wide not as sensing FET probe metal.
Wherein the transistor part of sensing FET is positioned near the center of home court effect pipe.
Wherein sensing FET transistor part, sensing FET probe metal and sensing FET source pad are all passed through insulation system, separate with home court effect pipe, and through sensing FET source pad, are positioned at the periphery of home court effect pipe.
Wherein insulation system contains one or more dark potential wells; Be formed on the top of epitaxial loayer; Wherein dark potential well makes the source electrode and the body of sensing FET, and with the source electrode and the body insulation of home court effect pipe, wherein the conduction type of dark potential well is identical with the conduction type in effect tube body district, home court.
Wherein the degree of depth of dark potential well is greater than the degree of depth in effect tube body district, home court.
Wherein the degree of depth of dark potential well is between 1 micron to 2 microns, and the body region depth of home court effect pipe is between 0.5 micron to 0.7 micron.
Wherein the doping content of dark potential well is less than the doping content in effect tube body district, home court.
Wherein the doping content of dark potential well is about 4 * 10
16/ cm
3
The dark potential well between the transistor part of sensing FET and the home court effect pipe wherein is about the width of the transistor unit spacing of twice.
Wherein the dark potential well width between the transistor part of sensing FET and the home court effect pipe is about 2 to 10 microns.
Wherein home court effect pipe and sensing FET are made up of metal oxide semiconductor field effect tube MOSFET.
Wherein the electrically insulated structures between sensing FET and the home court effect pipe is to be made up of near the body ring the insulated trench, and the metal level that one of them is positioned at electric insulation top is electrically connected to the grid of sensing FET the grid of home court effect pipe.
Another technical scheme of the present invention provides a kind of method that is used to prepare the semiconductor device that contains a home court effect pipe and a sensing FET, comprises:
A) in a substrate, source electrode, body and the grid of preparation home court effect pipe;
B) in substrate; Source electrode, body and the grid of preparation sensing FET, wherein the sensing FET is positioned near the center of home court effect pipe, and wherein the transistor part of sensing FET is surrounded by the transistor of home court effect pipe; And be positioned near the transistor of home court effect pipe; To reduce distortion and the error that the sensing FET is measured, wherein sensing FET and home court effect pipe are the vertical field-effect pipe, share a common substrate;
C) in substrate, prepare an electrically insulated structures, make the source electrode and the body of home court effect pipe, with the source electrode and the body electric insulation of sensing FET; And
D) prepare a sensing FET source pad that is positioned at effect tube edges place, home court, and be connected on the sensing FET through sensing FET probe metal,
Wherein sensing FET and sensing FET source pad through electrically insulated structures, are separated with home court effect pipe.
Described method is wherein a) to d) comprise:
I) above the substrate of heavily doped first conduction type, the epitaxial loayer of one first conduction type of preparation;
Ii) above epitaxial loayer, prepare a dark potential well mask; And
The alloy of second conduction type is implanted, to form dark potential well area, second conduction type and first conductivity type opposite in the iii) top of the epitaxial loayer in the insulation system zone of semiconductor device.
Wherein iii) also comprise the dark potential well area of preparation, make the degree of depth of dark potential well area be about 1 to 2 micron, doping content is about 4 * 10
16/ cm
3
Described method also comprises:
Preparation home court effect tube grid groove, sensing fet gate groove and insulated trench, wherein insulated trench and constitutes a part of described electric insulation between home court effect pipe and sensing FET, and wherein insulated trench does not connect grid voltage;
Above described electrically insulated structures, deposit an insulating barrier; And
Insulating barrier above described electric insulation prepares a metal level, and described metal level is connected to the grid of sensing FET the grid of home court effect pipe.
Wherein said semiconductor device is the vertical field-effect pipe of a separation.
Description of drawings
After detailed description below reading and the following accompanying drawing of reference, other characteristics of the present invention and advantage will be obvious:
Fig. 1 representes according to one embodiment of the present of invention, the plan view from above of this semiconductor device.
Figure 1A representes according to one embodiment of the present of invention, and the plan view from above of semiconductor device is with the expression passivation layer.
Fig. 2 representes semiconductor device shown in Figure 1 generalized section along the B-B line.
Sketch map shown in Fig. 3 A-3D is represented according to one embodiment of the present of invention the vertical view of the optional sensing field-effect tube structure of semiconductor device.
Fig. 4 A-4H representes according to one embodiment of the present of invention, prepares a kind of a series of generalized sections of semiconductor device.
Fig. 5 A representes according to one embodiment of the present of invention, a kind of schematic top plan view that is positioned near the semiconductor device that has sensing FET probe in device center.
The vertical view of the semiconductor device that has passivation layer shown in Fig. 5 B presentation graphs 5A.
The schematic top plan view of the sensing FET probe shown in Fig. 6 A presentation graphs 5A-5B.
Fig. 6 B presentation graphs 6A is along the profile of A-A ' line.
Fig. 6 C presentation graphs 6A is along the profile of B-B ' line.
Semiconductor device shown in Fig. 7 presentation graphs 5A-5B is along the profile of A-A ' line.
Fig. 8 representes the sketch map of the electric current line of master wafer and sensing FET probe.
Fig. 9 and Figure 10 B-B ' a series of generalized sections to the based semiconductor device shown in 16B-B ' expression preparation Fig. 5 A-5B and the 6C along B-B ' line.
Fig. 9 A and Figure 10 C-C ' a series of generalized sections to the based semiconductor device shown in 16C-C ' expression preparation Fig. 5 A-5B and 7 along C-C ' line.
Embodiment
Although in order to explain, below specify and comprised many details, any technical staff of this area should understand based on the multiple variation of following details and revise and belongs to scope of the present invention.Therefore, the proposition of exemplary embodiments of the present invention has no general loss for the invention of asking for protection, and not additional any restriction.
Be appreciated that the various aspects of the embodiment of the invention simultaneously with reference to Fig. 1, Figure 1A and Fig. 2.Fig. 1 representes according to one embodiment of the present of invention, the plan view from above of semiconductor device 100.As shown in Figure 1, semiconductor device 100 comprises a common substrate 101, one and is deposited on home court effect pipe 102 and the one or more sensing FET 104 that also is deposited in the common substrate in the common substrate 101.Shown in the example among Fig. 1, sensing FET 104 can be arranged in by the active area area surrounded of home court effect pipe 102.Home court effect pipe 102 can be metal oxide semiconductor field effect tube (metal-oxide-semiconductor field effect transistor), and normally MOS field effect tube can be configured to striped unit or isolated cell with it.Sensing FET 104 also can be a metal oxide semiconductor field effect tube (metal-oxide-semiconductor field effect transistor), thereby is configured to striped unit or isolated cell.Home court effect pipe 102 all is formed at common substrate 101 with sensing FET 104.Each home court effect pipe 102 all contains separately source electrode, grid and drain electrode structure with sensing FET 104.Source configuration is formed in the body layer of common substrate 101.Drain pad 103 (referring to Fig. 2) is formed on the back of substrate 101.
Constitute the grid and the source configuration of home court effect pipe 102, generally be positioned at the below of home court effect pipe source metal 106.The source configuration of sensing FET 104 is electrically connected on the sensing FET source metal 108.Constitute the grid and the source configuration of sensing FET 104, generally be positioned at the below of a part of sensing FET source metal 108.Yet for fear of the infringement that the wire-bonded effect brings, these structures are not positioned at the below of sensing FET source pad 118 (being also referred to as sensor mat sometimes) usually.Because than the little a plurality of orders of magnitude of quantity of home court effect pipe unit, the therefore this infringement that field sensing effect pipe unit is caused is with the accuracy that greatly influences required sensing ratio usually for the quantity of field sensing effect pipe unit.Though home court effect tube elements also can receive the infringement that the wire-bonded effect is brought, the quantity of impaired home court effect pipe unit is much total littler than home court effect pipe unit, thereby can greatly not influence the accuracy of required sensing ratio.Sensing FET source metal 108 can cover whole sensing FET source area; And extend to the zone outside the active sensor FET unit 104; Sensor mat just is formed directly on the FET source metal 108, or above the passivation layer above the sensing FET source metal 108.For easy, Fig. 1 does not express passivation layer.Figure 1A has provided the vertical view identical with Fig. 1; But expressed the window of being opened in passivation layer 208 and the passivation layer 208; According to one embodiment of the present of invention, this window is used to join to home court effect pipe source metal 106, sensing FET source metal 108 and external gate metal 111.In fact the metal that window exposed in the passivation layer 208 has constituted gate pad 120, home court effect pipe source pad 107 and sensing FET source pad 118.Obviously, sensing FET 104 is not the below that is located immediately at sensing FET source pad 118.
The grid structure of home court effect pipe 102 and sensing FET 104 through a public grid metal 110, is electrically connected to together each other.The first metal crack 112 can be with home court effect pipe source metal 106 and public grid metal 110 electric insulations.The second metal crack 114 can be between public grid metal 110 and sensing FET source metal 108.The 3rd metal crack 115 can be between home court effect pipe source metal 106 and external gate metal 111.Conductor filled groove (Fig. 1 does not express) is formed in the body of substrate 101; And through one deck oxide and the insulated substrate of liner on trenched side-wall; For example through conductor filled groove; Can realize the gate terminal of home court effect pipe 102 and sensing FET 104, with being electrically connected between the public grid metal 110.These conductor filled grooves also couple together public grid metal 110 and external gate metal 111.Home court effect pipe source metal 106, sensing FET source metal 108, external gate metal 111 and public grid metal 110 can be formed at the single patterned metal level that is deposited on substrate 101 tops.Gate pad 120 can be deposited on the external gate metal 111.
Home court effect pipe source metal 106, sensing FET source metal 108, external gate metal 111 and public grid metal 110 can be passivated layer 208 and cover (referring to Figure 1A and Fig. 2).External electric to home court effect pipe source metal 106 connects, and can be connected on the home court effect pipe source pad that is deposited on the passivation layer 208 through the through hole in the passivation layer 208.Also can select, home court effect pipe source pad can be formed at a part of home court effect pipe source metal 106, and home court effect pipe source metal 106 exposes out through the window in the passivation layer 208.Similar with it, the external electric to sensing FET source metal 108 connects, and can pass through passivation layer 208, is connected to sensing FET source metal pad 118 (sensor mats) on the passivation layer that is deposited on sensing FET source metal 108 tops.Also can select, sensing FET source pad 118 can be formed at a part of sensing FET source metal 108, and sensing FET source metal 108 exposes out through the window in the passivation layer 108.Almost the whole surface of home court effect pipe source metal 106 generally all can be used for wire-bonded.In addition,, can pass through passivation layer, be connected to the gate pad 120 on the passivation layer that is deposited on gate metal 110 tops to the external electric connection of gate metal 110.Yet in Fig. 1, Figure 1A and embodiment shown in Figure 2, gate pad 120 is formed at external gate metal 111.Public grid metal 110 and external gate metal 111 through grid slideway groove 222 (Fig. 2), link together below.The drain electrode of home court effect pipe 102 and sensing FET 104 can be electrically connected to a public drain electrode pad 103 (referring to Fig. 2) through the bottom of substrate 101, and public drain electrode pad 103 possibly be formed on the back of common substrate 101.
As shown in Figure 2, home court effect pipe 102 can contain a plurality of field-effect tube structures, and each field-effect tube structure all comprises a grid 202 that has a groove and the part body 201 formed source electrodes 204 through suitable doped substrate 101.The grid 202 of each home court effect tube device is all with the form of groove, and liner has insulators such as oxide, and fills with the polysilicon of conduction.Grid 202 can be perpendicular to the B-B cross section; Pass the trench-gate of the one or more B-B of being parallel to cross sections, be electrically connected on the grid slideway groove 222, grid slideway groove 222 is through insulating barrier 206; Via one or more conductive through holes 203, be electrically connected on the public grid metal 110.Grid slideway groove 222 also is connected on the external gate metal 111.The source electrode 204 of a home court effect pipe unit can pass through a home court effect pipe source metal 106; Be parallel on other this device; Source area 204 can pass insulating barrier 206, through conductive through hole 205, is electrically connected on the home court effect pipe source metal 106.Home court effect pipe source metal 106 can be electrically connected on the effect pipe source pad of home court through passing the conductive through hole of a part of passivation layer 208, and that part of passivation layer 208 is positioned at source pad below, effect pipe source metal 106 tops, home court.Also can select, home court effect pipe source pad can be formed at that part of home court effect pipe source metal 106 of the window covering that is not passivated in the layer 108.Generally allow the almost whole surface of home court effect pipe source metal 106, as the bonding land of bonding wire.
Likewise, sensing FET 104 also contains a plurality of device architectures, and each device architecture all comprises the grid 210 of a with groove, and the grid 210 of with groove is electrically coupled on the grid slideway 224 through one or more vertical gate trenchs.Grid slideway 224 is connected on the public grid metal 110 through through hole 211.From 110 beginnings of public grid metal, via external gate metal 111 and grid slideway 222, grid slideway 224 also is electrically connected on the gate pad 120.Sensing FET source electrode 212, is electrically coupled on other field sensing effect pipe unit source electrodes through through hole 225 via sensing FET source metal 108.The grid 210 of with groove, source electrode 212 and body 221 can dispose with above-mentioned home court effect tube grid 202, source electrode 204 and body 201 described modes.Sensing FET source metal 108 can be electrically connected on the sensing FET source pad (sensor mat) 118 through being formed on the conductive through hole in the passivation layer 208.Also can select, sensor mat is formed at a part of sensing FET source metal 108, and that part of sensing FET source metal 108 exposes out through the window in the passivation layer 208.Public grid metal 110 is the grid slideway 222 of the with groove of home court effect pipe 102, is electrically connected with the grid slideway 224 of the with groove of sensing FET 104.The first metal crack 112 is with home court effect pipe source metal 106 and public grid metal 110 electric insulations, and the second metal crack 114 is with sensing FET source metal 108 and public grid metal 110 electric insulations.
As stated, the source electrode of home court effect pipe and field sensing effect tube device and body all are formed in the same substrate 101.Electrical insulator 122 makes these two source electrodes and body insulation.As an example, electrical insulator 122 possibly contain body implants 207 and electric insulations of ring and the polysilicon filling groove 209 that electricity floats, and between home court effect pipe 102 and sensing FET 104, electric insulation is provided.The preparation body is implanted ring 207 can be through suitably mixing to part substrate 101.The similar of groove 209 is in trench-gate 202,210, but with the trench-gate electric insulation.In order to make home court effect pipe and sensing FET source metal 106 and 108 and public grid metal 110 electric insulations; Passivation layer 208 can be filled in metal crack 112 and 114, and passivation layer 208 is deposited on home court effect pipe source metal 106, sensing FET source metal 108 and public grid metal 110 tops.Also can select, save a part or totally inactivating layer 208, bonding wire directly is connected respectively on home court effect pipe source metal 106, sensing FET source metal 108 and the public grid metal 110.
According to embodiments of the invention, semiconductor device also has multiple different layout.Fig. 3 A-3D representes according to one embodiment of the present of invention, a kind of schematic top plan view of several optional sensing field-effect tube structure of semiconductor device.As an example, semiconductor device 300 possibly contain a sensing FET, and the active area that is positioned at home court effect pipe is inner, shown in Fig. 3 A.Semiconductor device 300 contains a sensing FET 304, is positioned near the center of home court effect pipe 302.The source metal of home court effect pipe 302 and sensing FET 304 FET and corresponding source pad 303 and 308 and gate pad 306 between.Be formed on the slit 305,307 in the common metal layer, common metal layer be divided into the gate metal district and the source metal district of home court effect pipe 302 and sensing FET 304.The source pad 303,308 of home court effect pipe and sensing FET is positioned at top, corresponding metal district.Gate pad 306 is positioned at top, a part of gate metal district.The electrical insulator 309 that dots possibly be formed in the body part of substrate, with a kind of suitable mode, makes the source area electric insulation of home court effect pipe 302 and sensing FET 304.
The a plurality of sensing FETs that have different current ratios can be integrated in the main MOS field effect tube like a cork.Fig. 3 D representes a kind of semiconductor device 310, and it contains two sensing FETs 312 and 314, is positioned near the turning of home court effect pipe 302.The source metal of home court effect pipe and two sensing FETs is between FET and corresponding source pad 311,313,315 and gate pad 317.Be formed on the slit 316,318,319 in the common metal layer, common metal layer be divided into the gate metal district and the source metal district of home court effect pipe and each sensing FET.The source pad 311,313,315 of home court effect pipe and sensing FET is positioned at top, corresponding metal district.Gate pad 317 is positioned at top, a part of gate metal district.The electrical insulator 320 that dots possibly be formed in the body part of substrate, with a kind of suitable mode, makes the source area electric insulation of home court effect pipe and sensing FET.
The semiconductor device of preparation the above-mentioned type also has many diverse ways.As an example, Fig. 4 A-4H representes according to one embodiment of the present of invention, prepares a kind of a series of generalized sections of N-passage metal-oxide-semiconductor field effect transistor semiconductor device.Can use similar technology, preparation P-passage metal-oxide-semiconductor field effect transistor device.Shown in Fig. 4 A, N-epitaxial loayer 404 can be formed on N+ substrate 402 tops.Then, a preparation trench mask (not expressing among the figure) above N-epitaxial loayer 404.Pass through trench mask; N-epitaxial loayer 404 is etched into the preset degree of depth; Form home court effect tube grid groove 403A, home court effect tube grid slideway groove 403B, sensing fet gate groove 405A and sensing fet gate slideway groove 405B and insulated trench 406, shown in Fig. 4 B.Then on the sidewall of groove 403A, 403B, 405A, 405B and 406, grow gate oxide 410.With electric conducting materials such as polysilicon 408 filling grooves 403,405 and 406, and return and carve, shown in Fig. 4 C.According to the method, in public preparation process, can form source terminal, trench-gate and insulated trench simultaneously.
In order to prepare source area and electrical insulator, can implant and the opposite alloy of its doping polarity (being conduction type) epitaxial loayer 404.As an example; Can body mask (not expressing among the figure) be implanted P-type alloy 412, and annealing near the N-epitaxial loayer 404 home court effect tube grid groove 403A, main grid utmost point slideway groove 403B, sensing fet gate groove 405A, sensing fet gate slideway groove 405B and insulated trench 406.Shown in Fig. 4 D, near the P-type alloy 412 the insulated trench 406 constitutes the body ring, and helping provides electric insulation between home court effect pipe and sensing FET.In this way, home court effect pipe and field sensing effect tube device zone and body ring can form in public preparation process simultaneously.Be noted that in this example,, in N-type doped epitaxial layer 404, implant P-type alloy in order to prepare the N-passage device.Also can select, in P-type doped epitaxial layer, implant N-type alloy, with preparation P-passage device.
Shown in Fig. 4 E, implant N+ type alloy, and annealing, with preparation home court effect pipe source area 413 and sensing FET source area 414.Above N-epitaxial loayer 404, deposit an insulating barrier 416, for example contain the silex glass (BPSG) of boric acid.Shown in Fig. 4 F, return and carve insulating barrier 416, so that above home court effect tube grid slideway groove 403B and sensing fet gate slideway groove 405B, form contact openings 417 and 418 respectively; And form the contact openings 430 and 431 of home court effect pipe source electrode and sensing FET source electrode respectively.Can pass contact openings 430 and 431, implant contact implant 432,434.
In the contact openings 417,418,430 and 431 of conductive layer deposition above insulating barrier 416; Form pattern, to process public grid metal 420 (being electrically connected to home court effect tube grid slideway groove 403B and sensing fet gate slideway groove 405B), home court effect pipe source metal 421 and sensing FET source metal 422.Shown in Fig. 4 G, return and carve conductive layer, form opening 423, so that make insulation between public grid metal 420 and the home court effect pipe source metal 421, and form opening 424, so that make insulation between public grid metal 420 and the sensing FET source metal 422.At last, shown in Fig. 4 H, deposit passivation layer 426 is in opening 423,424 and above public grid metal 420, home court effect pipe source metal 421 and sensing FET source metal 422.
Method shown in Fig. 4 A-4H only is illustrated in preparation N-passage home court effect pipe and sensing FET on the common substrate, and the sensing FET is not below sensing FET source pad.Yet, utilize this method, need not to use extra preparation process and extra mask layer, just can be on a common substrate that has a home court effect pipe easily preparation have a plurality of sensing FETs of multiple different current ratios.Embodiments of the invention make home court effect pipe, sensing FET and the electric insulation between them, can in public preparation process, be formed on on the semi-conductive substrate.Although according to embodiments of the invention, the used process characteristic of fabricate devices is all very common with order, the mask that is used to prepare electric insulation and FET device in the preparation process is different.
According to an optional embodiment of the present invention, can in the effect pipe of home court, be formed centrally a sensing FET probe, because the minimizing of the conduction current around the probe, thereby make the current ratio of home court effect pipe accurate more and stable.This current ratio is the important parameter of Current Regulation.The connection of sensing FET probe is to realize through a sensor mat that is positioned at discrete MOS field effect tube Waffer edge.This integrated extra mask layer that do not need or not extra preparation process yet.This integrated sensing FET probe will be shared identical gate terminal and identical drain electrode end with home court effect pipe, but source terminal but separates with home court effect pipe.
Shown in Fig. 5 A-5B and Fig. 6 A-6C, in the structure of semiconductor device 500, except sensing FET probe is positioned at effect tube hub place, home court, outside sensing FET source pad, other all with the similar of the semiconductor device 300 shown in Fig. 3 A.Semiconductor device 500 comprises a home court effect pipe that is positioned at semiconductor wafer 501 tops, and a sensing FET probe 510 that is positioned at effect pipe 502 centers, home court.Sensing FET probe 510 comprises one or more sensing field-effect tube structures that are formed between the field-effect tube structure, and these field-effect tube structures constitute home court effect pipe.Sensing FET source pad 503 is positioned near the edge of semiconductor device 500, away from sensing FET probe 510.Sensing FET probe 510 is connected on the sensing FET source pad 503 through conductive pin 511, and conductive pin 511 is also referred to as sensing FET probe metal or field sensing effect tube antenna sometimes.Can utilize the metal level identical, preparation sensing FET probe metal 511 with home court effect pipe source metal 508 and gate metal 509.Preferably select high conductive materials such as copper or aluminium for use, preparation sensing FET probe metal 511, and make sensing FET probe metal 511 enough wide, make conductive pin can not become a resistance.Let the sensing FET 510 (being positioned at probe metal 511 belows) can not be wideer or longer than probe metal 511.Sensing FET source pad 503 preferably is positioned at the periphery of device 500, and the position that spatially belongs to away from the sensing FET.The transistor part of sensing FET 510 is around the effect pipe transistor of home court, and major part is all surrounded by home court effect pipe transistor, so that distortion or the difference measured are reduced to minimum.
Through slit 505 and following electrically insulated structures; Sensing FET probe 510, conductive pin 511 and sensing FET source pad 503 all with home court effect pipe 502 electric insulations, this and the above-mentioned electrical insulator 122 that has body cyclization insulated trench shown in Figure 2 are similar.Slit 505 surrounds sensing FET probe 510 with insulation system.As an example, semiconductor device 500 can be the vertical power metal-oxide-semiconductor field effect transistor of a separation.What home court effect pipe 502 was different with integrated circuit (IC) chip is; The IC chip has a plurality of transistors that are not connected in parallel; And have different signals on the transistor; And home court effect pipe 502 is to be made up of a plurality of transistors with public grid signal parallel operation, plays the MOS field effect tube of an independent separation.
Electrical insulator (for example above-mentioned electrical insulator shown in Figure 2 122); Or have gate trench, do not have the zone of source electrode implant; Or dark potential well implant 512; Can be formed on substrate top with a kind of appropriate mode, so that the source electrode of the source electrode of home court effect pipe 502 and body and sensing FET probe 510 and body insulation.The conduction type of dark potential well 512 can be identical with effect tube body district, home court, but doping content is lower, for example is about 4 * 10
16/ cm
3Dark potential well can be darker than effect tube body district, home court, and for example approximately 1-2 micron (μ m) is dark, or more precisely between 1.4 to 2 microns (or being about 1.7 μ m), but can not cross gate trench deeply.As a reference, typically body region depth is about 0.5 to 0.7 μ m.Dark potential well insulation possibly be the width of several times transistor unit spacing, and for example 2 to 10 μ m are wide.The spacing that the width of dark potential well insulation may diminish to a transistor unit is equally little.This depends on the working ability of manufacturing equipment.Sensing FET source metal 608 and home court effect pipe source metal 618 must not short circuit or bridge joints, make them leave enough slits between two, and the size in slit depends on the working ability of manufacturing equipment.
Insulation system around the sensing FET has also stopped active area voltage; Thereby make sensing FET probe 510, conductive pin 511 and sensing FET source pad 503 because slit 505; And being positioned at " outside " of home court effect pipe active area and insulation system, insulation system begins to extend from the edge of active area.Yet, home court effect pipe 502 transistors that sensing FET probe 510 and conductive pin 511 are arranged in sensing FET probe 510 to have minimum distortion.Form the metal level of sensing FET source pad 503, conductive pin 511 and sensing FET probe source metal 608, can be the same with gate metal 509 and home court effect pipe source metal 508.Be noted that conductive pin 511 is not a resistance element.As an example, shown in Fig. 6 A, its width at least can be identical with the sensing FET.
Fig. 5 B representes the vertical view identical with semiconductor device shown in Fig. 5 A 500, and different is in the figure, and passivation layer 533 has covered the entire wafer except that home court effect pipe source pad 508, gate pad 506 and sensing FET source pad 503.Be not passivated the sensing FET probe 510 of layer 533 covering and the position of conductive pin 511, dot.
Shown in Fig. 5 A and 6B, sensing FET probe 510 is positioned at the center of home court effect pipe 502, through slit 505, with home court effect pipe 502 and insulation system 515 insulation.As an example, insulation system 515 possibly contain insulating barrier 516, for example a BPSG.Insulation system possibly also contain dark potential well 512, and dark potential well 512 is formed on the top of N-epitaxial loayer 513, and the below of insulating barrier 516.Dark potential well 512 makes the source electrode and the body of sensing FET probe 510, with 502 insulation of home court effect pipe.The conduction type of dark potential well 512 is identical with body, but it is darker than body.The layout of dark potential well 512 has roughly been followed the layout in the slit 505 shown in Fig. 5 A.Epitaxial deposition is above semiconductor substrate layer 514.
Shown in Fig. 5 A and 6C, conductive pin 511, sensing FET source pad 503 and sensing FET probe 510 all pass through slit 505, with home court effect pipe source pad 508 and insulation system 515 insulation.Dark potential well 512 makes the source electrode and the body of sensing FET probe 510, with the source electrode and the body insulation of home court effect pipe 502.Dark potential well 512 has also improved the puncture in terminator and the insulation system 515, guaranteeing puncturing not at first here (in less relatively termination and insulation layer) generation, thereby has strengthened the durability of device.Dark potential well also can be used as the part of the termination structure that surrounds home court effect pipe (not expressing among the figure), is used in the semiconductor device.
Can dispose insulation system 515; Make sensing FET 510 be positioned at insulation system 515 outsides, (therefore also in the home court " outside " of effect pipe active area) but the transistor part of sensing FET 510 roughly surrounded by the active transistor unit of home court effect pipe 502.In addition, sensing FET 502, probe metal 511 and sensing FET source pad 503 can be positioned at insulation system 515 outsides.Dark potential well 512 also can be positioned at sensing FET source pad 503 (Fig. 7) below, and sensing FET probe metal 511 belows.
Similar with Fig. 2, shown in Fig. 6 C, home court effect pipe 502 can contain a plurality of field-effect tube structures, and each field-effect tube structure all contains the grid 614 of with groove, and by a part of body 616 formed source electrodes 612 of suitable doping N-epitaxial loayer 513.The grid 614 of each home court effect tube device all occurs with the form of groove; The groove liner has insulators such as oxide; And fill with conductive polycrystalline silicon; Grid 614 can be connected on the grid slideway (not expressing among the figure), and the grid slideway is connected to them on the gate metal (not expressing among the figure).Grid 614 can be with vertical along the trench-gate in the A-A cross section.Also can select, grid 614 is parallel with those elements in the A-A cross section, but representes like vertical here, is for the ease of explanation.The source electrode 612 of a home court effect pipe unit can pass through home court effect pipe source metal 618, and is parallelly connected with other these type of devices.Source area 612 can pass through insulating barrier 515, via conductive through hole 620,621, electrically contacts with home court effect pipe source metal 618.Can implant body contactant 610 in through hole 620,621 and 623 bottoms.
Similar with it, sensing FET probe 510 also contains a plurality of device architectures, and each device architecture all contains the grid 622 of a with groove, is electrically coupled to grid slideway (not expressing among the figure).The grid slideway is connected to public grid metal (not expressing among the figure).The grid slideway is electrically connected on the gate pad 506 through external gate metal 509.Sensing FET source electrode 602, is electrically coupled on other field sensing effect pipe units via through hole 626 through sensing FET source metal 608.Can be such with above-mentioned home court effect tube grid 614, source electrode 612 and body 616 said ground, grid 622, source electrode 602 and the body 606 of configuration with groove.
The source electrode and the body of home court effect tube device, and sensing FET probe is formed on the same N-epitaxial loayer 513 that is arranged on (N+) substrate 514.Dark potential well 512 makes the source electrode and the body insulation of these home court effect pipes and sensing FET.
Shown in Fig. 5,6B-6C and 7, gate pad 506, sensing FET source pad 503 and sensing FET probe 510 can be positioned at the active area outside, promptly in the terminator of home court effect pipe 502.Can with gate pad 506, sensing FET source pad 503 and sensing FET probe 510, separate through having the insulation system 515 of sensing FET source pad 503 with home court effect pipe 502.
Referring to Fig. 3 A; Though sensing FET 304 is positioned at the center of home court effect pipe 302; But but in a relatively large source pad 303 (for example 150 microns * 150 microns) below; Be difficult to Control current and propagate, so the current ratio of field sensing effect tube current and home court effect tube current is difficult to control.Through a less relatively sensing FET probe (for example size is about 20 microns * 20 microns) being placed the center of master wafer FET; And through a narrow sensing FET probe conductive pin (such shown in above-mentioned Fig. 5 A-5B); Sensing FET probe is connected on the field sensing effect pipe pad; Control current is propagated at an easy rate, thus obtain suitable current than (for example real sensing than should the sensing ratio of design 5% in).In addition, this design places the sensing FET under the temperature more approaching with home court effect pipe (temperature can influence FET resistance/electric current), to resist the distortion that is brought owing to the temperature difference of bigger sensing FET source pad generation.To the width the sensing FET probe, be about the half the of home court effect pipe width from the edge of home court effect pipe.Be characterized in that home court effect pipe is in shape near being about 1-10mm
2Square or rectangular.
In addition, the temperature difference more also can influence current ratio and R
Ds-onThrough the sensing FET being placed effect tube hub place, home court, and surrounded, make the temperature difference reduction in the middle of home court effect pipe transistor and the sensing FET transistor, the excessive distortion of having avoided sensing FET source pad to bring by home court effect pipe transistor.The a plurality of sensing FET probes that have various different current ratios also can be integrated into the center of home court effect pipe like a cork.
The home court effect pipe 502 of that based semiconductor device shown in Fig. 8 presentation graphs 5A and the generalized section of the electric current line in the sensing FET probe 510.As shown in Figure 8; Because relatively large sensing FET wafer pad (not expressing among the figure) has been moved to the place away from sensing FET probe 510; Spacing in the middle of sensing FET probe and the home court effect pipe is dwindled, and propagates thereby obtain less current.Therefore, can design the R of sensing FET more exactly
Dson, make the sensing FET probe that has minimum distortion obtain required current ratio.
That based semiconductor device shown in Fig. 5 A is used in the striped or isolated cell technology of gate trench MOS field effect tube (comprising shielded gate trench (SGT) or planar gate MOS field effect tube).
Prepare that based semiconductor device shown in above-mentioned Fig. 5 A, also have many diverse ways.As an example, Fig. 9-9A and 10B-B ' prepare Fig. 5 A and Fig. 6 generalized section along that type N-passage metal-oxide-semiconductor field effect transistor semiconductor device shown in B-B ' and the C-C ' line to 16B-B ' and 10C-C ' to 16C-C ' for a series of expressions.(a kind of similar technology can be used for preparing the P-passage device.) compare with the technology shown in Fig. 4 A-4H, this technology does not need extra preparation process and extra mask layer.
As shown in Figure 9, N-epitaxial loayer 904 is formed on N+ substrate 902 tops.Dark potential well mask (not expressing among the figure) is formed on N-epitaxial loayer 904 tops.Shown in Fig. 9 A,, be implanted in the epitaxial loayer 904, to constitute dark potential well 905A with the opposite alloy of doping of polarity (being conduction type) with epitaxial loayer 904.
Then, above N-epitaxial loayer 904, form a trench mask (not expressing among the figure).Shown in Figure 10 B-B ' and 10C-C ', through trench mask, N-epitaxial loayer 904 is etched into predetermined depth, to form home court effect tube grid groove 903, sensing fet gate groove 905 and insulated trench 906.Then, the gate-dielectric (for example oxide) 910 of on the sidewall of groove 903,905 and 906, growing.Shown in Figure 11 B-B ' and 11C-C ',, and return and carve with electric conducting material (for example polysilicon) 908 filling grooves 903,905 and 906.According to the method, in public preparation process, can form source terminal, trench-gate simultaneously.
As an example; Shown in Figure 12 B-B ' and 12C-C ',, implant P-type alloy through body mask (not expressing among the figure); And annealing near the N-epitaxial loayer 904 home court effect tube grid groove 903, sensing fet gate groove 905, to process body 912 and 909.The degree of depth that the degree of depth that body is implanted is implanted less than dark potential well.Be noted that in this example,, in N-type doped epitaxial layer 904, implant P-type alloy, to process body 912 and 909 in order to prepare the N-passage device.Also can select, in P-type doped epitaxial layer, implant N-type alloy, to process the P-passage device.
Shown in Figure 13 B-B ' and 13C-C ', implant N+ type alloy (with regard to n-passage metal-oxide-semiconductor field effect transistor), and annealing, to process home court effect pipe source area 913 and sensing FET source area 914.Above N-epitaxial loayer 904, deposit an insulating barrier 916 (silex glass (BPSG) that for example contains boric acid).Shown in Figure 14 B-B ' and 14C-C ', mask insulating barrier 916 also returns and carves, so that above dark potential well 905A, prepare contact openings 917, and forms the contact openings 930 and 931 of home court effect pipe source electrode and sensing FET source electrode respectively.Body contact implant 932 is implanted in bottom in contact openings 917,930 and 931.
Shown in Figure 15 B-B ' and 15C-C '; Conductive layer deposition is above insulating barrier 916; And in contact openings 917,918,930 and 931, form pattern, and sensing FET source pad 925 with preparation home court effect pipe source metal 921 and sensing FET source metal 922.Shown in Figure 15 B-B ' and 15C-C '; Return and carve conductive layer, form opening 930, make insulation between home court effect pipe source metal 921 and the sensing FET source metal 922; Form opening 932, make insulation between home court effect pipe source metal 921 and the sensing FET source pad 925.At last, shown in Figure 16 B-B ' and 16C-C ', passivation layer 926 is deposited in the opening 930,932, and is deposited on home court effect pipe source metal 921 and sensing FET source metal 922 tops.
As Fig. 9,9A, 10B-B ' to 16B-B ' and 10C-C ' to the described method of 16C-C '; Only be illustrated in preparation N-passage home court effect pipe and sensing FET on the common substrate, and the sensing FET is not positioned at sensing FET source pad below.Yet, utilize the method, need not extra preparation process and extra mask layer, just can on common substrate, process a plurality of sensing FETs that have various different current ratios like a cork.Embodiments of the invention can through same semi-conductive substrate, form home court effect pipe, sensing FET and the electric insulation between them in public preparation process.Although according to embodiments of the invention, the used process characteristic of fabricate devices is all very common with order, the mask that is used to prepare electric insulation and FET device in the preparation process is different.
Although the present invention has done detailed narration about some preferable version, still possibly there are other versions.Therefore, scope of the present invention should be by above-mentioned explanation decision, and in contrast, scope of the present invention should be with reference to appending claims and whole equivalent thereof.Any selectable unit whether (no matter first-selection), all can with other any selectable units whether (no matter first-selection) combination.In following claim, unless specifically stated otherwise, otherwise indefinite article " " or " a kind of " refer to the quantity of the one or more projects in the hereinafter content.Only if spell out attributive function with " meaning is ", otherwise appending claims should not thought the limitation of meaning and function.
Although content of the present invention has been done detailed introduction through above-mentioned preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited appended claim.
Claims (20)
1. a semiconductor device is characterized in that, comprises:
A home court effect pipe that contains source electrode, body and grid;
A sensing FET that contains source electrode, body and grid, wherein the transistor part of sensing FET is surrounded by the transistor of home court effect pipe, and is positioned near the transistor of home court effect pipe;
A sensing FET source pad that is positioned at the semiconductor device edge place, wherein sensing FET source pad is separated with the transistor part of sensing FET, and through sensing FET probe metal, is connected to the transistor part of sensing FET; And
An electrically insulated structures makes the source electrode of home court effect pipe and the source electrode and the body electric insulation of body and sensing FET,
Wherein home court effect pipe, sensing FET and electrically insulated structures are formed in the independent semiconductor wafer; Make the transistor part of sensing FET and active area that sensing FET source pad is positioned at home court effect pipe outside through the configuration insulation system
Wherein semiconductor device is the vertical field-effect pipe of a separation.
2. the described semiconductor device of claim 1 is characterized in that, wherein sensing FET probe metal, home court effect pipe source metal and gate metal all are divided portion in the same independent metal level.
3. the described semiconductor device of claim 1 is characterized in that, wherein sensing FET probe metal is not a resistance.
4. the described semiconductor device of claim 1 is characterized in that, wherein the transistor part of sensing FET is wide not as sensing FET probe metal.
5. the described semiconductor device of claim 1 is characterized in that, wherein the transistor part of sensing FET is positioned near the center of home court effect pipe.
6. the described semiconductor device of claim 1; It is characterized in that; Wherein sensing FET transistor part, sensing FET probe metal and sensing FET source pad are all passed through insulation system; Separate with home court effect pipe, and, be positioned at the periphery of home court effect pipe through sensing FET source pad.
7. the described semiconductor device of claim 1; It is characterized in that; Wherein insulation system contains one or more dark potential wells, is formed on the top of epitaxial loayer, and wherein dark potential well makes the source electrode and the body of sensing FET; With the source electrode and the body insulation of home court effect pipe, wherein the conduction type of dark potential well is identical with the conduction type in effect tube body district, home court.
8. the described semiconductor device of claim 7 is characterized in that, wherein the degree of depth of dark potential well is greater than the degree of depth in effect tube body district, home court.
9. the described semiconductor device of claim 8 is characterized in that, wherein the degree of depth of dark potential well is between 1 micron to 2 microns, and the body region depth of home court effect pipe is between 0.5 micron to 0.7 micron.
10. the described semiconductor device of claim 8 is characterized in that, wherein the doping content of dark potential well is less than the doping content in effect tube body district, home court.
11. the described semiconductor device of claim 10 is characterized in that, wherein the doping content of dark potential well is about 4 * 10
16/ cm
3
12. the described semiconductor device of claim 7 is characterized in that, the dark potential well between the transistor part of sensing FET and the home court effect pipe wherein is about the width of the transistor unit spacing of twice.
13. the described semiconductor device of claim 7 is characterized in that, wherein the dark potential well width between the transistor part of sensing FET and the home court effect pipe is about 2 to 10 microns.
14. the described semiconductor device of claim 1 is characterized in that, wherein home court effect pipe and sensing FET are made up of metal oxide semiconductor field effect tube MOSFET.
15. the described semiconductor device of claim 1; It is characterized in that; The electrically insulated structures between sensing FET and the home court effect pipe wherein; Be to be made up of near the body ring the insulated trench, the metal level that one of them is positioned at electric insulation top is electrically connected to the grid of sensing FET the grid of home court effect pipe.
16. a method that is used to prepare the semiconductor device that contains a home court effect pipe and a sensing FET is characterized in that, comprises:
A) in a substrate, source electrode, body and the grid of preparation home court effect pipe;
B) in substrate; Source electrode, body and the grid of preparation sensing FET, wherein the sensing FET is positioned near the center of home court effect pipe, and wherein the transistor part of sensing FET is surrounded by the transistor of home court effect pipe; And be positioned near the transistor of home court effect pipe; To reduce distortion and the error that the sensing FET is measured, wherein sensing FET and home court effect pipe are the vertical field-effect pipe, share a common substrate;
C) in substrate, prepare an electrically insulated structures, make the source electrode and the body of home court effect pipe, with the source electrode and the body electric insulation of sensing FET; And
D) prepare a sensing FET source pad that is positioned at effect tube edges place, home court, and be connected on the sensing FET through sensing FET probe metal,
Wherein sensing FET and sensing FET source pad through electrically insulated structures, are separated with home court effect pipe.
17. the described method of claim 16 is characterized in that, wherein a) to d) comprise:
I) above the substrate of heavily doped first conduction type, the epitaxial loayer of one first conduction type of preparation;
Ii) above epitaxial loayer, prepare a dark potential well mask; And
The alloy of second conduction type is implanted, to form dark potential well area, second conduction type and first conductivity type opposite in the iii) top of the epitaxial loayer in the insulation system zone of semiconductor device.
18. the described method of claim 17 is characterized in that, wherein iii) also comprises the dark potential well area of preparation, makes the degree of depth of dark potential well area be about 1 to 2 micron, doping content is about 4 * 10
16/ cm
3
19. the described method of claim 16 is characterized in that, also comprises:
Preparation home court effect tube grid groove, sensing fet gate groove and insulated trench, wherein insulated trench and constitutes a part of described electric insulation between home court effect pipe and sensing FET, and wherein insulated trench does not connect grid voltage;
Above described electrically insulated structures, deposit an insulating barrier; And
Insulating barrier above described electric insulation prepares a metal level, and described metal level is connected to the grid of sensing FET the grid of home court effect pipe.
20. the described method of claim 16 is characterized in that, wherein said semiconductor device is the vertical field-effect pipe of a separation.
Applications Claiming Priority (2)
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|---|---|---|---|
| US12/870,489 | 2010-08-27 | ||
| US12/870,489 US7939882B2 (en) | 2008-04-07 | 2010-08-27 | Integration of sense FET into discrete power MOSFET |
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| CN103035602A (en) * | 2011-09-29 | 2013-04-10 | 瑞萨电子株式会社 | Semiconductor device |
| CN106024731A (en) * | 2016-06-23 | 2016-10-12 | 华天科技（西安）有限公司 | Packaging part capable of preventing plastic packaging material from overflowing out of surface by passivating layer |
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| US20090250770A1 (en) * | 2008-04-07 | 2009-10-08 | Alpha & Omega Semiconductor, Ltd. | Integration of a sense fet into a discrete power mosfet |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103035602A (en) * | 2011-09-29 | 2013-04-10 | 瑞萨电子株式会社 | Semiconductor device |
| CN103035602B (en) * | 2011-09-29 | 2017-04-26 | 瑞萨电子株式会社 | Semiconductor device |
| CN106024731A (en) * | 2016-06-23 | 2016-10-12 | 华天科技（西安）有限公司 | Packaging part capable of preventing plastic packaging material from overflowing out of surface by passivating layer |
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| CN113809180A (en) * | 2021-11-19 | 2021-12-17 | 陕西亚成微电子股份有限公司 | MOSFET structure with temperature detection function and manufacturing method |
| CN113809180B (en) * | 2021-11-19 | 2022-02-22 | 陕西亚成微电子股份有限公司 | MOSFET structure with temperature detection function and manufacturing method |
Also Published As
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| TWI500141B (en) | 2015-09-11 |
| TW201209996A (en) | 2012-03-01 |
| CN102386182B (en) | 2014-11-05 |
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Effective date of registration: 20200820 Address after: Ontario, Canada Patentee after: World semiconductor International L.P. Address before: 475 oakmead Park Road, Sunnyvale, California, USA Patentee before: Alpha and Omega Semiconductor Inc. |