CN102386912B - 用于可编程逻辑器件的专门处理块 - Google Patents

用于可编程逻辑器件的专门处理块 Download PDF

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CN102386912B
CN102386912B CN201110276366.8A CN201110276366A CN102386912B CN 102386912 B CN102386912 B CN 102386912B CN 201110276366 A CN201110276366 A CN 201110276366A CN 102386912 B CN102386912 B CN 102386912B
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CN102386912A (zh
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M·朗哈默
K·Y·M·李
O·阿兹高密
K·施特赖歇尔
林以雯
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Intel Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products

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Abstract

一种用于可编程逻辑器件的专门处理块加入了基本处理单元，该单元执行两个乘法的求和，将两个乘法的部分乘积相加，而不计算各个乘法。与传统分开的乘法器和加法器相比，这些基本处理单元消耗更小的面积。所述专门处理块还具有输入和输出级，以及回送功能，以允许该块可以被配置用于各种数字信号处理操作。

Description

用于可编程逻辑器件的专门处理块
本申请是2006年12月31日提交的名称为“用于可编程逻辑器件的专门处理块”的中国专利申请200610156622.9的分案申请。
相关申请的交叉引用
本申请要求分别在2006年2月9日和2006年4月4日提交的共同待决的、被共同转让的美国临时专利申请第60/772,197和60/789,535号的权益，每个所述申请都以其各自全文通过引用方式被并入本文。
技术领域
本发明涉及可编程逻辑器件(PLD)，而更具体地，涉及专门处理块，该处理块可被包含在这种器件中。
背景技术
随着使用PLD的应用在复杂性上增加，设计PLD时使其包括一般的可编程逻辑资源之外还包括专门处理块已变得更加普通。这些专门处理块可包括在PLD上的电路集合，其已经部分地或全部地被硬连线以执行一个或多个特定的任务，诸如逻辑或数学运算。专门处理块也可能包含一个或多个专门结构，诸如可配置存储器元件阵列。通常在这些专门处理块中实现的结构的例子包括：乘法器、算术逻辑单元(ALU)、桶型移位器、各种存储器元件(诸如FIFO/LIFO/SIPO/RAM/ROM/CAM块和寄存器文件)、与(AND)/与非(NAND)/或(OR)/异或(NOR)阵列等等、或者其组合。
一种已经配备在PLD上的特别有用类型的专门处理块是数字信号处理(DSP)块，其可能被用来处理例如音频信号。这些块通常也被称为乘累加(“MAC”)块，因为它们包括用以执行乘法运算以及求和和/或乘法运算的累加的结构。
例如，由加利福尼亚州圣何塞(SanJose，Californian)的Altera公司出售的名为的PLD包括DSP块，每个DSP块包括四个18×18的乘法器。每个这些DSP块也包括加法器和寄存器，以及可编程连接器(举例来说，多路复用器)，该可编程连接器允许各种组件以不同的方式进行配置。在每个这种块中，乘法器不仅可以被配置成四个单独18×18的乘法器，而且也可以被配置成四个更小的乘法器、或者一个更大(36×36)的乘法器。另外，一个18×18的复数乘法(其为每个实部和虚部部分分解成两个18×18乘法运算)可以被执行。为了支持四个18×18的乘法运算，该块具有4×(18+18)＝144个输入。类似地，18×18乘法的输出是36位宽度，因此为了支持四个这样乘法运算的输出，该块也具有36×4＝144个输出。
然而，那些输入和输出可能不是在DSP块可以工作的每个模式中都被使用。例如，如果DSP块被配置成一个具有18位数据和系数的有限脉冲响应(FIR)滤波器，那么每个块可以被用来执行四个18×18乘法的求和，以形成一个更长的FIR滤波器的四抽头子块。在这种情况下，输入的数量是4×(18+18)＝144线，但输出只有38位宽度，即使DSP块能支持144条输出线。类似地，在36×36位的乘法中，所有四个内部乘法器都被使用，但是只有(36+36)＝72条输入线和72条输出线被使用(即使有144条输入线和144条输出线)。因此，在这一配置中，输入线没有全部被使用，即使DSP块的核心是完全地被使用了。
输入/输出(I/O)驱动器和线可以消耗极大的器件面积。确实，在前面提及的PLD的DSP块中，I/O资源消耗了大约DSP块面积的50％。可是，如上面讨论的，它们不总是被使用。同时，它们不能被消除，因为必须支持该块的所有潜在配置。
这就希望能减少被诸如DSP块的专门处理块消耗的PLD的面积，而不丢失该块的功能性。
发明内容
本发明涉及用于PLD的专门处理块，其中所述专门处理块减少了面积而不失去功能性。根据本发明的一个方面，专门处理块优选地包括多个基本处理单元，而不是分离的乘法器。每个基本处理单元优选地包括至少两个乘法器以及对所有这些至少两个乘法器的部分乘积求和的逻辑的等效物。结果，所有乘法的总和在单步中计算，而不是对每个乘法器的部分乘积求和形成各个乘积，然后对那些乘积求和。这一基本处理单元可以被构造成具有比单独的乘法器和加法器更小的面积。如果需要执行单个乘法，则使用基本处理单元中的其中一个乘法器，而到其余乘法器的输入被置零输出。然而，由于基本处理单元装置减少了专门处理块的面积，所以效率得到了提高。
在一个优选的实施例中，基本处理单元包括两个18×18乘法器和一个加法器的等效物，以便该单元可以输出两个乘法运算的总和。当每个该18×18乘法器可以被配置用于更小的乘积运算(举例来说，9×9或者12×12)时，基本处理单元的集成本质意谓着各个乘法器输出是不易得到的。只有该总和可以被专门处理块的其余部分使用。因此，为了获得18位×18位或更小的单个非复数乘法的结果，整个基本处理单元都必须被使用。第二乘法器不能是空闲的，其简单地使其输入归零。
根据本发明，专门处理块优选地也具有一个或更多个额外的加法器，额外加法器用于基本处理单元以及可选的流水线寄存器和灵活输出级的输出的额外处理。因此，专门处理块优选地可以被配置用于各种形式的滤波和其他数字信号处理操作。另外，专门处理块优选地还具有这样的性能：将至少其中一个它的输出反馈作为输入(这在自适应滤波运算中是有很用的)，以及将输入和输出都链接到额外的专门处理块上。
因此，根据本发明，提供了用于可编程逻辑器件的专门处理块。该专门处理块优选地包括多个基本处理单元，每个基本处理单元包括多个乘法器和用于在一个运算中计算由所有多个乘法器产生的部分乘积的总和的电路。
附图说明
通过结合附图，考虑下面的详细描述，本发明上述的和其他的目的及优点将会显而易见，附图中同样的标记字符自始至终指代同样的部件，其中：
图1是根据本发明的专门处理块的一个优选实施例的高级框图；
图2是图1专门处理块的功能性框图；
图3是用于根据本发明的专门处理块的基本处理单元的优选实施例的框图；
图4是根据本发明的专门处理块的输出级的优选实施例；
图5是根据本发明被配置为有限脉冲响应滤波器的专门处理块的功能性框图；
图6是根据本发明被配置用于算术移位的专门处理块的功能性框图；
图7是根据本发明被配置用于逻辑移位的专门处理块的输出级的优选实施例；
图8是根据本发明被配置用于旋转的专门处理块的功能性框图；
图9是根据本发明被配置为桶型移位器(barrelshifter)的专门处理块的功能性框图；和
图10是采用并入本发明的可编程逻辑器件的说明性系统的简化框图。
具体实施方式
现在，将参考图1-9描述本发明。
图1示出了根据本发明的专门处理块的一个优选实施例10的高级框图，而图2是同一实施例10的功能性框图。
从图1中可以看出，专门处理块10包括可选的输入预多路复用(pre-MUX)级11、可选的输入寄存器级12、可选的输入多路复用级13、乘法级14、可选的流水线寄存器级15以及加法器/输出级16。
输入预多路复用级11(如果有)的功能是将常规的输入格式化、回送输入以及将输入(见下面)级联成适合寄存的形式。
常规的输入不需要任何特定的格式化。级联输入可能是前面输入的延迟一个寄存器的形式，因此，可能需要相应的格式化。然而，这样的格式化也可以在可编程逻辑器件的可编程逻辑中完成，而专门处理块10是该逻辑器件的一个部件，因此如果级联输入的格式化是唯一要求的预多路复用功能，则输入预多路复用级11可以被省略或(如果有)被旁路。回送输入17可能被布置，使其总是被连接到特殊的乘法器或乘法器组上。由输入预多路复用级11执行的格式化可能包括到特殊位位置的特殊输入的方向，这取决于由专门处理块10执行的功能。在一个实施例中，格式化可能根据存储的表来执行，该表识别各种可能的运算(举例来说：各种尺寸的简单乘法或复数乘法、移位运算、旋转运算等等)并指定所需要的相应格式。
输入预多路复用级11的输出(如果有)可由可选的输入寄存器级12寄存。如果没有输入预多路复用级11，那么如果需要，输入寄存功能可以在可编程逻辑器件的可编程逻辑部分中被实现，而块10是该逻辑器件的一个部件。因此，输入寄存器级12是被认为是可选的。输入寄存器级12(即使有)优选地可以可选地被旁路，这种情况下需要的或期望的是未寄存的输出。
输入多路复用级13(如果有)从输入预多路复用级11获取寄存的或未寄存的输入和从该可编程逻辑器件其他地方潜在地获取输入，并且将数据格式化用于不同的工作模式。在这方面，它类似于输入预多路复用级11，因此，通常如果提供了输入预多路复用级11和输入多路复用级13的其中一个，那么可以不提供另一个。
作为由输入预多路复用级11或输入多路复用级13执行的格式化类型的一个例子，考虑一个18×18的复数乘法，其中：
实部结果＝Re[(a+jb)×(c+jd)]＝(ac-bd)
虚部结果＝Im[(a+jb)×(c+jd)]＝(ad+bc)
这一复数运算需要四个18×18的乘法和因此需要8个18位输入，但是因为只有四个唯一的18位共享输入，所以输入多路复用级13将获取输入a、b、c和d，并且执行必要的复制，因此这四个输入被适当地路由到正确的乘法器输入上，用于每个实部和虚部的计算。同样地，对于9位和12位模式的运算而言，输入预多路复用级11和/或输入多路复用级13确保了输入位的正确对齐，以便获得正确的结果。
乘法级14优选地包括如上所述的多个基本处理单元。在一个优选的实施例中，每个专门处理块10(见图2)包括四个基本处理单元30，意谓着该处理块可以执行多达8个乘法，其中两个乘法为一组，这两乘法被一起求和。在这个实施例中，专门处理块10中的基本处理单元优选地被分组成相同的半块，所以在其本身右边的每个半块可以被认为是本发明内的一个专门处理块。
每个基本处理单元优选地包括用于两个18×18乘法的求和的功能。基本处理单元优选地是全部相同的，但是在一些实施例中，可能只在一些乘法器的一些输入上提供求反功能，因为这可能需要用于复数乘法(如上面显而易见的，在复数乘法中可能需要减法)。替代地，求反功能可能在基本处理单元的加法器部分中被提供，以使一个或多个加法器也能执行减法。
图3示出了基本处理单元的一个优选实施例的结构。每个基本处理单元30优选地支持两个18×18乘法的求和，并且优选地包括两个部分乘积发生器31、两个10向量到2向量的压缩器32、4到2压缩器33和两个进位传递加法器34。加法器34优选地包括一个30位加法器340和一个24位加法器341，该两个加法器是由控制信号342选择性地可连接的。对于诸如9×9或12×12的更小乘法，则只需要24位，因此该两个加法器可以被断开，以允许两个独立乘法。对于诸如18×18的更大乘法，则该两个加法器34应该被连接成单个加法器。
每个部分乘积发生器31优选地产生9个20位的布斯编码的(Booth-encoded)向量(布斯编码是一项已知的技术，其可以减少部分乘积的数目)，以及一个17位无符号进位向量(负的部分乘积具有二进制补码的格式，在该进位向量中带有关联的进位-输入(carry-in)位)。在无符号乘法器(其优选地总是将零用于有符号乘法器)的情况下，可能产生额外19位有符号的部分乘积。尽管优选地多达11个向量可能被产生，但是进位位优选地与部分乘积向量组合，这只需要10个向量被压缩。
部分乘积优选地被压缩成两个39位的向量(36位加上符号扩展位)。任何符号扩展应该被正确地保存越过36位18×18乘法器的边界，以使任何符号扩展可以是有效的，达到72位36×36乘法器的边界(假设两个基本处理单元被组合实现如下面描述的36×36的乘法)。压缩后，结果优选地在多路复用和移位电路35中被处理，该电路优选地包括组合逻辑，在该逻辑处相加前结果的任一符号扩展、补零或移位(因为可能需要它们，这取决于要执行的运算)可以在4到2压缩器33中的结果和进位传递加法器34中结果的最终组合前被执行。对于每个电路350、351，输入优选地是两个39位的向量，总计78个输入位，而输出优选地是两个54位的向量，总计108位。额外的30位是符号扩展、补零以及或移位的结果。多路复用器352显示了在符号扩展结果或补零结果之间的选择。四个54位的向量被输入到压缩器33，该压缩器输出两个54位的向量，该两向量在加法器34中被相加以产生一个54位的输出。
如上面讨论，因为来自两个乘法器的部分乘积立即被相加，所以基本处理单元的这两个乘法器不能用于两个独立乘法，但是单个乘法可以通过将第二乘法器的输入置零得以实现。
对于更小的乘法，独立的子集乘法器(9×9和12×12的情况)可能被处理如下：
对于两个9×9乘法，第一个9×9乘法优选地是利用第一个乘法器(图3的左边)的最高有效位(MSB)进行计算，而第二个9×9乘法优选地利用第二乘法器(图3的右边)的最低有效位(LSB)进行计算。右乘法器的MSB以相应数值的符号扩展适当地进行填充。左乘法器的输出(总和以及进位向量)被左移18位。然后，两个乘法器的输出优选地是压缩到一起，并且两个结果的最终向量随后用两个加法器34进行相加，在这个运算中没有连接该两个加法器。第一个9×9结果优选地将是左(30位)加法器340的MSB上的输出，而第二个9×9结果优选地将是右(24位)加法器341的LSB上的输出。
独立的12×12乘法可以用类似于9×9乘法的方式，利用MSB/LSB方法进行计算。
在这两种情况下，优选地右乘法器的输出在24位以上被置零，以防止对独立的左乘法器结果的任何干扰。
在被求和的乘法的情况下，不管什么精度，所有输入优选地被移位以占据所用乘法器的MSB，而输出向量优选地不被移位。然而，输出向量优选地被完全符号扩展，以使在加法器34外的符号扩展可以被用于累加器的全部宽度(如下)。
优选地，对于复数乘法和其他需要乘积相减的运算，加法器输入可以被求反(有效地使得该加法器成为加法器/减法器)。然而，替代地，通过反转输入(二进制补码)和将被乘数加到结果上，一个或更多个乘法器可被提供选择性地求反其输出向量的能力。被乘数加法可以在部分乘积的压缩中被执行，以便在加法器34之前可以实现求反。
流水线寄存器级15优选地可根据用户的选择被旁路，其优选地允许乘法级14的输出在进一步加法或累加或其他处理前可以被寄存。
优选地，加法器/输出级16选择性地移位、相加、累加、或寄存其输入、或者是上面的任何组合。其输入优选地是在专门处理块10中的两个基本处理单元的输出。如图4中可看出的，两个输入40、41被输入到各自的寄存器/移位器单元42、43中，这些单元可选地可能对输入40、41进行移位或符号扩展。在一个优选的实施例中，输入40、41中的每一个是一个54位向量，其被移位或符号扩展以产生各自的72位向量。
单元42、43的输出优选地是连同级16自己的输出45一起被输入到3∶2压缩器44。这一反馈给专门处理块10提供了累加功能。优选地，该反馈输出45经过多路复用器46，当累加不是必需的或期望的时，该多路复用器替代地可以选择零(举例来说，地)输入。
压缩器44的输出被提供(通过如下所述的适当多路复用器)到两个加法器47、48，该两个加法器可在可编程控制下被链接到一起，这取决于如下所述它们要被运用的用途。加法器47、48的输出优选地可能被寄存在寄存器49、400中或者不被寄存，这由多路复用器401、402决定。无论被寄存与否，输出47、48都优选地组成专门处理块10的输出向量。作为一种替代路径，多路复用器403、404、405允许加法器47、48被旁路，在此处基本处理单元30的输出被输出而没有进一步的处理。
上面描述的在每个基本处理单元30可以执行两个18×18乘法的求和的情况下，两个基本处理单元30可以执行36×36的乘法，众所周知，该乘法可以被分解成四个18×18的乘法。在这一情况下，两个压缩的72位向量优选地由压缩器44输出并优选地由两个44位的加法器47、48相加在一起，通过与门406，这两个加法器被可编程地连接到一起用于这一模式。在这一模式中，高16位可被忽略。
在其他具有更窄输出的模式中，加法器47、48不需要被连接在一起，加法器47、48可选地被布置，以将专门处理块10的输出和另一专门处理块10的类似输出链接。为了帮助这一模式，寄存器400的输出，例如，可能被馈送到4∶2多路复用器407上，该多路复用器提供两个输入到加法器47。到多路复用器407的另一输入可能是来自另一专门处理块10的链入(chain-in)输入408，该输入可能是通过来自其他专门处理块10的寄存器49的链出(chain-out)输出409提供的。
因此，在链式模式中，44位的加法器48可能被用来将专门处理块10其中一个(该处理块可被配置，举例来说，为单个乘法器、乘法器的求和、或累加器)内的结果和前面块的结果加在一起。通过利用多路复用器407选择加法器48的输出和另一专门处理块10的输出作为加法器47的输入，当前专门处理块10的输出可以是当前的和前面的专门处理块10的输出的链式和。如果使用链式模式，只有44位的累加器是可利用的，该累加器将仍给出6位到8位的保护带，这取决于乘法器的数量。然而，显而易见的是，链式模式对36位模式是不可用的，在36位模式中需要加法器47、48，以获得单个专门处理块10的结果。
根据运算的模式，输出路径可能是稍微不同的。因此，多路复用器401、402允许选择加法器47、48的寄存或未寄存的输出。然而，应当理解，如所示的，被寄存的输出优选地用于级联或链式模式中。
另外，至少一个输出，如在17，可能被回送到专门处理块10的输入。例如，如果专门处理块10是可编程地被配置用于自适应滤波，则这一回送特征可能被使用。虽然可提供多个回送，但是在优选的实施例中，提供了到单个乘法器或乘法器组的一个回送17。
本发明的专门处理块10可被可编程地配置为一个长链有限脉冲响应(FIR)滤波器。如图5所示，四个基本处理单元30被配置为这一FIR滤波器50的一部分。如上讨论的，这可能被认为是一个或两个专门处理块10。如所示的，每个加法器48被用以相加四个乘法的结果，而在上面描述的链式或级联模式中使用的加法器47将加法器48的输出(也可能，其他专门处理块10的加法器48的输出)相加在一起，从而形成一个长FIR滤波器。FIR滤波器的系数是在51的输入，而要被滤波的数据是经由寄存器链52输入的，该寄存器链52优选地形成在输入预多路复用级11、输入寄存器级12或者输入多路复用级13的其中之一中。为了解决由输出级联链引入的延迟，在输入级联链52中优选地提供了至少一个额外延迟53(举例来说，以额外寄存器的形式)。优选地，该延迟的数目与加法器47的数目对应，或更具体地，对应于延迟53补偿的输出寄存器400。通常，这将为每对基本处理单元30合计一个延迟53。在与此同时提交的(律师备审案件目录第000174-0465-101号)共同待决的、共同转让的美国专利申请第11/_，_，号中，描述了进一步的FIR滤波器实现，在此该专利申请以全文引用的方式被并入本文。
除了实现FIR滤波器，本发明的专门处理块10可被可编程地配置为桶型移位器。具体地，通过利用36×36的乘法器模式，一个32位向量可以被算术或逻辑地移位到左边或右边。这一N位的移位可通过把要被移位的向量乘以等长度的第二个向量来执行，除了第N个最低有效位是1之外，该第二向量的所有位都是0。
如果要被移位的向量被符号扩展到36位，而第二个向量被填零到36位，则结果是算术移位，而该移位是到左边还是到右边取决于结果是分别取自于64位结果的32个最高有效位，还是32个最低有效位。图6示出了这一移位运算。
同样地，如果两个向量都被填零到36位，则结果是逻辑移位，而该移位是到左边或是到右边取决于结果是分别取自于64位结果的32个最高有效位，还是32个最低有效位。图7示出了这一移位运算。
另外，如果两个向量都被填零到36位，并且64位结果的32个最高有效位和32个最低有效位做“或”运算，则结果是将第一向量的N个最高位旋转到该结果的N个最低位，如图8所示。
图9示出了怎样利用36×36乘法器模式90(其执行如上所述的32×32乘法)、或门91(其输入是64位结果的两个32位的半部分)以及三输入多路复用器92来执行算术和逻辑移位、和旋转，其根据下表运算：
A B MUX Result(结果)
有符号 无符号 00 算术左移
有符号 无符号 01 算术右移
无符号 无符号 00 逻辑左移
无符号 无符号 01 逻辑右移
无符号 无符号 10 旋转
应当注意到算术左移和逻辑左移产生同样的结果，因而那些情况是多余的。换一方式说，只有算术右移才真正地需要有符号的输入。
因此可见，基于多个基本处理单元，已经提供了用于可编程逻辑器件的专门处理块。
包含根据本发明的这样电路的PLD100可能在多种电子器件中被使用。一种可能的用途是在数据处理系统中，如图10所示。数据处理系统900可能包括一个或更多个下面的组件：处理器901；存储器902；输入/输出电路903；以及外围设备904。这些元件由系统总线905连接到一起，并被组装到电路板906上，该电路板被包含在终端用户系统907中。
系统900可以被用于广泛的各种应用，诸如计算机联网、数据联网、仪表、视频处理、数字信号处理或者任何其他应用，在这些应用中期望利用可编程逻辑或可重新编程逻辑的优点。PLD100可以被用来执行各种不同逻辑功能。例如，PLD100可以被配置为处理器或控制器，其与处理器901协同工作。PLD100也可能被用做判优器(arbiter)，其用于裁定对系统900中共享资源的访问。在另一例子中，PLD100可以被配置为在处理器901和系统900中其他元件之一之间的接口。应当注意到系统900只是示例性的，而本发明真正的范围和精神应该由下面的权利要求指出。
各种技术可以被用来实现如上所述并且包含本发明的PLD90。
应当理解，前面所述只是本发明原理的阐释性说明，而在不脱离本发明范围和精神的情况下，本领域的技术人员可以做各种修改。例如，本发明的各种元件可以以任一期望的数量和/或布置被提供在PLD上。本领域的技术人员将意识到本发明可以由不同于所述实施例的实施例来实施，所述实施例是为了阐释说明而不是限制的目的，并且本发明只由下面的权利要求加以限定。

Claims (10)

1.一种用于可编程逻辑器件的专门处理块，多个所述专门处理块存在于所述可编程逻辑器件上，每个所述专门处理块适于形成有限脉冲响应滤波器，所述专门处理块包括：
多个基本处理单元，每个所述基本处理单元包括：多个部分乘积发生器，所述部分乘积发生器的每个各自一个提供表示各自部分乘积的各自多个向量；
第一组多个输入寄存器，用于将所述有限脉冲响应滤波器的系数作为输入输入到所述多个部分乘积发生器；
第二组多个输入寄存器，用于将数据输入到所述有限脉冲响应滤波器，所述寄存器被链接用于逐一地输入数据到所述多个部分乘积发生器中的每个；和
输出级，用于将以下两项相加作为输出：(1)涉及两个所述基本处理单元的运算之和，和(2)从所述多个专门处理块的第一其他一个级联的对应输出，所述输出级包括输出级联寄存器，用于寄存级联到所述多个专门处理块的第二其他一个中的另一个输出级的所述输出；其中：
所述第二组多个输入寄存器包括延迟寄存器，以在所述第二组多个输入寄存器链接到所述多个专门处理块的所述第二其他一个中的对应的第二组多个输入寄存器时补偿所述输出级联寄存器。
2.根据权利要求1所述的专门处理块，其中所述延迟寄存器包括多个延迟寄存器，所述多个延迟寄存器包括针对每一对所述基本处理单元的一个延迟寄存器。
3.根据权利要求1所述的专门处理块，进一步包括：
压缩器电路，其将每个各自多个向量压缩成表示所述各自部分乘积的较少数目的向量；和
用于相加的电路，其用于在一次运算中相加由所有所述多个部分乘积发生器产生的所述较少数目的向量表示的部分乘积，其中：
所述用于相加的电路仅仅输出所有所述多个部分乘积发生器的所有部分乘积之和；和
没有任何一个所述多个部分乘积发生器的部分乘积被单独输出。
4.根据权利要求1所述的专门处理块，其中所述输出级包括多个加法器，所述多个加法器中的一个加法器适于提供涉及两个所述基本处理单元的运算的所述和作为输出，并且所述多个加法器中的另一个加法器适于提供以下两项的和作为输出：(1)涉及两个所述基本处理单元的运算的所述和，和(2)从所述多个专门处理块的所述第一其他一个级联的所述对应输出。
5.一种可编程逻辑器件，其适于形成有限脉冲响应滤波器，所述可编程逻辑器件包括：
至少一个专门处理块，每个所述专门处理块包括：
多个基本处理单元，每个所述基本处理单元包括：多个部分乘积发生器，所述部分乘积发生器的每个各自一个提供表示各自部分乘积的各自多个向量；
输出级，用于将以下两项相加作为输出：(1)涉及两个所述基本处理单元的运算之和，和(2)从所述至少一个专门处理块的第一其他一个中的第一其他输出级级联的对应输出；每个所述专门处理块还包括：
输出级联寄存器，用于寄存级联到所述至少一个专门处理块的第二其他一个中的第二其他输出级的所述输出；所述可编程逻辑器件还包括：
第一组多个输入寄存器，用于将数据输入到所述有限脉冲响应滤波器，所述寄存器被链接用于逐一地输入数据到所述多个部分乘积发生器中的每个；和
与所述第一组多个输入寄存器链接的延迟寄存器，以在所述第一组多个输入寄存器链接到所述至少一个专门处理块的所述第二其他一个中的对应的第一组多个输入寄存器时补偿所述输出级联寄存器。
6.根据权利要求5所述的可编程逻辑器件，其中所述延迟寄存器包括多个延迟寄存器，所述多个延迟寄存器包括针对每一对所述基本处理单元的一个延迟寄存器。
7.根据权利要求5所述的可编程逻辑器件，其中所述专门处理块还包括：
压缩器电路，其将每个各自多个向量压缩成表示所述各自部分乘积的较少数目的向量；和
用于相加的电路，其用于在一次运算中相加由所有所述多个部分乘积发生器产生的所述较少数目的向量表示的部分乘积，其中：
所述用于相加的电路仅仅输出所有所述多个部分乘积发生器的所有部分乘积之和；和
没有任何一个所述多个部分乘积发生器的部分乘积被单独输出。
8.根据权利要求5所述的可编程逻辑器件，其中所述输出级包括多个加法器，所述多个加法器中的一个加法器适于提供涉及两个所述基本处理单元的运算的所述和作为输出，并且所述多个加法器中的另一个加法器适于提供以下两项的和作为输出：(1)涉及两个所述基本处理单元的运算的所述和，和(2)从所述至少一个专门处理块的所述第一其他一个中的所述第一其他输出级级联的所述对应输出。
9.根据权利要求5所述的可编程逻辑器件，其中所述第一组多个输入寄存器和所述延迟寄存器在所述专门处理块中合并。
10.根据权利要求5所述的可编程逻辑器件，进一步包括第二组多个输入寄存器，用于将所述有限脉冲响应滤波器的系数作为输入输入到所述多个部分乘积发生器。
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