CN102403971B - Automatic gain control demodulation circuit - Google Patents
Automatic gain control demodulation circuit Download PDFInfo
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- CN102403971B CN102403971B CN201010286327.1A CN201010286327A CN102403971B CN 102403971 B CN102403971 B CN 102403971B CN 201010286327 A CN201010286327 A CN 201010286327A CN 102403971 B CN102403971 B CN 102403971B
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- current mirror
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- demodulation
- variable gain
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Abstract
The invention discloses an automatic gain control demodulation circuit, belonging to the field of radio frequency integrated circuit; the circuit of the invention comprises a variable gain amplifier, a demodulation loop, a buffer and a charge pump, wherein the output end of the variable gain amplifier is connected with the input end of the demodulation loop, the output end of the demodulation loop is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the charge pump, and the control end of the variable gain amplifier is connected with the output end of the charge pump. Compared with the prior art, the automatic gain control demodulation circuit of the invention has the advantages of simple structure, low power dissipation, easiness in implementation and large power self-regulating range of input signals.
Description
Technical field
The present invention relates to a kind of demodulator circuit, relate in particular to a kind of automatic gain control demodulation circuit, belong to field of radio frequency integrated circuits.
Background technology
Along with integrated circuit (Integrated Circuits, IC) development of technology, the size of semiconductor device is constantly dwindled, and the performance of integrated circuit constantly promotes, and is mainly manifested in that operating frequency is more and more faster, more and more higher, the attainable function of integrated level becomes increasingly complex.Dwindling of device itself can increase leakage current, and the lifting of operating frequency increases node capacitor and discharges and recharges the power consumption causing, the complicated of function often be take power consumption especially as sacrifice.Especially when process node be developed to deep-submicron 130,90nm, the cut-off frequency f of device
trise to 70GHz, 100GHz and more than, circuit work frequency rises to even 10GHz magnitude of GHz, high-performance and low-power consumption more and more become the conflict index that needs compromise to consider.
The temperature rising that power consumption causes can make device performance degeneration even burn, and another is more seriously at battery technology under the prerequisite without marked improvement, and power consumption is by the service time of direct limiting mobile terminal.Radio frequency (Radio Frequency, RF) circuit is as the radio communication of supplying with without lasting power supply and an important module in personal data terminal, and its power consumption also day by day increases and becomes the key factor affecting in system power dissipation.Low-power consumption (Low Power, LP) design becomes an important consideration of integrated circuit (IC) design thereupon.In digital circuit, various Low-power Technology are widely used already, as multivoltage technology, multi-Vt technology, pipelining, concurrent technique, precomputation technology etc., these technology are by system research and be widely used in the system level design and electric design automation (Electronic Design Automation, EDA) synthesis tool of digital circuit.Ultralow Consumption for simulation and radio circuit, there is no systematized design cycle at present.Its low power dissipation design and research are except considering power consumption in overall situation integral body, and designer should be in each circuit details optimizing power consumption index.
In digital communication, receive signal after the amplification of RF front-end module and the filtering of filter and mirror image inhibition, in analog baseband section, divide further amplification, and obtain final data " 1 ", " 0 " signal after giving demodulation module reception.Traditional ripple demodulation mode that unloads comprises two kinds of coherent demodulation and non-coherent demodulations.The former needs the relevant local oscillated signal of local generation and carrier wave that reception signal is mixed to Low Medium Frequency or zero intermediate frequency, and the latter generally only comprises the amplitude detection of waveform.Comparatively speaking, the local oscillated signal that the former needs local phase-locked loop generation strictly to synchronize with carrier frequency and phase place, therefore that circuit implements is comparatively complicated, and when existence interference and signal attenuation, more difficultly reaches requirement; And the latter generally only needs envelope detected (as frequency shift keying) or phase-detection (as differential phase keying (DPSK)), cost is the 3dB loss of signal to noise ratio.No matter be traditional coherent demodulation method, or non-coherent demodulation method, generally realizing more complicated, power consumption is larger.
Summary of the invention
For the power problems of current demodulation loop, the object of the present invention is to provide a kind of automatic gain control demodulation circuit, the present invention is applicable to ultra-low power consumption wireless communication field.
Because coherent demodulation circuit is realized complexity, power consumption is generally very big, and the present invention proposes a kind of new incoherent ripple demodulation mode that unloads.By the I after low noise amplifier, frequency mixer down-conversion, filter filtering, Q tetra-road signals, variable gain amplifier in circuit of the present invention (Variable Gain Amplifier, VGA) after amplifying, by squaring circuit, realized and unloaded ripple and demodulation, the gain of VGA is controlled by method provided by the invention.
Technical scheme of the present invention is:
, it is characterized in that comprising variable gain amplifier, demodulation loop, buffer, charge pump; Wherein, the output of described variable gain amplifier and the input of described demodulation loop is connected, the output of described demodulation loop and the input of described buffer is connected, the output of described buffer and the input of described charge pump is connected, the control end of described variable gain amplifier is connected with described electric charge delivery side of pump.
Further, comprise the variable gain amplifier of the input of two groups of difference, difference output, described demodulation loop is for square unloading ripple demodulation loop; Described in two groups, the output of variable gain amplifier is connected with described square of input that unloads ripple demodulation loop respectively, and described in two groups, the gain control end of variable gain amplifier is connected with described electric charge delivery side of pump respectively.
Further, described square is unloaded ripple demodulation loop and comprises current mirror 1, current mirror 2, metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7 and a resistance R, wherein M1, M2, M3, M4 are that the breadth length ratio of measure-alike 4 metal-oxide-semiconductors and M5 is 4 times of M1 breadth length ratio, described M1, M2, M3, the grid of M4 is connected with an output of described variable gain amplifier respectively, and described M1, M2, M3, the source electrode of M4 is connected with ground wire respectively, drain electrode is connected with the source electrode of described M6 respectively, the drain electrode of described M6 is connected with the output of described current mirror 1, and the grid of described M6 is connected with the grid of described M7, the drain electrode of described M7 is connected with the input of described current mirror 1, and the source electrode of described M7 is connected with the drain electrode of described M5, the grid of described M5 is connected with a bias current end, and its source electrode is connected with ground wire, the drain electrode of described M6 is connected with the input of described current mirror 2, the output of described current mirror 2 is connected with one end of described resistance R and the input of described buffer respectively, the other end of described resistance R is connected with ground wire.
Further, described current mirror 1 is the current mirror of PMOS cascade.
Further, described current mirror 2 is the current mirror of PMOS cascade.
Further, described M1, M2, M3, M4, M5 are NMOS pipe.
Further, the difference input that described variable gain amplifier is three-stage cascade, difference output variable gain amplifier.
Further, described buffer consists of two inverter cascades.
Further, described demodulation loop is non-coherent demodulation loop.
Compared with prior art, tool of the present invention has the following advantages:
(1) simple in structure.Main modular of the present invention is that VGA, the novel square of demodulator circuit of basic source degeneration unloads ripple demodulator circuit and charge pump (Charge Pump).Circuit entire area is little, and principle is clear.
(2) super low-power consumption, the present invention adopts, and square to unload ripple demodulation loop power consumption extremely low, and other modules also adopt the simplest structure or improvement as VGA and charge pump as far as possible.Under 1.8V supply voltage, current drain is only 300 μ A left and right, is applicable to long-time radio communication requirement.
(3) low to intermediate frequency accuracy requirement, utilization of the present invention is operated in square complementary characteristic of the MOS device current of saturation region and the square law characteristic of voltage and sine and cosine, little with the big or small correlation of IF-FRE itself, reduced index and the design difficulty requirement of local oscillated signal;
(4) dynamic range is large, and the present invention is large for the power self-regulation scope of input signal, and the signal that is-45dBm～-5dBm for input power range all has good demodulation effect, and dynamic range can reach 40dB and higher in theory.
Accompanying drawing explanation
Fig. 1 is automatic gain control demodulation circuit schematic diagram of the present invention.
Fig. 2 is the VGA circuit diagram of three-stage cascade.
Fig. 3 square unloads ripple demodulator circuit figure.
Fig. 4 is Fig. 1 charge pump circuit figure.
Specific embodiments
The specific embodiments of super low-power consumption of the present invention square demodulation loop and gain control mode is as follows:
Fig. 1 is automatic gain control demodulation circuit schematic diagram of the present invention.The importation of whole loop is VGA, and its input signal is radio-frequency front-end and frequency mixer down-conversion, amplify and filtered I, Q difference Gong Si road signal, and its phase place is respectively 0, pi/2, π, and 3 pi/2s.As shown in Figure 1, VGA amplifies filtered baseband signal with a suitable gain, through a square demodulation module, unload ripple again, the signal unloading after ripple is shaped as and is similar to shorter digital baseband data of square wave time by buffer, buffer consists of two inverter cascades, obtains the demodulating data that duty ratio in theory is finally 50%.The automatic control process of loop gain mainly completes by charge pump.If the gain of VGA is too high, may have partial data 0 be demodulated into 1 or the duty ratio of demodulating data surpass 50%, vice versa.The effect of charge pump is to detect whether the duty ratio of output data is 50%.If output data duty cycle is less than 50%, mean that VGA gain is too low, in charge pump, the ON time of NMOS will be short compared with PMOS, on the whole, the integrating capacitor of charge pump will be charged gradually, voltage in integrating capacitor will raise, and this voltage is the gain control signal V_Ctrl of VGA, therefore VGA gain will become large; Vice versa.After the output voltage stabilization of charge pump, it is stable that system gain also reaches, thereby realize the gain control of loop.
Fig. 2 is the general structure of three-stage cascade VGA.VGA amplifying signal makes it have the demodulated module demodulation of enough amplitudes, and the correct control of its gain size directly has influence on the judgement of demodulation module to data " 1 ", " 0 ".In the present invention, adopt the structure of three-stage cascade VGA to improve cascade gain, and by corresponding gain control loop, the gain of VGA is controlled automatically.The gain providing of VGA is very large, and between every grade of VGA, needing affects the DC point of late-class circuit by capacitance AC coupled to prevent prime DC shift.Thereby it is to change its equivalent resistance and realize by changing the grid voltage of input stage source feedback metal-oxide-semiconductor that the gain of every grade of VGA is controlled, every grade of VGA is the highest provides the approximately gain of 0～20dB, integral body provides approximately 0～60dB gain altogether, can meet the dynamic range of input 40dB.Whole VGA's is simple in structure, with small electric stream, realizes high-gain.
Figure 3 shows that novel square of schematic diagram that unloads ripple demodulator circuit, for ease of this circuit working principle is described, with f
crepresent to receive the carrier frequency after signal down-conversion, differing between the I after mixing low-pass filtering, Q difference four tunnels can be expressed as for pi/2 ，Zhe tetra-road signals
v
l＝V
mA
scog(2πf
0t)；
v2＝V
mA
scos(2πf
ct+π);
Wherein, A
mthe signal amplitude of expression after VGA amplifies, A
srepresent binary data signal (" 1 " or " 0 ").Above-mentioned 4 road ac small signals are carried in the NMOS pipe M1～M4 grid voltage that works in saturation region, and electric current is separately sued for peace:
The conduction factor of input pipe M1～M4 that wherein K is same size, V
0poor for M1～M4 direct current grid voltage biasing and threshold voltage.I
dmiddle first is flip-flop, and second portion has comprised binary data signal A
salternating component.The NMOS pipe M5 of 4 times that another design breadth length ratio is M1, and itself and M1～M4 are biased under identical DC environment, the bank tube altogether of connecting on M1～M4 and M5 equates with M1～M4 direct current sum to guarantee M5 direct current.Electric current after the same M1 of the electric current of M5～M4 summation is connected by PMOS common-source common-gate current mirror, like this, at the tie point of M1～M4 branch road and PMOS current mirror, the electric current I of M1～M4 pipe
dwill with M5 tube current
differ from, thereby obtain electric current I
daC portion I_DATA, that is 2KV
m 2a
s 2.This AC portion copies and acts in resistance R through the PMOS current mirror of cascade, obtains the restituted signal after ripple that unloads tentatively.This signal, through the data buffer shaping of the inverter formation of cascade, obtains restituted signal finally.For reducing dimensional mismatch and metal-oxide-semiconductor second-order effects, to asking the long value of grid of square input pipe larger.Resistance R value is larger, and whole circuit can be obtained the enough discriminations to primary signal 0,1 under lower electric current, thereby power consumption is extremely low.
Fig. 4 is electric charge pump structure, and its effect is the duty ratio that detects 0,1 data after demodulation, thus the gain of FEEDBACK CONTROL VGA.For saving power consumption, charge pump is taked the simplest structure, but can't acute exacerbation affect circuit performance.(the 1+ α) of the pull-down current that the pull-up current of supposing charge pump PMOS is NMOS doubly, for a burning voltage in integrating capacitor, charging interval is only 1/ (the 1+ α) of discharge time, this means in the demodulating data after loop stability, 1 length is 1/ (1+ α) with respect to 0 length, and duty ratio is 1/ (2+ α) in other words.After the duty cycle deviations that can correctly sample in clock and data recovery (Clock Data Recovery, the CDR) Circuit theory that connects be 25%, this means, can tolerate the current mismatch of charge pump 100%.Visible, gain control method provided by the invention is less demanding to the currents match of charge pump, has simplified charge pump design, thereby can its power consumption compression is extremely low.
In a word, novel square of the present invention design unloads the ingenious complementary characteristic of sine and cosine functions square that utilized of ripple demodulation module and has removed carrier wave.Whole demodulating process is very succinct, and all expansion of the requirement based on super low-power consumption of the design of circuit, and the power consumption of whole demodulation module is approximately 300 μ A.It should be noted that this square of demodulation method that unloads ripple do not have direct requirement for IF-FRE, this is the requirement greatly having reduced for phase-locked loop frequency precision, thereby gives the larger design margin that stays of other modules, comprises power consumption.
Claims (7)
1. an automatic gain control demodulation circuit, is characterized in that the variable gain amplifier, demodulation loop, buffer, the charge pump that comprise that two groups of difference inputs, difference are exported, wherein, described demodulation loop is for square unloading ripple demodulation loop, the input that described in two groups, the output of variable gain amplifier all unloads ripple demodulation loop with described square is connected, described square unload the output of ripple demodulation loop and the input of described buffer is connected, the output of described buffer and the input of described charge pump is connected, the control end of variable gain amplifier is all connected with described electric charge delivery side of pump described in two groups, described square is unloaded ripple demodulation loop and comprises current mirror 1, current mirror 2, metal-oxide-semiconductor M1, M2, M3, M4, M5, M6, M7 and a resistance R, wherein M1, M2, M3, M4 are that the breadth length ratio of measure-alike 4 metal-oxide-semiconductors and M5 is 4 times of M1 breadth length ratio, described M1, M2, M3, the grid of M4 is connected with an output of described variable gain amplifier respectively, and described M1, M2, M3, the source electrode of M4 is connected with ground wire respectively, drain electrode is connected with the source electrode of described M6 respectively, the drain electrode of described M6 is connected with the output of described current mirror 1, and the grid of described M6 is connected with the grid of described M7, the drain electrode of described M7 is connected with the input of described current mirror 1, and the source electrode of described M7 is connected with the drain electrode of described M5, the grid of described M5 is connected with a bias current end, and its source electrode is connected with ground wire, the drain electrode of described M6 is connected with the input of described current mirror 2, the output of described current mirror 2 is connected with one end of described resistance R and the input of described buffer respectively, the other end of described resistance R is connected with ground wire.
2. circuit as claimed in claim 1, is characterized in that described current mirror 1 is for the current mirror of PMOS cascade.
3. circuit as claimed in claim 1, is characterized in that described current mirror 2 is for the current mirror of PMOS cascade.
4. circuit as claimed in claim 1, is characterized in that described M1, M2, M3, M4, M5 are NMOS pipe.
5. circuit as claimed in claim 1, is characterized in that described variable gain amplifier is difference input, the difference output variable gain amplifier of three-stage cascade.
6. circuit as claimed in claim 1, is characterized in that described buffer consists of two inverter cascades.
7. circuit as claimed in claim 1, is characterized in that described demodulation loop is non-coherent demodulation loop.
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| CN201010286327.1A CN102403971B (en) | 2010-09-17 | 2010-09-17 | Automatic gain control demodulation circuit |
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|---|---|---|---|
| CN201010286327.1A CN102403971B (en) | 2010-09-17 | 2010-09-17 | Automatic gain control demodulation circuit |
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| CN102403971A CN102403971A (en) | 2012-04-04 |
| CN102403971B true CN102403971B (en) | 2014-02-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5825239A (en) * | 1997-05-06 | 1998-10-20 | Texas Instruments Incorporated | Peak detector for automatic gain control |
| CN1901401A (en) * | 2006-07-07 | 2007-01-24 | 广东鼎威经济发展有限公司 | Realizing two-way conversion integrated circuit between RF signals and medium frequency wired signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3097605B2 (en) * | 1997-06-06 | 2000-10-10 | 日本電気株式会社 | AGC circuit |
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2010
- 2010-09-17 CN CN201010286327.1A patent/CN102403971B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5825239A (en) * | 1997-05-06 | 1998-10-20 | Texas Instruments Incorporated | Peak detector for automatic gain control |
| CN1901401A (en) * | 2006-07-07 | 2007-01-24 | 广东鼎威经济发展有限公司 | Realizing two-way conversion integrated circuit between RF signals and medium frequency wired signal |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平10-341267A 1998.12.22 |
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