CN102412198A - Semiconductor device fabrication method - Google Patents
Semiconductor device fabrication method Download PDFInfo
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- CN102412198A CN102412198A CN2011103353158A CN201110335315A CN102412198A CN 102412198 A CN102412198 A CN 102412198A CN 2011103353158 A CN2011103353158 A CN 2011103353158A CN 201110335315 A CN201110335315 A CN 201110335315A CN 102412198 A CN102412198 A CN 102412198A
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Abstract
The invention discloses a semiconductor device fabrication method, which ensures that the depths of a redundant metal trench and an auxiliary pattern redundant metal trench are smaller than the depth of a metal wire trench, so that the heights of a finally formed redundant metal line and a finally formed auxiliary pattern redundant metal line are smaller than the height of a metal wire. Compared with the prior art, the semiconductor device fabrication method reduces the thicknesses (heights) of the redundant metal line and the auxiliary pattern redundant metal line, consequently, an etching process window can be effectively enlarged, and moreover, the coupling capacitance in the metal layers filled with the redundant metal line and the auxiliary pattern redundant metal line and the coupling capacitance between the metal layers can be decreased.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of manufacturing method of semiconductor device.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain through etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes the dual damascene process of through hole (also claiming contact hole) and plain conductor simultaneously.Specifically; Single damascene structure (also claiming single inlay structure) only is to change the production method of single-layer metal lead into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled); Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together.The common method of making dual-damascene structure generally has following several kinds: all-pass hole precedence method (Full VIA First), half via-first method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; In dielectric layer 110, form metallic channel through photoetching and etching technics then; Depositing metal layers subsequently, said metal level are filled in the metallic channel and on said dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technology and remove the metal on the said dielectric layer 110, thereby in said metallic channel, processed plain conductor 140.
As stated, in Damascus technics, need utilize chemical mechanical milling tech, be embedded in the plain conductor 140 in the dielectric layer 110 with final formation.Yet,, therefore can cause the depression of not expecting (dishing) and corrode (erosion) phenomenon the selectivity of grinding because the rate that removes of metal and dielectric layer material is generally inequality.Depression occurs in metal often and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is thin excessively.Depression and erosion are subject to the structure of figure and the density influence of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, the method for solution is to fill the pattern density homogenizing that redundant metal line pattern makes domain at the white space of domain, thereby also forms redundant metal wire (dummy metal) 150 when in dielectric layer 110, forming plain conductor 140, and is as shown in Figure 2.But,, but introduced in the extra metal level inevitably and the coupling capacitance of metal interlevel though redundant metal wire has improved the uniformity of pattern density.
In order to reduce the negative effect that extra coupling capacitance brings device, when the redundant metal of design, to reduce the filling quantity of redundant metal as far as possible, and make main graphic (plain conductor figure) big as far as possible with redundant intermetallic distance.Yet the excessive pattern density of regional area that can cause again of the spacing of main graphic and redundant metal is inhomogeneous, influences the regional area flatness of chemical mechanical milling tech.Under given live width condition, the depth of focus of various bargraphss (DOF) process window has following relationship: intensive lines＞half intensive lines＞isolated lines.Utilize this relation, increase the process window that auxiliary pattern can enlarge half intensive lines and isolated lines at half intensive lines and isolated lines side.That is, auxiliary pattern can enlarge the lithographic process window of half intensive lines and isolated lines, improves the regional area flatness of the cmp of metal, but also can cause in the bigger metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor device, to enlarge lithographic process window effectively and to reduce redundant metal wire and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form dielectric layer;
On said redundant metal area and the redundant metal area of auxiliary pattern, form hard mask layer;
With said hard mask layer is the said dielectric layer of mask etching, and to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
Optional, in described manufacturing method of semiconductor device, the hard mask layer thickness on the redundant metal area of said auxiliary pattern is identical with the hard mask layer thickness on the said redundant metal area.The degree of depth of the redundant metallic channel of said auxiliary pattern is identical with the degree of depth of said redundant metallic channel.
Optional, in described manufacturing method of semiconductor device, hard mask layer thickness and the hard mask layer thickness on the said redundant metal area on the redundant metal area of said auxiliary pattern are inequality.The degree of depth of the redundant metallic channel of said auxiliary pattern and the degree of depth of said redundant metallic channel are inequality.
Optional, in described manufacturing method of semiconductor device, form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: the correspondence position at said metallic channel forms through hole.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form dielectric layer;
On said dielectric layer, form hard mask layer; And the said hard mask layer of etching; On redundant metal area, to form the redundant groove of hard mask, on the redundant metal area of auxiliary pattern, form hard mask auxiliary pattern groove, on the nonredundancy metal area, form hard mask metallic channel; Said hard mask metallic channel exposes said dielectric layer, and the degree of depth of said hard mask metallic channel is greater than the degree of depth of redundant groove of hard mask and hard mask auxiliary pattern groove;
Remaining hard mask layer of etching and dielectric layer form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
Optional, in described manufacturing method of semiconductor device, form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: the correspondence position at said metallic channel forms through hole.
The present invention makes the degree of depth of the degree of depth of redundant metallic channel and the redundant metallic channel of auxiliary pattern less than metallic channel; The height of therefore final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor; Compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern; Can enlarge lithographic process window effectively, and reduce the redundant metal wire of redundant metal wire and auxiliary pattern and fill in the metal level of introducing the coupling capacitance with metal interlevel.
In addition; The present invention makes the degree of depth of the degree of depth of redundant metallic channel less than the redundant metallic channel of auxiliary pattern; Thereby the height of redundant metal wire that makes formation is less than the height of the redundant metal wire of auxiliary pattern, further reduces the redundant metal wire of auxiliary pattern and fills in the metal level of introducing the coupling capacitance with metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 A～3F is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention one;
Fig. 4 A～4F is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention two;
Fig. 5 A～5G is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention three;
Fig. 6 A～6F is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention four.
Fig. 7 A～7G is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of the embodiment of the invention five.
Embodiment
Mention that in background technology though the redundant metal wire of redundant metal wire and auxiliary pattern has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows that the relative area that reduces metal can reduce electric capacity with increase intermetallic distance.In view of this; The present invention makes the degree of depth of the degree of depth of redundant metallic channel and the redundant metallic channel of auxiliary pattern less than metallic channel; The height of therefore final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor; Compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern, can enlarge lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Manufacturing method of semiconductor device below in conjunction with generalized section proposes the present invention is respectively done further to specify.
Embodiment one
Introduce the manufacturing process of single Damascus metal interconnect structure in detail below in conjunction with Fig. 3 A～3F; The redundant metallic channel that present embodiment forms is identical with the degree of depth of the redundant metallic channel of auxiliary pattern, thereby makes the redundant metal wire of formation identical with the height of the redundant metal wire of auxiliary pattern.
Shown in Fig. 3 A; At first; Semiconductor substrate 300 is provided; Said Semiconductor substrate 300 comprises redundant metal area 302, the redundant metal area 303 of auxiliary pattern and nonredundancy metal area 301, that is, the semiconductor substrate region except the redundant metal area 303 of redundant metal area 302 and auxiliary pattern is a nonredundancy metal area 301.Wherein, Be formed with metal line in the said Semiconductor substrate 300; Because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 300, forms metal line, but those skilled in the art are still this and know.
Shown in Fig. 3 B, then, on said Semiconductor substrate 300, form dielectric layer 310, said dielectric layer 310 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of conduction fast.Preferable; It is black diamond (black diamond that said dielectric layer 310 adopts the trade mark of Material Used (Applied Materials) company; BD) silicon oxide carbide; Perhaps adopt the Coral material of Novellus company, perhaps adopt again and utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.
In other embodiments of the invention; Before forming dielectric layer 310 on the said Semiconductor substrate 300; Also can form etching stop layer (not shown) earlier; Said etching stop layer can be used for preventing metal diffusing in the metal line in dielectric layer 310, and said in addition etching stop layer can prevent that also the metal line in the Semiconductor substrate 300 is etched in follow-up etching process of carrying out.The material of said etching stop layer for example is a silicon nitride, and the dielectric layer of itself and follow-up formation has good adhesive force property.
Shown in Fig. 3 C, on said redundant metal area 302 and the redundant metal area 303 of auxiliary pattern, form hard mask layer 330.Detailed; Photoetching process capable of using forms patterned light blockage layer on dielectric layer 310; Be that mask carries out etching technics with said patterned light blockage layer subsequently; Can remove the hard mask layer on the said nonredundancy metal area 301, and only keep the hard mask layer on said redundant metal area 302 and the redundant metal area 303 of auxiliary pattern, remove patterned light blockage layer subsequently again.In the present embodiment, the hard mask layer thickness on the redundant metal area 303 of said auxiliary pattern is identical with the hard mask layer thickness on the redundant metal area 302, so, can make the degree of depth of auxiliary pattern redundancy metallic channel of follow-up formation identical with the degree of depth of redundant metallic channel.
Shown in Fig. 3 D; With hard mask layer 330 is mask etching dielectric layer 310; To form redundant metallic channel 312a on the redundant metal area 302, on the redundant metal area 303 of auxiliary pattern, to form redundant metallic channel 313a of auxiliary pattern and the formation of the correspondence position on nonredundancy metal area 301 metallic channel 311a; Owing to formed hard mask layer 330 on the redundant metal area 303 of redundant metal area 302 and auxiliary pattern; Therefore through after the same etch step, the degree of depth of redundant metallic channel 313a of the auxiliary pattern of formation and redundant metallic channel 312a is less than the degree of depth of metallic channel 311a.The degree of depth of the redundant metallic channel 313a of auxiliary pattern is identical with the degree of depth of redundant metallic channel 312a in the present embodiment; Particularly; The height of the redundant metallic channel 313a of said redundant metallic channel 312a and auxiliary pattern can change according to concrete technology accordingly, and the present invention also will not limit this.
Shown in Fig. 3 E; Then, depositing metal layers 320 in said redundant metallic channel 312a, the redundant metallic channel 313a of auxiliary pattern and metallic channel 311a is because the characteristic of depositing operation; Also can deposit metal on this process medium layer 310, the material of wherein said metal level 320 is a copper.
Shown in Fig. 3 F; Then; Carry out cmp (CMP) technology until the surface that exposes said dielectric layer 310; In redundant metallic channel 312a, to form redundant metal wire 322, in the redundant metallic channel 313a of auxiliary pattern, form the redundant metal wire 323 of auxiliary pattern, in metallic channel 311a, to form plain conductor 321; The height of said redundant metal wire 322 and the redundant metal wire 323 of auxiliary pattern is less than the height 321 of plain conductor, and redundant metal wire 322 is identical with the height of the redundant metal wire 323 of auxiliary pattern.
Compared with prior art; The present invention has reduced the height (thickness) of redundant metal wire 322 and the redundant metal wire 323 of auxiliary pattern, thereby enlarges lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment two
Present embodiment combines Fig. 4 A～4F to introduce the manufacturing process of single Damascus metal interconnect structure in detail; Wherein, The degree of depth (highly) of redundant metallic channel and the redundant metallic channel of auxiliary pattern is inequality, thereby makes that the height of final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is also inequality.
Shown in Fig. 4 A; At first; Semiconductor substrate 400 is provided; Said Semiconductor substrate 400 comprises redundant metal area 402, the redundant metal area 403 of auxiliary pattern and nonredundancy metal area 401, wherein removes redundant metal area 402 and is nonredundancy metal area 401 with semiconductor substrate region the auxiliary pattern redundancy metal area 403.
Shown in Fig. 4 B, then, on said Semiconductor substrate 400, form dielectric layer 410.
Shown in Fig. 4 C, then, on said redundant metal area 402 and the redundant metal area 403 of auxiliary pattern, form hard mask layer 430.In the present embodiment, hard mask layer thickness and the hard mask layer thickness on the redundant metal area 402 on the redundant metal area 403 of auxiliary pattern are inequality, so, can make the degree of depth of the degree of depth and redundant metallic channel of auxiliary pattern redundancy metallic channel of follow-up formation inequality.For example; Can on dielectric layer 410, form hard mask film earlier; Utilize etching technics to remove the hard mask film on the nonredundancy metal area 401 then; Utilize another etching technics again, remove the hard mask layer film of redundant metal area 402 top thickness, can make hard mask layer thickness on the redundant metal area 403 of auxiliary pattern greater than the hard mask layer thickness on the redundant metal area 402.
Shown in Fig. 4 D; With hard mask layer 430 is mask etching dielectric layer 410; To form redundant metallic channel 412a on the redundant metal area 402, on the redundant metal area 403 of auxiliary pattern, to form redundant metallic channel 413a of auxiliary pattern and the formation of the correspondence position on nonredundancy metal area 401 metallic channel 411a; Owing to formed hard mask layer 430 on the redundant metal area 403 of redundant metal area 402 and auxiliary pattern; Therefore, through after the same etch step, the degree of depth of redundant metallic channel 413a of the auxiliary pattern of formation and redundant metallic channel 412a is less than the degree of depth of metallic channel 411a; And the degree of depth of the redundant metallic channel 413a of auxiliary pattern is less than the degree of depth of redundant metallic channel 412a.
Shown in Fig. 4 E, then, on said redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern and metallic channel 411a and dielectric layer 410 in depositing metal layers 420.
Shown in Fig. 4 F; Then; Carry out cmp (CMP) technology until the surface that exposes said dielectric layer 410; In redundant metallic channel 412a, to form redundant metal wire 422, in the redundant metallic channel 413a of auxiliary pattern, form the redundant metal wire 423 of auxiliary pattern, in metallic channel 411a, to form plain conductor 421; The height of said redundant metal wire 422 and the redundant metal wire 423 of auxiliary pattern is less than the height 421 of plain conductor, and the height of redundant metal wire 422 is less than the height of the redundant metal wire 423 of auxiliary pattern.
Compare with embodiment one; The degree of depth (highly) of the redundant metallic channel 413a of redundant metallic channel 412a that forms in the present embodiment and auxiliary pattern is inequality; Thereby make that the redundant metal wire 422 that forms is also inequality with the height of the redundant metal wire 423 of auxiliary pattern; Further reduce the redundant metal wire of redundant metal wire and auxiliary pattern and filled in the metal level of introducing and the coupling capacitance of metal interlevel, and enlarged lithographic process window.
Embodiment three
Present embodiment combines Fig. 5 A～5G to introduce the manufacturing process of the dual damascene metal interconnect structure of through hole elder generation etching in detail; Wherein, Redundant metallic channel is identical with the degree of depth (highly) of the redundant metallic channel of auxiliary pattern, thereby makes the final redundant metal wire that forms also identical with the height of the redundant metal wire of auxiliary pattern.
Shown in Fig. 5 A; At first; Semiconductor substrate 500 is provided; Said Semiconductor substrate 500 comprises redundant metal area 502, the redundant metal area 503 of auxiliary pattern and nonredundancy metal area 501, wherein removes redundant metal area 502 and is nonredundancy metal area 501 with semiconductor substrate region the auxiliary pattern redundancy metal area 503.
Shown in Fig. 5 B, then, on said Semiconductor substrate 500, form dielectric layer 510.
Shown in Fig. 5 C, then, on said redundant metal area 502 and the redundant metal area 503 of auxiliary pattern, form hard mask layer 530.
Shown in Fig. 5 D, then, the dielectric layer on the said nonredundancy metal area 501 of etching forms through hole 511b in the position of metallic channel to be formed.
Shown in Fig. 5 E; Then; With hard mask layer 530 is mask etching dielectric layer 510, and to form the redundant metallic channel 513a of redundant metallic channel 512a and auxiliary pattern, the correspondence position at said through hole 511b forms metallic channel 511a simultaneously; The degree of depth of the redundant metallic channel 513a of said auxiliary pattern equals the degree of depth of redundant metallic channel 512a, and the degree of depth of redundant metallic channel 513a of said auxiliary pattern and redundant metallic channel 512a is less than the degree of depth of metallic channel 511a.
Shown in Fig. 5 F, then, depositing metal layers 520 in said redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern, metallic channel 511a and through hole 511b and on the dielectric layer 510.
Shown in Fig. 5 G; Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer 520; To form redundant metal wire 522, the redundant metal wire 523 of auxiliary pattern and plain conductor 521; The redundant metal wire 523 of said auxiliary pattern is identical with the height of redundant metal wire 522, and the height of redundant metal wire 523 of said auxiliary pattern and redundant metal wire 522 is less than the height of said plain conductor 521.
Compare with previous embodiment; Present embodiment forms through hole 511b earlier and then forms redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern and metallic channel 511a; And the degree of depth of redundant metallic channel 513a of auxiliary pattern and redundant metallic channel 512a is less than the degree of depth of metallic channel 511a; Thereby the height that makes redundant metal wire 523 of auxiliary pattern and redundant metal wire 522 is all less than the height of plain conductor 521; Reduced the height (thickness) of redundant metal wire 522 and the redundant metal wire 523 of auxiliary pattern; Fill in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduce the redundant metal wire of redundant metal wire and auxiliary pattern effectively, and enlarged lithographic process window.
Embodiment four
Present embodiment combines Fig. 6 A～6F to introduce the manufacturing process of the hard mask list of autoregistration formula Damascus metal interconnect structure in detail, wherein, the degree of depth (highly) of redundant metallic channel and auxiliary pattern redundancy metallic channel can be identical also can be inequality.
Shown in Fig. 6 A, at first, Semiconductor substrate 600 is provided, said Semiconductor substrate 600 comprises redundant metal area 602, the redundant metal area 603 of auxiliary pattern and nonredundancy metal area 601.
Shown in Fig. 6 B, then, on said Semiconductor substrate 600, form dielectric layer 610 successively.
Shown in Fig. 6 C, subsequently, on dielectric layer 610, form hard mask layer; And etching hard mask layer; On redundant metal area 602, to form the redundant groove 632a of hard mask, on the redundant metal area 603 of auxiliary pattern, form hard mask auxiliary pattern groove 633a, on nonredundancy metal area 601, form hard mask metallic channel 631a; Said hard mask metallic channel 631a exposes the surface of dielectric layer 610; And the degree of depth of hard mask metallic channel 631a is greater than the degree of depth of hard mask redundancy groove 632a and hard mask auxiliary pattern groove 633a, that is, redundant groove 632a of hard mask and hard mask auxiliary pattern groove 633a do not expose the surface of dielectric layer 610.
Shown in Fig. 6 D; Then; Remaining hard mask layer of etching and dielectric layer 610; Form redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a, the degree of depth of redundant metallic channel 613a of said auxiliary pattern and redundant metallic channel 612a is less than the degree of depth of said metallic channel 611a.
Shown in Fig. 6 E, then, depositing metal layers 620 in said redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a and on the dielectric layer.
Shown in Fig. 6 F; Then; Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer; To form redundant metal wire 622, the redundant metal wire 623 of auxiliary pattern and plain conductor 621, the height of the redundant metal wire 623 of said auxiliary pattern is less than the height of said redundant metal wire 622, and the height of said redundant metal wire 622 is less than the height of said plain conductor 621.
The degree of depth of present embodiment through making hard mask metallic channel 631a is greater than the degree of depth of redundant groove 632a of hard mask and hard mask auxiliary pattern groove 633a; Thereby the height that makes redundant metal wire 623 of auxiliary pattern and redundant metal wire 622 is all less than the height of plain conductor 621; Reduced the height (thickness) of redundant metal wire 622 and the redundant metal wire 623 of auxiliary pattern; Reduce the redundant metal wire of redundant metal wire and auxiliary pattern and filled in the metal level of introducing and the coupling capacitance of metal interlevel, and enlarged lithographic process window.
Embodiment five
Present embodiment combines Fig. 7 A～7G to introduce the manufacturing process of the hard mask dual damascene of autoregistration formula metal interconnect structure in detail; Wherein, Redundant metallic channel is identical with the degree of depth (highly) of the redundant metallic channel of auxiliary pattern, thereby the height of feasible redundant metal wire that forms and the redundant metal wire of auxiliary pattern is inequality.
Shown in Fig. 7 A, at first, Semiconductor substrate 700 is provided, said Semiconductor substrate 700 comprises redundant metal area 702, the redundant metal area 703 of auxiliary pattern and nonredundancy metal area 701.
Shown in Fig. 7 B, on said Semiconductor substrate 700, form dielectric layer 710.
Shown in Fig. 7 C; Subsequently; On dielectric layer 710, form hard mask layer, and the etching hard mask layer, on redundant metal area 702, to form the redundant groove 732a of hard mask; On the redundant metal area 703 of auxiliary pattern, form hard mask auxiliary pattern groove 733a; On the correspondence position of nonredundancy metal area 701, form hard mask metallic channel 731a, said hard mask metallic channel 731a exposes the surface of dielectric layer 710, and the degree of depth of hard mask metallic channel 731a is greater than the degree of depth of redundant groove 732a of hard mask and hard mask auxiliary pattern groove 733a.
Shown in Fig. 7 D, the dielectric layer on the said nonredundancy metal area 701 of etching forms through hole 711b with the correspondence position at said hard mask metallic channel 731a.
Shown in Fig. 7 E; Then; With said hard mask layer is mask etching dielectric layer 710, and to form the redundant metallic channel 713a of redundant metallic channel 712a and auxiliary pattern, the while is at the correspondence position metallic channel 711a of through hole 711b; The degree of depth of the redundant metallic channel 713a of auxiliary pattern equals the degree of depth of redundant metallic channel 712a, and the degree of depth of redundant metallic channel 713a of said auxiliary pattern and redundant metallic channel 712a is all less than the degree of depth of metallic channel 711a.
Shown in Fig. 7 F, then, depositing metal layers 720 in said redundant metallic channel 712a, the redundant metallic channel 713a of auxiliary pattern, metallic channel 711 and through hole 711b and on the dielectric layer 710.
Shown in Fig. 7 G; Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer 720; To form redundant metal wire 722, the redundant metal wire 723 of auxiliary pattern and plain conductor 721; The redundant metal wire 723 of said auxiliary pattern is identical with the height of redundant metal wire 722, and the height of redundant metal wire 723 of said auxiliary pattern and redundant metal wire 722 is less than the height of said plain conductor 721.
Compare with embodiment four; Present embodiment forms through hole 711b earlier and then forms redundant metallic channel 712a, the redundant metallic channel 713a of auxiliary pattern and metallic channel 711a; And reduced the height (thickness) of redundant metal wire 722 and the redundant metal wire 723 of auxiliary pattern; Fill in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduce the redundant metal wire of redundant metal wire and auxiliary pattern effectively, enlarged lithographic process window.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses all is the difference with other embodiment, the reference mutually of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for the purpose of convenience, each embodiment of aid illustration the present invention lucidly.
In addition, although abovely specified the present invention with a plurality of embodiment respectively, those skilled in the art can also carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form dielectric layer;
On said redundant metal area and the redundant metal area of auxiliary pattern, form hard mask layer;
With said hard mask layer is the said dielectric layer of mask etching, and to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
2. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the hard mask layer thickness on the redundant metal area of said auxiliary pattern is identical with the hard mask layer thickness on the said redundant metal area.
3. manufacturing method of semiconductor device as claimed in claim 2 is characterized in that, the degree of depth of the redundant metallic channel of said auxiliary pattern is identical with the degree of depth of said redundant metallic channel.
4. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, hard mask layer thickness and the hard mask layer thickness on the said redundant metal area on the redundant metal area of said auxiliary pattern are inequality.
5. manufacturing method of semiconductor device as claimed in claim 4 is characterized in that, the degree of depth of the redundant metallic channel of said auxiliary pattern and the degree of depth of said redundant metallic channel are inequality.
6. like any described manufacturing method of semiconductor device in the claim 1 to 5, it is characterized in that form before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, also comprise: the correspondence position at said metallic channel forms through hole.
7. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and said Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On said Semiconductor substrate, form dielectric layer;
On said dielectric layer, form hard mask layer; And the said hard mask layer of etching; On redundant metal area, to form the redundant groove of hard mask, on the redundant metal area of auxiliary pattern, form hard mask auxiliary pattern groove, on the nonredundancy metal area, form hard mask metallic channel; Said hard mask metallic channel exposes said dielectric layer, and the degree of depth of said hard mask metallic channel is greater than the degree of depth of redundant groove of hard mask and hard mask auxiliary pattern groove;
Remaining hard mask layer of etching and dielectric layer form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, and the degree of depth of redundant metallic channel of said auxiliary pattern and redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes said dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of redundant metal wire of said auxiliary pattern and redundant metal wire is less than the height of said plain conductor.
8. manufacturing method of semiconductor device as claimed in claim 7 is characterized in that, forms before redundant metallic channel, the redundant metallic channel of auxiliary pattern and the metallic channel, and also comprise: the correspondence position at said metallic channel forms through hole.
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| CN201110335315.8A Active CN102412198B (en) | 2011-10-29 | 2011-10-29 | Semiconductor device fabrication method |
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| CN111564422A (en) * | 2020-04-08 | 2020-08-21 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof, semiconductor device and chip |
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20080315365A1 (en) * | 2007-06-20 | 2008-12-25 | Elpida Memory, Inc. | Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20080315365A1 (en) * | 2007-06-20 | 2008-12-25 | Elpida Memory, Inc. | Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111564422A (en) * | 2020-04-08 | 2020-08-21 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof, semiconductor device and chip |
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