CN102412811A - Adjustable non-overlapping clock signal generating method and generator - Google Patents
Adjustable non-overlapping clock signal generating method and generator Download PDFInfo
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Abstract
The invention discloses an adjustable non-overlapping clock signal generating method and generator, and the method is characterized in that a square signal generated by an oscillating circuit is respectively output to at least 2 duty-ratio regulating circuits; duty-ratio regulation of the square signal is achieved by each duty-ratio regulating circuit through control signals with different duty ratios, thus output signals with different duty ratios of the at least two circuits are obtained, and the output signals with different duty ratios are non-overlapping clock signals. The adjustable non-overlapping clock signal generator provided by the invention has the characteristics of adjustable duty ratio and wide frequency output range.
Description
Technical field
The present invention relates to a kind of non-overlapping clock generator, be specifically related to a kind of adjustable non-overlapping clock method for generation and generator.
Background technology
Switching capacity (SC) technology is the focus in the cmos vlsi.Switched-capacitor circuit not only is widely used in analog (like filter, switching capacity DC-DC transducer and voltage comparator etc.), also penetrates into mixed signal module (like analog to digital converter, sigma-delta modulator and sampled analog structure).Non-overlapped clock generator then is used to the switch that control capacitance discharges and recharges, and is one of nucleus module of switched-capacitor circuit.Traditional non-overlapping clock generator design is general to be adopted with/NOR gate and chain of inverters and forms delay unit.Although researcher has in the past proposed different methods for designing to the non-overlapping clock generator, clock circuit module wherein mostly is independent of input generator, all can only be shaping circuit therefore.In these circuit, the definition non-overlapping clock is to (clk1, the clk2) parameter of attribute is such as duty ratio, non-overlapped time interval Δ τ [clk1, clk2] with all depend on the formation of delay cell rising/fall time.In case circuit is integrated, these parameters can not change.In addition, in the concept field of this kind traditional design, because the delay cell limited in number arrives high-frequency application during tandem circuit is only limited to.Have the researcher to propose to be suitable for the circuit design that low frequency is used, but required number of transistors reach up to a hundred.The researcher who has has recognized oscillator and the incorporate importance of clock, proposes utilization digital controlled oscillator (DCO) structure and realizes occurring to the overall process that non-overlapping clock produces from oscillator signal.But, in order to control the right attribute of non-overlapping clock, adopted DCO, level translator and some other digital circuit, make circuit structure become very complicated.
Summary of the invention
Technical problem to be solved by this invention provides a kind of adjustable non-overlapping clock method for generation and generator, and it has EDM Generator of Adjustable Duty Ratio and the wide characteristics of frequency output area.
For addressing the above problem, the present invention realizes through following technical scheme:
A kind of adjustable non-overlapping clock method for generation of the present invention; The square-wave signal that oscillating circuit produces is input to respectively at least 2 tunnel duty cycle adjustment circuit; Per 1 tunnel duty cycle adjustment circuit is realized the duty cycle adjustment of square-wave signal under the effect of different duty control signal; Obtain thus at least 2 the tunnel have different duty the output signal, these output signals with different duty are the non-overlapping clock signal.
Above-mentioned per 1 tunnel duty cycle adjustment circuit constitutes with the control inverter by 2 input inverters that form parallel connection each other; Under the adjusting of the duty cycle control signal of control inverter input, the overturn point that changes input inverter realizes importing the duty cycle adjustment of square-wave signal from the square-wave signal of input inverter input input.
Above-mentioned clock method also is included in middle inverter that 2 of serial connections on the output of input inverter form series connection each other and exports the steps that inverter improves duty cycle adjustment circuit output signal waveform.
Above-mentioned oscillating circuit mainly is made up of input control circuit and the end to end delay unit of N level, and wherein per 1 grade of delay unit comprises the transmission gate and vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is through input control circuit adjustment back formation complementary voltage signal, the voltage that this complementary voltage voltage of signals size is power source voltage and input voltage signal poor.Above-mentioned input voltage signal and complementary voltage signal send into respectively the transmission gate of per 1 grade of delay unit 2 control ends, let all transmission gates between conducting and cut-off state, change, and the square-wave signal that impels delay unit to produce to have the broadband tunable range.
A kind of adjustable non-overlapping clock generator of the present invention comprises the clock generator body.This clock generator body mainly is made up of oscillating circuit and 2 tunnel EDM Generator of Adjustable Duty Ratio circuit at least; Wherein the EDM Generator of Adjustable Duty Ratio circuit more than 2 road or 2 tunnel is parallel with one another, and the input of per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit all links to each other with the output of oscillating circuit; Have a duty cycle adjustment end on per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit, different duty cycle control signals gets into the clock generator body from different EDM Generator of Adjustable Duty Ratio circuit; The output of duty cycle adjustment circuit forms the output of clock generator body.
In the such scheme, per 1 tunnel duty cycle adjustment circuit constitutes with the control inverter by 2 input inverters that form parallel connection each other; Wherein the input of input inverter forms the input of oscillating circuit, and the input of control inverter forms the duty cycle adjustment end, link to each other with the output of the control inverter output of this duty cycle adjustment circuit of back formation of input inverter.
In order to improve the waveform of output signal, above-mentioned per 1 tunnel duty cycle adjustment circuit also includes 2 the middle inverters and output inverter that form series connection each other; The input of inverter is connected on the output of input inverter and control inverter wherein, and the output of exporting inverter this moment forms the output of this duty cycle adjustment circuit.
In order to obtain complementary signal, also draw one road complementary signal output on the output of above-mentioned middle inverter.
In order to obtain the tuning capability of broadband; Above-mentioned oscillating circuit mainly is made up of input control circuit and the end to end delay unit of N level; Wherein per 1 grade of delay unit comprises the transmission gate circuit and vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is divided into 2 the tunnel immediately after getting into the clock generator body; Wherein 1 the tunnel directly insert per 1 grade of delay unit transmission gate 1 control end, another road is through inserting 1 control end in addition of per 1 grade of delay unit transmission gate behind input control circuit; The output of the vibration inverter of afterbody delay unit be divided into 2 the tunnel, the 1 tunnel as feedback end be connected to first order delay unit input, in addition 1 the tunnel then form oscillating circuit output.
Constant for the grid voltage sum that guarantees transmission gate, above-mentioned said input control circuit is for to be made up of 2 identical FETs; Wherein the source electrode of first FET links to each other with the positive pole of power supply, and the drain and gate of second FET links to each other with the negative pole of power supply; The drain electrode of first FET is connected with the source electrode of second FET, and the grid of first FET forms the input of input control circuit.
Compared with prior art, the present invention has following characteristics:
1) through producing non-overlapped clock signal at the rear of oscillating circuit parallel connection at least 2 tunnel duty cycle adjustment circuit; Let the present invention can collect the oscillator signal generation and betide one with non-overlapping clock; Thereby broken traditional non-overlapping clock circuit structure, made this circuit become a clock generator truly;
2) because the duty cycle control signal of duty cycle adjustment circuit can be drawn the outside of clock generator; This not only can carry out flexible to the time interval of the clock signal of clock generator output, and can under the prerequisite of simplifying circuit, produce complementary, that the high level zone is non-overlapped and/or the low level zone non-overlapped etc. many to non-overlapping clock;
3) oscillating circuit adopts the voltage controlled oscillator based on transmission gate; Because it is that oscillating circuit can obtain wide frequency ranges that transmission gate can have wide Standard resistance range as adjustable equivalent resistance; Therefore the present invention can have the broadband tuning range of a plurality of orders of magnitude, can be widely used in low frequency field (like processing of biomedical signals) and high frequency field (surveying and handle a certain signal like wireless sensor network node).
Description of drawings
Fig. 1 is a kind of theory diagram of adjustable non-overlapping clock generator;
Fig. 2 is the circuit diagram of oscillating circuit;
Fig. 3 is the circuit diagram of duty cycle adjustment circuit;
Fig. 4 is the equivalent resistance model of Fig. 3;
Fig. 5 is a kind of simulation result of adjustable non-overlapping clock generator;
Fig. 6 is the details enlarged drawing of Fig. 5.
Embodiment
Referring to Fig. 1; A kind of adjustable non-overlapping clock method for generation of the present invention; Comprise that square-wave signal produces step and square-wave signal duty cycle adjustment step; The square-wave signal that its oscillating circuit produces is input to respectively at least 2 tunnel duty cycle adjustment circuit; Per 1 tunnel duty cycle adjustment circuit is realized the duty cycle adjustment of square-wave signal under the effect of different duty control signal, obtain thus at least 2 the tunnel have different duty the output signal, these output signals with different duty are the non-overlapping clock signal.
Above-mentioned per 1 tunnel duty cycle adjustment circuit constitutes with the control inverter by 2 input inverters that form parallel connection each other; Under the adjusting of the duty cycle control signal of control inverter input, the overturn point that changes input inverter realizes importing the duty cycle adjustment of square-wave signal from the square-wave signal of input inverter input input.For the waveform that makes final signal better; Per 1 tunnel duty cycle adjustment circuit also contains 2 the middle inverters and output inverter that form series connection each other; Middle inverter is serially connected on the overturn point of above-mentioned input inverter with the output inverter, to improve the waveform of duty cycle adjustment circuit output signal.
Above-mentioned oscillating circuit mainly is made up of input control circuit and the end to end delay unit of N level, and wherein per 1 grade of delay unit comprises the transmission gate and vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is through input control circuit adjustment back formation complementary voltage signal, the voltage that this complementary voltage voltage of signals size is power source voltage and input voltage signal poor; Above-mentioned input voltage signal and complementary voltage signal send into respectively the transmission gate of per 1 grade of delay unit 2 control ends, let all transmission gates between conducting and cut-off state, change, and the square-wave signal that impels delay unit to produce to have the broadband tunable range.
This circuit design is to be based upon on passgate structures voltage controlled oscillator (TG-VCO) basis of EDM Generator of Adjustable Duty Ratio.Input signal forms two paths of signals through input control circuit, and simultaneously the transmission gate in the delay unit is carried out regulating and controlling.This regulates mainly is the tuning range that obtains broadband for the output signal that makes oscillating circuit.Behind the delay unit of being made up of transmission gate and inverter through the N level, oscillating circuit is exported square-wave signal.Consider this output signal is carried out voltage control, can change its duty ratio.Along this thinking; In order to obtain the not overlapping clock signal of two phases; We propose parallel voltage-controlled design; Respectively the output signal of TG-VCO is carried out the adjusting of different duty with two control voltages through the duty cycle adjustment circuit, thereby make directly output two not overlapping clock mutually of VCO, the generation of non-overlapping clock signal is integrated mutually with two in the generation that has realized oscillator signal.
According to a kind of adjustable non-overlapping clock generator that said method designed, as shown in Figure 1, it mainly is made up of oscillating circuit and 2 tunnel EDM Generator of Adjustable Duty Ratio circuit at least; Wherein the EDM Generator of Adjustable Duty Ratio circuit more than 2 road or 2 tunnel is parallel with one another, and the input of per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit all links to each other with the output of oscillating circuit; Have a duty cycle adjustment end on per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit, different duty cycle control signals gets into the clock generator body from different EDM Generator of Adjustable Duty Ratio circuit; The output of duty cycle adjustment circuit forms the output of clock generator body.
In order to obtain the broadband tuning capability, in the present invention, said oscillating circuit adopts the voltage controlled oscillator (TG-VCO) based on passgate structures.Be that said oscillating circuit mainly is made up of input control circuit and the end to end delay unit of N level, wherein per 1 grade of delay unit comprises the transmission gate circuit and vibration inverter of mutual formation series connection.Above-mentioned N is equal to or greater than 3 odd number, like N=3,7,9,11 ..., in the present embodiment, adopt 3 grades of delay units.The input voltage signal of outside input is divided into 2 the tunnel immediately after getting into the clock generator body; Wherein 1 the tunnel directly insert per 1 grade of delay unit transmission gate 1 control end, another road is through inserting 1 control end in addition of per 1 grade of delay unit transmission gate behind input control circuit; The output of the vibration inverter of afterbody delay unit be divided into 2 the tunnel, the 1 tunnel as feedback end be connected to first order delay unit input, in addition 1 the tunnel then form oscillating circuit output.Because transmission gate is made up of a N channel field-effect pipe and the parallel connection of a P-channel field-effect transistor (PEFT) pipe, and the voltage sum that is used to control the grid of N channel field-effect tube grid and P-channel field-effect transistor (PEFT) pipe is Vdd.Therefore constant in order to guarantee this grid voltage sum Vdd, in the present invention, available 2 identical FETs constitute input control circuit.Wherein the source electrode of first FET links to each other with the positive pole of power supply, and the drain and gate of second FET links to each other with the negative pole of power supply; The drain electrode of first FET is connected with the source electrode of second FET, and the grid of first FET forms the input of input control circuit.Referring to Fig. 2.
Input voltage control signal through regulating transmission gate circuit changes transistorized working region; Transmission gate is changed between conducting state and cut-off state; Transmission gate equivalent resistance, the delay unit of being made up of inverter and transmission gate change simultaneously; And then let the oscillating circuit output signal frequency be able to by voltage control, and the relation between frequency and transmission gate equivalent resistance is shown below:
In the following formula, N is a delay cell progression, and τ is the time-delay of each unit, and Gm is the mutual conductance of inverter, and Rtg is the transmission gate equivalent resistance, and Cg is a parasitic capacitance.Because Gm and Cg are device parameters, be considered to constant usually, so frequency of oscillation is influenced by Rtg mainly.
Consider that the output signal to oscillating circuit carries out voltage control, can change its duty ratio.Along this thinking; In order to obtain the not overlapping clock of two phases; The present invention proposes parallel voltage-controlled design, respectively the output signal of TG-VCO is carried out the adjusting of different duty, thereby make the directly not overlapping clock of output two phases of VCO with two control voltages.Change the duty ratio of oscillating circuit output signal, need change high level and the shared ratio of low level in the signal period actually.When PMOS pipe that constitutes inverter and NMOS pipe were all saturated, its voltage-transfer characteristic curve was approximately vertical line segment, and the The perfect Gain in this zone is an infinity.Overturn point is also claimed turn threshold, is defined as the point that makes inverter input, output voltage equate.When two transistors of inverter all are in the zone of saturation, can realize the conversion of high and low level through the overturn point that changes inverter, thereby change the duty ratio of output signal.The duty cycle adjustment circuit that is used to control TG-VCO output signal is as shown in Figure 3, and promptly per 1 tunnel duty cycle adjustment circuit constitutes with the control inverters by 2 input inverters that form parallel connection each other.Wherein input inverter is made up of transistor M15 and transistor M16, and the input of this input inverter forms the input of oscillating circuit, and the square-wave signal Vin of TG-VCO output imports thus; The control inverter is made up of transistor M17 and transistor M18, and the input of this control inverter forms the duty cycle adjustment end, and duty cycle control signal Vduty imports thus; Input inverter links to each other with the output of control inverter and afterwards forms the overturn point of this duty cycle adjustment circuit; Better for the waveform that makes final signal, behind the overturn point of above-mentioned duty cycle adjustment circuit, also be serially connected with 2 inverters.Be that per 1 tunnel duty cycle adjustment circuit also includes 2 middle inverters and output inverter that form series connection each other; Inverter is made up of transistor M19 and transistor M20 wherein; The input of this centre inverter is connected on the output of input inverter and control inverter; The output of middle inverter is the complementary signal output, and complementary output signal Vout ' exports thus; The output inverter is made up of transistor M21 and transistor M22, and the input of this output inverter links to each other with the output of middle inverter, and the output of output inverter forms the output of this duty cycle adjustment circuit, and output signal Vout exports thus.
Suppose all pipe works in the saturation region, input inverter is as shown in Figure 4 with the equivalent resistance model of control inverter, and node voltage Vb can pass through computes:
R is the conducting resistance (on-resistance) of FET, and wherein R17 and R18 can regard variable resistor as.Adjusting Vduty controls the resistance of R17 and R18, and the value of Vb also changes thereupon.Therefore, the overturn point of the input inverter that M15 and M16 form can be controlled by Vduty, can regulate the duty ratio that oscillating circuit is exported signal thus.
In the present embodiment, the output with the input Vin of two duty cycle adjustment circuit diagrams 3 is parallel to oscillating circuit Fig. 2 can realize the non-overlapping clock generator shown in Fig. 1 theory diagram.Vduty1, Vduty2 are respectively two duty cycle adjustment circuit control voltages.Through these two control voltages are set, draw the output signal of different duty, it is right to produce non-overlapping clock thus.Because middle inverter can be exported the signal of anti-phase each other with the output inverter; Therefore can behind middle inverter, set up a complementary signal output, so the signal nclk1 of this complementary signal output output just with the former complementary clock signal of a pair of each other anti-phase of signal clk1 that is located at the signal output part output behind the output inverter.According to this scheme,, so just can draw different non-overlapping clock signals if each road duty cycle circuit can both be exported the complementary clock signal of a pair of anti-phase.Duty cycle circuit with 2 Fig. 4 of parallel connection is an example, and can export 4 signals so altogether is clk1, nclk1, clk2, nclk2, the waveform of these 4 signals such as Fig. 5 and shown in Figure 6.Wherein have:
2 groups of complementary non-overlapping clock signals: clk1 and nclk1, clk2 and nclk2.Their characteristics are clk when being high, and nclk is low, and high and low level part is never overlapping.
1 group of high level part non-overlapping clock signal: clk1 and clk2.Their low level partly can be overlapping.
1 group of low level part non-overlapping clock signal: nclk1 and nclk2.Their high level partly can be overlapping.
It is thus clear that parallel connection is how many road EDM Generator of Adjustable Duty Ratio circuit, what just can be exported to complementary non-overlapping clock signal, i.e. clk and nclk.
When the output of oscillating circuit only is connected to one tunnel EDM Generator of Adjustable Duty Ratio circuit, only export one group of complementary non-overlapping clock signal.
When the output of oscillating circuit parallel connection 2 tunnel EDM Generator of Adjustable Duty Ratio circuit, exportable 2 groups of complementary signals, 1 group of high level are overlapped signal not, and 1 group of low level is overlapped signal not.
When the output of oscillating circuit parallel connection 3 tunnel EDM Generator of Adjustable Duty Ratio circuit, exportable 3 groups of complementary signals, 3 groups of high level parts are overlapped signal not, and 3 groups of low level parts are overlapped signal not.For example, through regulating the various signals duty ratio of 3 tunnel duty cycle adjustment circuit, export 6 signal: clk1 (high level partly accounts for 44%), nclk1 (56%), clk2 (80%), nclk2 (20%), clk3 (60%), nclk3 (40%).Wherein have:
3 groups of complementary non-overlapped signals are right: clk1 and nclk1, clk2 and nclk2, clk3 and nclk3.
Overlapped signal is not right: clk1 and nclk2, clk1 and nclk3, clk3 and nclk2 for 3 groups of high level parts.
Overlapped signal is not right: clk2 and nclk1, clk2 and nclk3, clk3 and nclk1 for 3 groups of low level parts.
Therefore, the present invention can obtain many to the non-overlapping clock signal through parallel multiplex duty cycle adjustment circuit, include complementary non-overlapped signal to, high level part not overlapped signal to overlapped signal is not right with the low level part.
Claims (10)
1. adjustable non-overlapping clock method for generation; It is characterized in that: the square-wave signal that oscillating circuit produces is input to respectively at least 2 tunnel duty cycle adjustment circuit; Per 1 tunnel duty cycle adjustment circuit is realized the duty cycle adjustment of square-wave signal under the effect of different duty control signal; Obtain thus at least 2 the tunnel have different duty the output signal, these output signals with different duty are the non-overlapping clock signal.
2. a kind of adjustable non-overlapping clock method for generation according to claim 1 is characterized in that: per 1 tunnel duty cycle adjustment circuit constitutes with the control inverter by 2 input inverters that form parallel connection each other; Under the adjusting of the duty cycle control signal of control inverter input, the overturn point that changes input inverter realizes importing the duty cycle adjustment of square-wave signal from the square-wave signal of input inverter input input.
3. a kind of adjustable non-overlapping clock method for generation according to claim 2 is characterized in that: also be included in middle inverter that 2 of serial connections on the output of input inverter form series connection each other and export the steps that inverter improves duty cycle adjustment circuit output signal waveform.
4. according to any described a kind of adjustable non-overlapping clock method for generation in the claim 1～3; It is characterized in that: oscillating circuit mainly is made up of input control circuit and the end to end delay unit of N level; Wherein per 1 grade of delay unit comprises the transmission gate and vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is through input control circuit adjustment back formation complementary voltage signal, the voltage that this complementary voltage voltage of signals size is power source voltage and input voltage signal poor; Above-mentioned input voltage signal and complementary voltage signal send into respectively the transmission gate of per 1 grade of delay unit 2 control ends, let all transmission gates between conducting and cut-off state, change, and the square-wave signal that impels delay unit to produce to have the broadband tunable range.
5. an adjustable non-overlapping clock generator comprises the clock generator body, it is characterized in that: the clock generator body mainly is made up of oscillating circuit and 2 tunnel EDM Generator of Adjustable Duty Ratio circuit at least; Wherein the EDM Generator of Adjustable Duty Ratio circuit more than 2 road or 2 tunnel is parallel with one another, and the input of per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit all links to each other with the output of oscillating circuit; Have a duty cycle adjustment end on per 1 tunnel EDM Generator of Adjustable Duty Ratio circuit, different duty cycle control signals gets into the clock generator body from different EDM Generator of Adjustable Duty Ratio circuit; The output of duty cycle adjustment circuit forms the output of clock generator body.
6. a kind of adjustable non-overlapping clock generator according to claim 5 is characterized in that: per 1 tunnel duty cycle adjustment circuit constitutes with the control inverter by 2 input inverters that form parallel connection each other; Wherein the input of input inverter forms the input of oscillating circuit, and the input of control inverter forms the duty cycle adjustment end, link to each other with the output of the control inverter output of this duty cycle adjustment circuit of back formation of input inverter.
7. a kind of adjustable non-overlapping clock generator according to claim 6 is characterized in that: per 1 tunnel duty cycle adjustment circuit also includes 2 the middle inverters and output inverter that form series connection each other; The input of inverter is connected on the output of input inverter and control inverter wherein, and the output of exporting inverter this moment forms the output of this duty cycle adjustment circuit.
8. a kind of adjustable non-overlapping clock generator according to claim 7 is characterized in that: also draw one road complementary signal output on the output of middle inverter.
9. according to any described a kind of adjustable non-overlapping clock generator in the claim 5～8; It is characterized in that: said oscillating circuit mainly is made up of input control circuit and N level delay cells connected in series; Wherein per 1 grade of delay unit comprises the transmission gate circuit and vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is divided into 2 the tunnel immediately after getting into the clock generator body; Wherein 1 the tunnel directly insert per 1 grade of delay unit transmission gate 1 control end, another road is through inserting 1 control end in addition of per 1 grade of delay unit transmission gate behind input control circuit; The output of the vibration inverter of afterbody delay unit be divided into 2 the tunnel, the 1 tunnel as feedback end be connected to first order delay unit input, in addition 1 the tunnel then form oscillating circuit output.
10. a kind of adjustable non-overlapping clock generator according to claim 9, it is characterized in that: said input control circuit is for to be made up of 2 identical FETs; Wherein the source electrode of first FET links to each other with the positive pole of power supply, and the drain and gate of second FET links to each other with the negative pole of power supply; The drain electrode of first FET is connected with the source electrode of second FET, and the grid of first FET forms the input of input control circuit.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103078611A (en) * | 2012-12-28 | 2013-05-01 | 香港中国模拟技术有限公司 | Clock generator and switched capacitor circuit comprising same |
| CN104579171A (en) * | 2013-10-16 | 2015-04-29 | 精工爱普生株式会社 | Oscillation circuit, oscillator, electronic device, and moving object |
| CN104639125A (en) * | 2013-11-14 | 2015-05-20 | 展讯通信（上海）有限公司 | Clock signal generator and electronic equipment |
| CN106357238A (en) * | 2015-07-17 | 2017-01-25 | 爱思开海力士有限公司 | Signal generator adjusting a duty cycle and semiconductor apparatus using the same |
| CN107124161A (en) * | 2017-03-17 | 2017-09-01 | 东南大学 | A kind of method based on unimolecule and two molecular chemical reaction real-time performance M/N duty cycle clock signals |
| CN112448700A (en) * | 2021-02-01 | 2021-03-05 | 南京邮电大学 | 50% duty cycle shaping circuit used under low voltage |
| CN117498840A (en) * | 2023-12-29 | 2024-02-02 | 中茵微电子(南京)有限公司 | Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator |
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