CN102427056A - Photoresist removing method in integrated oxide film etching process - Google Patents
Photoresist removing method in integrated oxide film etching process Download PDFInfo
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- CN102427056A CN102427056A CN2011102502441A CN201110250244A CN102427056A CN 102427056 A CN102427056 A CN 102427056A CN 2011102502441 A CN2011102502441 A CN 2011102502441A CN 201110250244 A CN201110250244 A CN 201110250244A CN 102427056 A CN102427056 A CN 102427056A
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Abstract
The invention discloses a photoresist removing method in an integrated oxide film etching process. The photoresist removing method comprises the following steps of: step 1, firstly injecting high-pressure reaction gas in a reaction chamber before removing photoresist from the surface of a silicon wafer in the reaction chamber, and removing a copper polymer attached to the surface of the reaction chamber by the injected high-pressure reaction gas; step 2, injecting low-pressure reaction gas in the reaction chamber, and removing the photoresist covering the surface of the silicon wafer by the low-pressure reaction gas; and step 3, filling a metal material in a through hole and a groove. By the photoresist removing method in the integrated oxide film etching process, disclosed by the invention, the capacitance state and the etching speed of the reaction chamber effectively keep stable by removing the copper polymer attached to the surface of the reaction chamber, and the oxide layer below the groove is prevented from being over-etched, thus the stability of metal resistivity of metal material filled in the groove is improved.
Description
Technical field
The present invention relates to a kind of technique processing method, relate in particular to a kind of process of in integrated oxidization film etching technics, removing photoresist.
Background technology
Integrated oxidization film etching technics is meant through in same etching cavity, carrying out via etch successively, remove photoresist and carrying out etching groove.As shown in Figure 1, in the reaction chamber of etching, form capacitance structure each other by supply voltage and bias voltage, on bias voltage, place silicon chip and carry out etching.
In technical process to the oxide-film etching; Wherein, silicon chip is shown in Figure 2, is formed with metal interconnecting wires in the bottom dielectric layer that silicon chip comprised; Be coated with etching barrier layer and oxide layer on the bottom dielectric layer successively; And in oxide layer, form groove, and be formed with through hole in the zone that is arranged in beneath trenches of oxide layer, said through hole runs through etching barrier layer and is in contact with one another with metal interconnecting wires.Wherein, The accumulative total that is formed with the copper polymer that the copper in the metal interconnecting wires shed by ion bombardment in the bottom dielectric layer that silicon chip comprised covers the reaction cavity surface; And reaction cavity surface accumulative total gradually thickening cause the electric capacity in the reaction chamber to descend, the electric capacity caused electric field strength that descends increases, when electric field strength increases; Etching intermediate ion bombardment power at second dielectric layer increases gradually; As shown in Figure 3, causing is that the etching depth of groove increases (depth H 1 by standard is increased to unusual depth H 2) gradually when etching groove, and the volume that causes simultaneously being filled in the metallic object in the groove increases; Thereby having influenced the resistivity of filling metal diminishes; Cause metallic resistance rate, the state in the etching reaction chamber and the etch rate of filling metal material in the groove unstable, too much etching simultaneously is positioned at the oxide layer of said beneath trenches, thereby has reduced the stability of filling the metallic resistance rate of metal material in the groove.
Summary of the invention
Disclosure of the Invention a kind of through electric capacity state and etch rate problem of unstable in the reaction chamber that causes in order to the copper polymer that solves reaction chamber surface adsorption in the prior art.
For realizing above-mentioned purpose, the technical scheme that invention is adopted is:
A kind of process of in integrated oxidization film etching technics, removing photoresist wherein, is formed with metal interconnecting wires in the bottom dielectric layer that silicon chip comprised; Be coated with etching barrier layer and oxide layer on the bottom dielectric layer successively; And in oxide layer, form groove, and be formed with through hole in the zone that is arranged in beneath trenches of oxide layer, said through hole runs through etching barrier layer and contacts with metal interconnecting wires; Wherein, comprise following processing step:
Wherein, Form in the process of groove at the etching oxidation layer; The copper polymer of removing the reaction chamber surface adsorption is used to make the electric capacity state of reaction chamber and etch rate to keep stable; Avoid too much etching to be positioned at the oxide layer of said beneath trenches, thereby improve the stability of filling the metallic resistance rate of metal material in the groove.
Above-mentioned process, wherein, said high pressure, low pressure attitude reacting gas are oxygen.
Above-mentioned process, wherein, the injection rate of said high voltage state reacting gas is greater than 100mTorr.
Above-mentioned process, wherein, the injection rate of said low pressure attitude reacting gas is less than 50mTorr.
Above-mentioned process, wherein, said reaction chamber is an etching cavity.
Of the present invention through a kind of process of in integrated oxidization film etching technics, removing photoresist; Adopted following scheme to have following effect; This project is used to make the electric capacity state of reaction chamber and etch rate to keep stable through the copper polymer of removing the reaction chamber surface adsorption; Avoid too much etching to be positioned at the oxide layer of said beneath trenches, thereby improve the stability of filling the metallic resistance rate of metal material in the groove.
Description of drawings
Through the detailed description that reading is done non-limiting example with reference to following accompanying drawing, the further feature of invention, it is more obvious that purpose and advantage will become.
Fig. 1 is the electric capacity structural scheme of mechanism of a kind of process of in integrated oxidization film etching technics, removing photoresist of invention;
Fig. 2 is the silicon chip structural representation of a kind of process of in integrated oxidization film etching technics, removing photoresist of invention;
Fig. 3 is the silicon chip erosion structural representation of a kind of process of in integrated oxidization film etching technics, removing photoresist of invention;
As scheme sequence number: silicon chip 1, dielectric layer 2, metal interconnecting wires 3, etching barrier layer 4, oxide layer 5, groove 6, through hole 7, reaction chamber 8, photoresist 9, copper polymer 10.
Embodiment
For technological means that invention is realized, create characteristic, reach purpose and effect and be easy to understand and understand that following combinations specifically illustrates, and further sets forth the present invention.
Please referring to Fig. 1, shown in 2; In the bottom dielectric layer 2 that silicon chip 1 is comprised, be formed with metal interconnecting wires 3, be coated with etching barrier layer 4 on the bottom dielectric layer 2 successively and form groove 6 with oxide layer 5 and in oxide layer 5, and be formed with through hole 7 in the zone that is arranged in below the groove 6 of oxide layer 5; Through hole 7 runs through etching barrier layer 4 and contacts with metal interconnecting wires 3; Wherein, comprise following processing step: step 1, before in reaction chamber 8, the photoresist 9 on silicon chip 1 surface being removed; In reaction chamber 1, inject the high voltage state reacting gas earlier, utilize the high voltage state reacting gas that is injected to remove copper polymer 10 in reaction chamber 8 surface adsorption; Step 2 is injected low pressure attitude reacting gas in reaction chamber 8, utilize low pressure attitude reacting gas to remove to cover the photoresist 9 on silicon chip 1 surface; Step 3 is filled metal material in through hole 7 and groove 6; Wherein, Form in the process of groove 6 at etching oxidation layer 5; The copper polymer 10 of removing reaction chamber 8 surface adsorption is used to make the electric capacity state of reaction chamber 8 and etch rate to keep stable; Avoid too much etching to be positioned at the oxide layer 5 of groove 6 belows, thereby improve the stability of filling the metallic resistance rate of metal material in the groove 6.
Further, wherein inject reaction chamber 8 high pressure, low pressure attitude reacting gas is an oxygen.
Further, the injection rate of high voltage state reacting gas makes its high voltage state reacting gas that injects reaction chamber 8 can effectively remove the copper polymer 100 that is adsorbed on reaction chamber 8 greater than 100mTorr.
Further, the injection rate of low pressure attitude reacting gas makes its low pressure attitude reacting gas that injects reaction chamber can effectively remove the photoresist 9 that silicon chip 1 surface is covered less than 50mTorr.
Further, reaction chamber 8 is an etching cavity, and all etching technics are accomplished in reaction chamber 8.
In specific embodiment of the present invention; The high voltage state reacting gas that is injected in the reaction chamber 1 that utilizes as shown in Figure 3 is removed the copper polymer 10 in reaction chamber 8 surface adsorption; Remove copper polymer 10 and just can keep can not receiving between supply voltage and the bias voltage electric capacity that interference the caused decline that copper polymer 10 stops; Further; The be inversely proportional to decline of E=Kq/C electric capacity of electric field strength and electric capacity directly influences the increase of electric field strength, and the increase of electric field strength directly has influence on the bombardment power of reactive ion to dielectric layer 2, so keep the stability of electric capacity just can effectively control the bombardment of dielectric layer 2; Make dielectric layer 2 can remain on the distance of the depth H 1 of standard; Avoided the appearance of unusual depth H 2, the volume that is filled in the metallic object in the groove 6 simultaneously keeps fixed value, and the stability of resultant metal resistivity is significantly improved.Further, increase by a step step of high pressure before in conventional low pressure attitude reacting gas, going the photoresist step, remove copper 10 polymer of housing surface, make state and etch rate in the reaction chamber keep stable.
In sum; Invent a kind of process of in integrated oxidization film etching technics, removing photoresist; Effectively be used to make the electric capacity state of reaction chamber and etch rate to keep stable through the copper polymer of removing the reaction chamber surface adsorption; Avoid too much etching to be positioned at the oxide layer of said beneath trenches, thereby improve the stability of filling the metallic resistance rate of metal material in the groove.
More than to the invention specific embodiment be described.It will be appreciated that invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence the essence of an invention content.
Claims (5)
1. a process of in integrated oxidization film etching technics, removing photoresist wherein, is formed with metal interconnecting wires in the bottom dielectric layer that silicon chip comprised; Be coated with etching barrier layer and oxide layer on the bottom dielectric layer successively; And in oxide layer, form groove, and be formed with through hole in the zone that is arranged in beneath trenches of oxide layer, said through hole runs through etching barrier layer and contacts with metal interconnecting wires; It is characterized in that, comprise following processing step:
Step 1 before in reaction chamber, the photoresist of silicon chip surface being removed, is injected the high voltage state reacting gas earlier in reaction chamber, utilize the high voltage state reacting gas that is injected to remove the copper polymer in the reaction chamber surface adsorption;
Step 2 is injected low pressure attitude reacting gas in reaction chamber, utilize low pressure attitude reacting gas to remove the photoresist that covers silicon chip surface;
Step 3 is filled metal material in said through hole and groove;
Wherein, Form in the process of groove at the etching oxidation layer; The copper polymer of removing the reaction chamber surface adsorption is used to make the electric capacity state of reaction chamber and etch rate to keep stable; Avoid too much etching to be positioned at the oxide layer of said beneath trenches, thereby improve the stability of filling the metallic resistance rate of metal material in the groove.
2. process according to claim 1 is characterized in that, said high pressure, low pressure attitude reacting gas are oxygen.
3. process according to claim 1 is characterized in that the injection rate of said high voltage state reacting gas is greater than 100mTorr.
4. process according to claim 1 is characterized in that, the injection rate of said low pressure attitude reacting gas is less than 50mTorr.
5. process according to claim 1 is characterized in that, said reaction chamber is an etching cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102502441A CN102427056A (en) | 2011-08-29 | 2011-08-29 | Photoresist removing method in integrated oxide film etching process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102502441A CN102427056A (en) | 2011-08-29 | 2011-08-29 | Photoresist removing method in integrated oxide film etching process |
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| Publication Number | Publication Date |
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| CN102427056A true CN102427056A (en) | 2012-04-25 |
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| CN2011102502441A Pending CN102427056A (en) | 2011-08-29 | 2011-08-29 | Photoresist removing method in integrated oxide film etching process |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001048804A1 (en) * | 1999-12-29 | 2001-07-05 | Lam Research Corporation | In situ post-etch photoresist and polymer stripping and dielectric etch chamber cleaning |
| US6323121B1 (en) * | 2000-05-12 | 2001-11-27 | Taiwan Semiconductor Manufacturing Company | Fully dry post-via-etch cleaning method for a damascene process |
-
2011
- 2011-08-29 CN CN2011102502441A patent/CN102427056A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001048804A1 (en) * | 1999-12-29 | 2001-07-05 | Lam Research Corporation | In situ post-etch photoresist and polymer stripping and dielectric etch chamber cleaning |
| US6323121B1 (en) * | 2000-05-12 | 2001-11-27 | Taiwan Semiconductor Manufacturing Company | Fully dry post-via-etch cleaning method for a damascene process |
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Application publication date: 20120425 |