CN102446846B - Method for achieving high-performance copper interconnection by utilizing upper mask - Google Patents
Method for achieving high-performance copper interconnection by utilizing upper mask Download PDFInfo
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- CN102446846B CN102446846B CN201110384049.8A CN201110384049A CN102446846B CN 102446846 B CN102446846 B CN 102446846B CN 201110384049 A CN201110384049 A CN 201110384049A CN 102446846 B CN102446846 B CN 102446846B
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Abstract
The invention discloses a method for achieving high-performance copper interconnection by utilizing an upper mask. The method is characterized in that a semiconductor substrate with a metal interconnection layer is arranged, wherein a composite structure is firstly formed on the metal interconnection layer of the semiconductor substrate and comprises an etch stop layer, a dielectric layer, an upper coating, an etch adjustment layer and a mask layer from bottom to top in sequence. The invention has the following beneficial effects: through the process flow and method disclosed by the invention, the added silicon nitride etch depth adjustment layer is utilized to selectively change the depth of the grooves of copper interconnection lines, thus reducing the square resistance of the copper interconnection lines which conform to the conditions and are arranged in the specific region, and further achieving the aim of selectively reducing the chip interconnection resistance; and by utilizing the method, the interconnection resistance can be furthest reduced on the premises of not changing the overall copper interconnection depth, not increasing the process difficulty and not reducing the process window, thus reducing the signal delay of the chips, reducing the losses and improving the overall performance of the chips.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially a kind of method of utilizing mask to realize copper-connection.
Background technology
In semiconductor integrated circuit industry, high performance integrated circuit chip needs high performance back segment electricity to connect.Metallic copper, due to its low-resistivity characteristic, has obtained application more and more widely in advanced integrated circuit (IC) chip.From aluminum steel to copper cash, the change of material has brought the huge reduction of resistivity.Along with the progress of integrated circuit technique, the increase of chip complexity, this means that the resistance of the back segment interconnection line in chip becomes one of bottleneck of performance.How effectively to reduce resistance, become an important subject of back segment interconnection.
From resistance formula, we can obtain some inspirations:
(in upper figure formula, R represents resistance, and ρ represents the resistivity of material, and L represents conductor length, and W represents interconnection line width, and H represents the thickness of interconnection line.) along with the dwindling of chip size, the raising of density and the raising of chip complexity, the width of interconnection line constantly reduces, the also inevasible increase of the total length L of interconnection line.The factor of resistance be can reduce and only resistivity and thickness have been left.And be switched to copper-connection from aluminium interconnection, thereby the resistivity that reduces interconnection line realizes the reduction of overall resistance.And for same material, its resistivity is certain substantially.Therefore, can just only be improved the thickness H of interconnection line for reducing unique factor of the resistance of high-end copper interconnecting line.In order to characterize more accurately the impact of thickness on resistance, in semiconductor technology, adopt square resistance (sheet resistance, is also sheet resistance, and computing formula is Rs=ρ/H, R=Rs*L/W) to characterize.For the difform interconnection line of same process, square resistance can symbolize the impact of thickness on resistance accurately like this, and is not subject to the impact of conductor length and width.
In fact, due to the restriction of metal filled technique and etching technics, Embedded copper interconnection structure will successfully be realized, and its basic technology conditional request depth-width ratio can not be excessive, and, for the copper interconnecting line of a certain width, its thickness can not be too thick.Because thickness is too thick, mean that the groove structure degree of depth is very large, will be unfavorable for that etching technics controls etched pattern and size, and metal filled technique also more difficult complete completely fill, can increase resistance so on the contrary, reduce the reliability of interconnection, bring very adverse influence.Therefore integral thickness that can not unconfined increase interconnection line reduces resistance.
Summary of the invention
The problems referred to above that exist for existing back segment electricity syndeton, the invention provides a kind of method of utilizing mask to realize copper-connection.
The technological means that technical solution problem of the present invention adopts is:
Utilize mask to realize a method for copper-connection, comprise that one exists the semiconductor base of metal interconnecting layer, wherein, comprise following concrete steps:
Step a, on the metal interconnecting layer of described semiconductor base, form a composite construction, described composite construction is that etching stop layer, dielectric layer, overlying strata, etching are adjusted layer and mask layer from down to up successively;
Step b, described composite construction is carried out to etching, in described mask layer, form the pattern of metal interconnect structure and make etching stopping adjust layer in described etching;
Step c, in described metal interconnect structure pattern, the predetermined described etching that needs the region of deepening is adjusted to layer and removes;
Steps d, in described metal interconnect structure pattern, photoetching and partial etching are carried out in the predetermined position that forms through hole, make to form on described composite construction the through-hole pattern of desired depth;
Step e, described composite construction is carried out to etching, the groove and the through hole that to form described metal interconnect structure pattern, sketch the contours;
Step f, in described groove and through hole embedded with metal, make described metal be full of described groove and through hole;
Step g, smooth described composite structure surface.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, described etching stop layer is nitrogen-doped silicon carbide layer.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the relative dielectric constant of described dielectric layer is 2-4.2.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, described overlying strata is silicon oxide layer.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, it is silicon nitride layer that described etching is adjusted layer.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, described mask layer is titanium nitride metal level.
In above-mentioned utilization, mask is realized the method for copper-connection, wherein, in described step b, described in etching, the method for composite construction is: utilize photoetching by described metal interconnect structure design transfer to described mask layer, etching is removed the mask layer in described metal interconnect structure pattern.
In above-mentioned utilization, mask is realized the method for copper-connection, wherein, the method of removing described etching adjustment layer in described step c is: utilize a predefine light shield, described in etching, the predetermined described etching in the region of intensification that needs is adjusted layer, etching mode is plasma dry etching, and described etching stopping is in described overlying strata.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, in described step f, the metal of inlaying is copper.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, in described step g, the method for smooth described composite structure surface is cmp.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described nitrogen-doped silicon carbide layer is chemical vapour deposition (CVD).
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described dielectric layer is chemical vapour deposition (CVD).
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described silicon oxide layer is chemical vapour deposition (CVD).
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described silicon nitride layer is chemical vapour deposition (CVD).
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described titanium nitride metal level is physical vapour deposition (PVD).
In above-mentioned utilization, mask is realized the method for copper-connection, wherein, between the groove on described metallic copper and described composite construction and through hole, has barrier layer.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the method for embedding of described metallic copper is for electroplating.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, described barrier layer is tantalum or tantalum nitride.
In above-mentioned utilization, mask is realized the method for copper-connection, and wherein, the formation method of described tantalum or tantalum nitride barrier layer is physical vapour deposition (PVD).
The invention has the beneficial effects as follows:
By technological process of the present invention and method, utilize the silicon nitride etch degree of depth of adding to adjust layer, the degree of depth of copper interconnecting line groove is carried out to selectively changing, thereby the copper interconnecting line square resistance of qualified specific region is reduced, thereby realize the object of elective reduction chip interconnects resistance.Through utilization of the present invention, can not increase technology difficulty not changing global copper interconnect depth,, under the prerequisite of reduction process window, farthest do not reduce interconnection resistance, thereby reduce the signal delay of chip, reduce the wastage, improve chip overall performance.
Accompanying drawing explanation
Fig. 1 is a kind of flow chart that utilizes mask to realize the method for copper-connection of the present invention;
Fig. 2 is the profile status structure chart after a kind of step a that utilizes mask to realize the method for copper-connection of the present invention completes;
Fig. 3 is the profile status structure chart after a kind of step b that utilizes mask to realize the method for copper-connection of the present invention completes;
Fig. 4 is the profile status structure chart after a kind of step c that utilizes mask to realize the method for copper-connection of the present invention completes;
Fig. 5 is the profile status structure chart after a kind of steps d of utilizing mask to realize the method for copper-connection of the present invention completes;
Fig. 6 is the profile status structure chart after a kind of step e that utilizes mask to realize the method for copper-connection of the present invention completes;
Fig. 7 is the profile status structure chart after a kind of step f that utilizes mask to realize the method for copper-connection of the present invention completes;
Fig. 8 is the profile status structure chart after a kind of step g of utilizing mask to realize the method for copper-connection of the present invention completes.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
As shown in Figure 1, a kind of method of utilizing mask to realize copper-connection of the present invention, comprises that one exists the semiconductor base 100 of metal interconnecting layer 110, wherein, comprises following concrete steps:
As shown in Figure 2, step a, on the metal interconnecting layer 110 of semiconductor base 100, form a composite construction 200, composite construction 200 is that etching stop layer 210, dielectric layer 220, overlying strata 230, etching are adjusted layer 240 and mask layer 250 from down to up successively.
Wherein said etching stop layer 210 is nitrogen-doped silicon carbide layer, and its formation method can be chemical vapour deposition (CVD); Dielectric layer 220 can be fluorine doped silicon oxide glass, carbon doped silicon oxide, porous low dielectric constant material, can be also that traditional dielectric material is as silica in practical application, the dielectric material that the relative dielectric constants such as boron phosphor silicon oxide glass are 2-4.2, its formation method can be chemical vapour deposition (CVD); Overlying strata 230 is silicon oxide layer, and its formation method can be chemical vapour deposition (CVD); Etching adjustment layer 240 can be silicon nitride layer, its thickness range is 5～200 nanometers, the size of the required adjustment degree of depth of its thickness selective basis and adjust layer film and the different materials etching selection ratio of copper-connection dielectric film determines jointly, its formation method can be chemical vapour deposition (CVD); Mask layer 250 is titanium nitride metal level, and its formation method can be physical vapour deposition (PVD).
As shown in Figure 3, step b, composite construction 200 is carried out to etching, in mask layer 250, form the pattern 300 of metal interconnect structures and make etching stopping adjust layer 210 in etching; Wherein the method for etching composite construction 200 is: form photoresistance 400 and utilize photoetching that metal interconnect structure pattern 300 is transferred to mask layer 250, etching is removed the mask layer 250 in metal interconnect structure pattern 300.
As shown in Figure 4, step c, in metal interconnect structure pattern 300, adjusts layer 240 by the predetermined etching that needs the region 310 of deepening and removes; The method of removing etching adjustment layer 240 is: utilize predefine light shield 410 coverings not need the region of deepening, and the etching adjustment layer 240 in the predetermined region 310 that need to deepen of etching, etching mode is plasma dry etching, etching stopping is in overlying strata 230.
As shown in Figure 5, steps d, in metal interconnect structure pattern 300, photoetching and partial etching are carried out in the predetermined position that forms through hole 340, make to form on composite construction 200 pattern of the through hole 330 of desired depth; The pattern of through hole 340 makes through hole 340 structures temporarily rest in the middle of dielectric layer 220 after the method for partial etching, be conducive to like this to reduce the damage of final through hole 340 structures in the process of removing photoresistance, in this step by regulating the degree of depth of partial etching to control the depth scale of groove and through hole in final form.
As shown in Figure 6, step e, composite construction 200 is carried out to etching, the groove 330 and through hole 340 that to form metal interconnect structure pattern 300, sketch the contours; Remove after photoresistance, substrate 100 surfaces have only retained the mask layer 250 with metal interconnect structure pattern 300 features.Utilize stopping of mask layer 250, composite construction 200 in substrate 100 is carried out to plasma dry etching, form groove 330, make through hole 340 etch into dielectric layer 220 bottoms simultaneously, and open etching barrier layer 210 so that the connection of the metal interconnecting layer 110 in former substrate 100.Because the effect of etching adjustment layer 240 makes the predetermined groove 330 that need to deepen region 310 darker than the groove in other regions 330.
As shown in Figure 7, step f, in groove 330 and the interior embedded with metal 350 of through hole 340, makes metal 350 be full of groove 340 and through hole 350; Wherein, the metal 350 of inlaying is copper, has barrier layer (not marking in the drawings) between the groove 330 on metal 350 and composite construction 200 and through hole 340, and barrier layer is tantalum or tantalum nitride, and its formation method is physical vapour deposition (PVD).On barrier layer, form the inculating crystal layer of a bronze medal, adopt electric plating method on the inculating crystal layer of copper, to continue filling and makes copper be full of groove 330 and through hole 340, wherein this filling step can redundancy to make up the loss of the metallic copper that may cause in follow-up surfacing step.
As shown in Figure 8, step g, smooth composite construction 200 surfaces, remove and inlay copper redundancy and mask layer, etching adjustment layer and the overlying strata that step produces, and the method on smooth composite construction 200 surfaces is cmp.
As can be seen from Figure 8 the copper interconnecting line in groove intensification region 310 has larger thickness, and the copper in this region has larger conductive section, therefore has lower square resistance Rs.Due to the copper degree of depth in this region, be less than again the degree of depth of copper in through hole 340, can guarantee that the copper interconnecting line of intensification can be realized good filling smoothly, unrestricted on technological ability.
In fact, the present invention also can embedded for individual layer (single Damascus) technique in.As long as the fill process of copper can guarantee that copper can be filled in structure smoothly, and the structure of below, groove intensification region does not affect adversely.
The foregoing is only preferred embodiment of the present invention; not thereby limit claim of the present invention; so the equivalent structure that all utilizations specification of the present invention and diagramatic content have been done changes, utilizes the material of mentioning the same-actions such as tool in known and the present invention to replace; utilize the means and methods of the same-actions such as means and methods tool of mentioning in known and the present invention to replace, resulting execution mode or result of implementation are all included in protection scope of the present invention.
Claims (17)
1. in utilization, mask is realized the method for copper-connection, comprises that one exists the semiconductor base of metal interconnecting layer, it is characterized in that, comprises following concrete steps:
Step a, on the metal interconnecting layer of described semiconductor base, form a composite construction, described composite construction is that etching stop layer, dielectric layer, overlying strata, etching are adjusted layer and mask layer from down to up successively;
Step b, described composite construction is carried out to etching, in described mask layer, form the pattern of metal interconnect structure and make etching stopping adjust layer in described etching;
Step c, in described metal interconnect structure pattern, the predetermined described etching that needs the region of deepening is adjusted to layer and removes, retain and do not need the etching in the region of deepening to adjust layer;
Steps d, in described metal interconnect structure pattern, photoetching and partial etching are carried out in the predetermined position that forms through hole, make to form on described composite construction the through-hole pattern of desired depth, wherein, the through-hole pattern of described desired depth is arranged in described metal interconnect structure pattern does not need the region of deepening;
Step e, described composite construction is carried out to etching, the groove and the through hole that to form described metal interconnect structure pattern, sketch the contours, wherein, when described composite construction is carried out to etching, utilize the barrier effect that does not need the etching in the region of deepening to adjust layer in described metal interconnect structure pattern, make that described predetermined need to deepen the groove in region darker than the described groove that does not need to deepen region;
Step f, in described groove and through hole embedded with metal, make described metal be full of described groove and through hole;
Step g, smooth described composite structure surface;
Wherein, it is silicon nitride layer that described etching is adjusted layer, and the formation method of described silicon nitride layer is chemical vapour deposition (CVD); Described in the thickness of the metal interconnecting wires in the described predetermined groove that need to deepen region is greater than, do not need to deepen the thickness of the metal interconnecting wires in the groove in region, and in the described predetermined groove that need to deepen region, the degree of depth of metal is less than the degree of depth of metal in described through hole.
2. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, described etching stop layer is nitrogen-doped silicon carbide layer.
3. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, the relative dielectric constant of described dielectric layer is 2-4.2.
4. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, described overlying strata is silicon oxide layer.
5. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, described mask layer is titanium nitride metal level.
6. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, in described step b, described in etching, the method for composite construction is: utilize photoetching by described metal interconnect structure design transfer to described mask layer, etching is removed the mask layer in described metal interconnect structure pattern.
7. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, the method of removing described etching adjustment layer in described step c is: utilize a predefine light shield, described in etching, the predetermined described etching in the region of intensification that needs is adjusted layer, etching mode is plasma dry etching, and described etching stopping is in described overlying strata.
8. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, in described step f, the metal of inlaying is copper.
9. utilize as claimed in claim 1 upper mask to realize the method for copper-connection, it is characterized in that, in described step g, the method for smooth described composite structure surface is cmp.
10. utilize as claimed in claim 2 upper mask to realize the method for copper-connection, it is characterized in that, the formation method of described nitrogen-doped silicon carbide layer is chemical vapour deposition (CVD).
11. utilize upper mask to realize the method for copper-connection as claimed in claim 3, it is characterized in that, the formation method of described dielectric layer is chemical vapour deposition (CVD).
12. utilize upper mask to realize the method for copper-connection as claimed in claim 4, it is characterized in that, the formation method of described silicon oxide layer is chemical vapour deposition (CVD).
13. utilize upper mask to realize the method for copper-connection as claimed in claim 5, it is characterized in that, the formation method of described titanium nitride metal level is physical vapour deposition (PVD).
14. utilize upper mask to realize the method for copper-connection as claimed in claim 8, it is characterized in that, between the groove on described metallic copper and described composite construction and through hole, have barrier layer.
15. utilize upper mask to realize the method for copper-connection as claimed in claim 8, it is characterized in that, the method for embedding of described metallic copper is for electroplating.
16. utilize upper mask to realize the method for copper-connection as claimed in claim 14, it is characterized in that, described barrier layer is tantalum or tantalum nitride.
17. utilize upper mask to realize the method for copper-connection as claimed in claim 16, it is characterized in that, the formation method of described tantalum or tantalum nitride barrier layer is physical vapour deposition (PVD).
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| CN102800568B (en) * | 2012-09-11 | 2016-01-20 | 上海华力微电子有限公司 | Improve the method for MOM capacitor density |
| CN102867734B (en) * | 2012-09-17 | 2015-04-08 | 上海华力微电子有限公司 | Manufacturing process for increasing density of MOM (metal oxide metal) capacitor |
| CN102867735A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Manufacture method of MOM capacitor |
| CN102931051B (en) * | 2012-10-09 | 2016-02-03 | 上海华力微电子有限公司 | Improve the method for MOM capacitor density |
| CN102881561B (en) * | 2012-10-09 | 2015-06-17 | 上海华力微电子有限公司 | Method for increasing MOM (mass optical memory) capacitance density |
| CN107731745B (en) * | 2017-10-18 | 2020-03-10 | 武汉新芯集成电路制造有限公司 | Preparation method of vase-shaped contact hole |
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| CN1412845A (en) * | 2001-10-19 | 2003-04-23 | 日本电气株式会社 | Semiconductor device and its mfg. method |
| CN102446843A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving high-performance copper interconnection by utilizing upper mask |
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| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| CN1412845A (en) * | 2001-10-19 | 2003-04-23 | 日本电气株式会社 | Semiconductor device and its mfg. method |
| CN102446843A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving high-performance copper interconnection by utilizing upper mask |
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