CN102474481A - Scrambling method and communication apparatus - Google Patents
Scrambling method and communication apparatus Download PDFInfo
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- CN102474481A CN102474481A CN2010800312408A CN201080031240A CN102474481A CN 102474481 A CN102474481 A CN 102474481A CN 2010800312408 A CN2010800312408 A CN 2010800312408A CN 201080031240 A CN201080031240 A CN 201080031240A CN 102474481 A CN102474481 A CN 102474481A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
Abstract
The present invention is directed to transmission of scrambled data in which the data redundancy has been suppressed and which has a bit sequence characteristic suitable for transmission. There are included the steps of: generating, by use of an isochronous scrambler, scrambled data from a reference frame in which a reference value has been added as the header of the reference frame; generating scrambled data of a compared frame in which a value different from the reference value has been added as the header of the compared frame; calculating an evaluation value related to the bit sequence characteristic of each scrambled data; selecting the evaluation value representative of the bit sequence characteristic that is the most suitable for transmission; transmitting the scrambled data of the selected evaluation value; if the scrambled data of the compared frame has been transmitted, correcting the value held by a shift register of the scrambler to a value specified in consideration of the time of completion of the scrambled data of the compared frame; and applying the value as corrected to the reference frame of a new data block.
Description
Technical field
Scrambling in the present invention relates to communicate by letter (scrambling) technology.
Background technology
During transmission during base band in digital communication transmits was handled, the Bit String experience that send was handled with DC balance that satisfies the balance between the number of indication 0 and 1 and the constraint the run length.This processing is called as " line coding (line coding) ".Line coding roughly is divided into two kinds of methods: a kind of is to carry out coding through adding redundant code to satisfy constraint; Another kind is through using scrambler to carry out coding to satisfy constraint randomly.
Based on the former method redundancy code to
(Ethernet
) used in the Manchester coding or 8B/10B encoding is representative.When transfer rate surpassed 10 Gbps, redundancy increased, and correspondingly, channel speed might increase.Therefore, the requirement for transmission/receiving equipment becomes strict.For example, under the situation of 8B/10B coding, the channel speed that is used for the information that transmits with 10 Gbps is 12.5 Gbps, thereby requires to have the transmission/receiving equipment that can support this channel speed.For the requirement that relates in this high-speed communication, it is preferably using back a kind of coding method of scrambler.
Use the method utilization of scrambler to come randomization to send bit sequence by the pseudo-random number sequence of easy-to-install LFSR (linear feedback shift register) generation.Such method for scrambling roughly is divided into synchronized model and motor synchronizing type.
Synchronously method for scrambling is to realize randomized method through information sequence with from the addition (XOR, XOR) of the pseudo-random number sequence of LFSR.Figure 14 shows according to the transmit leg scrambler 101 of synchronous method for scrambling and the ios dhcp sample configuration IOS DHCP of recipient's scrambler 102.The LFSR of transmit leg scrambler 101 has shift register 103a, and similarly, the LFSR of recipient's scrambler 102 has shift register 103b.The value of these registers (103a, 103b) expression is called as the LFSR state.
In this synchronous method for scrambling, between transmit leg (101) and recipient (102), need LFSR state fully synchronously.The favourable part of the method is mistake (bit reversal) and can propagate if take place.In as the SONET of multiplexed standard, as CCSDS of the recommendation of satellite communication or the like, adopt above synchronous method for scrambling.
The motor synchronizing method for scrambling be through the output bit storage that will pass by in LFSR and from the output of LFSR and the information sequence method of Calais's execution scrambling mutually.Figure 15 shows the ios dhcp sample configuration IOS DHCP of motor synchronizing method for scrambling.Transmit leg scrambler 201 has shift register 203a, and similarly, recipient's scrambler 202 has shift register 203b.Can propagate by number if the disadvantage of the method is that the mistake such as bit reversal takes place, and favourable part is need not carry out frame synchronization, thereby, possibly therefrom recovers if lock-out takes place from the connecting line of LFSR.
In addition, the motor synchronizing scrambling is favourable with regard to fail safe.As the security threat in the scrambling, can consider the for example network nuisance of the data of input offset scrambling effect.The assailant selects the initial condition of LFSR to harm sequence to generate at random in the case.Yet, can fully reduce the initial condition probability consistent that the assailant sets with actual initial condition through abundant increase LFSR length.
Use the motor synchronizing method for scrambling in the 64b/66b coding at
.64b/66b coding is a kind of like this method: will be divided into 64 bit data block according to the data sequence that generator polynomial g (x)=x^57+x^19+1 has experienced the motor synchronizing scrambling and add to the beginning of each data block and be used for 2 synchronous bit heads (" 01 " or " 10 "), thereby form 66 bit transmit frames.
In the line coding based on scrambling, the bit mode of deterioration communication characteristic is inevitable randomly.As relevant therewith technology, the known for example method of the disclosed CIMT of being called as (Conditional Inversion Master Transition, the condition counter-rotating is main to be changed) in the following PTL that lists 1 and 2.
The CIMT method keeps the accumulation of DC balance in advance and calculates the DC balance of the data block that will send.When the polarity of the DC balance of the polarity (direction of balance) of the DC of the data block that will send balance and previous data block was consistent with each other, all bits in the data block that send all were inverted and the piece that reverses is sent out.Otherwise the bit in this data block is sent by its primitive form.The head of at this moment, indicating this piece whether to be inverted is added to this piece.This makes that sending bit sequence can be adjusted to better direction of DC balance all the time.
{ quoted passage tabulation }
{ patent documentation }
{ PTL 1} United States Patent(USP) No. 5,022,051, specification
{ PTL 2} United States Patent(USP) No. 5,438,621, specification
Summary of the invention
{ technical problem }
According to disclosed method in PTL 1 and 2, can adjust accumulation DC balance; Yet method for scrambling is a synchronized model, thereby between transmit leg and recipient, needs to carry out frame synchronization.In addition, in above method, the mistake in the head causes the mistake in whole, thereby requires like disclosed defencive function among the PTL 2, and this has increased redundancy.In addition, for complete zero piece or complete one, bit value just is inverted, thereby does not change in the run length in the piece, and this makes and is difficult to reduce maximum run length.
Therefore an object of the present invention is to provide a kind of method for scrambling and communicator, be used to send the scrambled data that data redudancy has obtained suppressing and having the bit sequence characteristic that is suitable for sending.
{ scheme of dealing with problems }
According to a first aspect of the invention, a kind of method for scrambling is provided, has comprised: the beginning of fiducial value being added to data block as head is to form reference frame; Through using the motor synchronizing scrambler to generate the scrambled data of reference frame; Through the scrambled data addition of correction sequence and reference frame being generated the scrambled data of comparison frame, the value different with fiducial value is used as head and added data block in this comparison frame; According to evaluation criteria, calculate about the assessed value of the bit sequence characteristic of the scrambled data of reference frame with about another assessed value of the bit sequence characteristic of the scrambled data of frame relatively; From the assessed value that calculates, select the assessed value of expression optimum bit sequence characteristic for transmission; When selected assessed value during, send the scrambled data of reference frame corresponding to reference frame; And when selected assessed value during corresponding to frame relatively; The scrambled data that transmission obtains through the scrambled data addition with correction sequence and reference frame; The value that the shift register of scrambler is preserved is corrected to the value of when the completion of the scrambled data of considering the comparison frame, confirming, and calibrated value is applied to the reference frame of new data block.
According to a second aspect of the invention, a kind of communicator is provided, has comprised: head interpolation portion, this head interpolation portion add fiducial value to the beginning of data block to form reference frame as head; Scrambling portion, this scrambling portion generates the scrambled data of reference frame through using the motor synchronizing scrambler; The assessment detection unit, this assessment detection unit: through the scrambled data addition of correction sequence and reference frame being generated the scrambled data of comparison frame, the value different with fiducial value is used as head and added data block in this comparison frame; According to evaluation criteria, calculate about the assessed value of the bit sequence characteristic of the scrambled data of reference frame with about another assessed value of the bit sequence characteristic of the scrambled data of frame relatively; From the assessed value that calculates, select the assessed value of expression optimum bit sequence characteristic for transmission; And according to selecting output calibration sequence or null sequence; And adder; This adder is with the scrambled data addition of correction sequence or null sequence and reference frame and send addition results; Wherein, When selected assessed value during corresponding to frame relatively; The assessment detection unit is the result that will select offer scrambling portion and correction sequence is outputed to adder, and the scrambling portion value of when the result who selects is sent out, the shift register of scrambler being preserved definite value when being corrected to the completion in the scrambled data of considering the comparison frame, and calibrated value is applied to the reference frame of new data block.
{ advantageous effects of the present invention }
According to the present invention, can send the scrambled data that data redudancy has obtained suppressing and having the bit sequence characteristic that is suitable for sending.
Description of drawings
Fig. 1 is the block diagram of the communicator in the exemplary embodiment of the present invention.
Fig. 2 is the key diagram about the frame format in the exemplary embodiment of the present invention.
Fig. 3 is the flow chart about the basic operation of the communicator in the exemplary embodiment of the present invention.
Fig. 4 is the ios dhcp sample configuration IOS DHCP of the scrambler with calibration function in the exemplary embodiment of the present invention.
Fig. 5 is the ios dhcp sample configuration IOS DHCP of the assessment detection unit in the exemplary embodiment of the present invention.
Fig. 6 is about be used as the flow chart of the operation of detection unit under the situation of evaluation criteria in the exemplary embodiment of the present invention in weighted accumulation DC balance.
Fig. 7 be about in the exemplary embodiment of the present invention at the flow chart that uses the operation of detection unit under the situation of first and second evaluation criterias.
Fig. 8 be about in the exemplary embodiment of the present invention at the flow chart that uses the operation of detection unit under the situation of random bit sequence.
Fig. 9 is the block diagram that is used as detection unit under the situation of evaluation criteria in the exemplary embodiment of the present invention in weighted accumulation DC balance.
Figure 10 is another block diagram that is used as detection unit under the situation of evaluation criteria in the exemplary embodiment of the present invention in weighted accumulation DC balance.
Figure 11 is the diagrammatic sketch about the weighted accumulation DC balance in the exemplary embodiment of the present invention (ρ=0.9).
Figure 12 is the diagrammatic sketch about the weighted accumulation DC balance in the exemplary embodiment of the present invention (ρ=1.0).
Figure 13 is the diagrammatic sketch about the accumulation DC balance of a limited number of frame in the exemplary embodiment of the present invention.
Figure 14 is the key diagram about synchronous scrambler.
Figure 15 is the key diagram about the motor synchronizing scrambler.
{ label list }
101,201: the transmit leg scrambler
102,202: recipient's scrambler
103a, 103b, 203a, 203b: shift register
500: communicator
501: head interpolation portion
502: scrambler (scrambling portion) with calibration function
503: buffer
504: the assessment detection unit
505: adder
601: corrected value
701: correction sequence generation portion
702a, 702b: assessed value calculating part
703: detection unit
704: selector
1101,1202: register
1102: adder
1103: multiplier
1201: shift register
Embodiment
Fig. 1 shows the configuration of the transmitting system of the communicator 500 in the exemplary embodiment of the present invention.Head interpolation portion 501 adds the scrambling head with fiducial value, the frame that has the structure shown in Fig. 2 with generation to each beginning of the fixed-length block that obtains through dividing data.
Wherein fiducial value be set to the scrambling head frame corresponding to reference frame of the present invention.The bit number of scrambling head and fiducial value can be set to any value; In this exemplary embodiment, the bit number of head is set to 1 bit, and fiducial value is set to " 0 ".Be added under the situation of the data block of N bit at 1 bit scramble head as in this exemplary embodiment, the redundancy of frame is represented as (N+1)/N.Even be set at N under 32 the situation, the bit number of head is set to 1 bit makes that also redundancy is 1.03, thereby with the 8B/10B coding in obtain 1.25 compare, reduced redundancy fully.
More specifically, when selecting the assessed value of T1,504 outputs of assessment detection unit are after a while with the correction sequence M that describes.Correction sequence M is formed T1 by adder 505 with output (T0) from buffer 503 mutually, and T1 is sent out subsequently.Correction sequence M is the output sequence that under following situation, obtains: promptly, it is complete zero that the initial condition of LFSR is set to, and scrambling is applied to through scrambling head " 1 " being added to the frame ((N+1) bit) that full zero data blocks with bit length N obtains.On the other hand, when selecting the assessed value of T0, assessment detection unit 504 output null sequences (complete zero).
In addition, 504 of assessment detection units are that T0 or the information of T1 feed back to above-mentioned scrambler 502 as result of determination about the scrambled data that is assessed as optimum assessed value.
With reference to the flow chart shown in the figure 3, description had the basic operation of the communicator 500 of above-mentioned configuration.The process of Fig. 3 shows the handling process when handling the t data block.The state of LFSR when the processing with the corresponding frame of t data block is begun in the scrambler 502 is represented by S (t).
When the portion of interpolation from the head 501 received that wherein scrambling head " 0 " has been added to the reference frame of data block t, scrambler 502 was used scrambling to generate scrambled data T0 (step S401) to this reference frame in state S (t).The tentation data block length is the N bit, and then the total data length of T0 is (N+1) bit.The T0 that is generated is stored in the buffer 503, and is provided for assessment detection unit 504.
In addition, assessment detection unit 504 has been added to the frame (relatively frame) of data block t, generation scrambled data T1 (bit length: (N+1) bit) (step S403) among state S (t) based on scrambling head " 1 " wherein.Data T1 is according to utilizing T0 to generate the method for describing after a while.Assessment detection unit 504 calculates the assessed value (step S404) of the T1 that is generated.
After the assessed value of calculating T0 and T1, the assessed value that assessment detection unit 504 compares them and optimum bit sequence characteristic is represented in judgement based on evaluation criteria.Be better than under the situation of assessed value of T1 (" being " among the S405) in the assessed value of T0, assessment detection unit 504 is carried out control so that T0 is sent out.That is to say that assessment detection unit 504 is to the full null sequence of adder 505 output N bits.This full null sequence is quilt and T0 addition in adder 505, thereby final T0 is sent out (step S406).
On the other hand, be better than under the situation of assessed value of T0 (" denying " among the S405) in the assessed value of T1, assessment detection unit 504 is carried out control so that T1 is sent out.That is to say assessment detection unit 504 output calibration sequence M.This correction sequence M is quilt and T0 addition in adder 505, thereby final T1 is sent out (step S408).
But executed in parallel step S401 and S403.In addition, for the T0 that generates in order and T1 execution in step S402 and S404 in order.Hereinafter use description to realize the Hardware configuration of the communicator 500 of this processing.
Fig. 4 shows the ios dhcp sample configuration IOS DHCP of the scrambler 502 with calibration function.Scrambler 502 is based on the configuration of motor synchronizing scrambler (Figure 15), and is designed to adjust according to the result of determination of coming from assessment detection unit 504 feedbacks the state of LFSR.
The corrected value 601 of LFSR be the initial condition at LFSR be set to complete zero and " 100 ... 000 " (number of " 0 " is a data block length) situation about being transfused under the register value of the LFSR that obtains, and by representing with the corresponding bit number of the register capacity of LFSR.
Fig. 5 is the ios dhcp sample configuration IOS DHCP of assessment detection unit 504.Be imported into assessment detection unit 504 from the T0 of scrambler 502 outputs.The above-mentioned correction sequence M of correction sequence generation portion 701 outputs.This can realize through the precalculated value of storage in memory.Scrambled data T1 with comparison frame of header value " 1 " can be through obtaining at the Calais correction sequence M with the T0 that exports from scrambler 502 mutually.
One assessed value calculating part 702a calculates the assessed value of T0, and another assessed value calculating part 702b calculates the assessed value of T1.The processing that assessed value calculating part 702a and 702b carry out takes place according to the input in order of T0.Detection unit 703 is judged optimum bit sequence characteristic from the assessed value of T0 and T1, and result of determination is fed back to scrambler 502, and result of determination is provided to the control port of selector 704.
Under the situation of result of determination corresponding to head " 0 " from control port, selector 704 is exported the full null sequence of N bit as stated as the sequence that will be outputed to adder 505.In the case, the T0 from buffer 503 is sent out under the not reformed situation of value.Under the situation of result of determination corresponding to head " 1 " from control port, selector 704 outputs are from the correction sequence M of correction sequence generation portion 701.This M quilt converts T0 to T1 mutually with the T0 that exports from buffer 503, and this T1 is sent out subsequently.
[assessed value model 1]
The assessed value model that uses in the assessment detection unit 504 will be described below.With regard to realization, it is important being easy to calculate assessed value.Suppose that the DC balance (difference between the number of the number of " 0 " and " 1 ") based on the scrambled data of data block t is Y (t).For example, therein the number of " 0 " be 30 and the number of " 1 " be that (Frame length: N+1=64), DC balance Y (t) is-4 under the situation of 34 scrambled data.
Can utilize DC balance Y (t) and drop on the weight coefficient ρ (0≤ρ≤1) in the preset range, according to following formula (1) define based on continuous data block t (t=1,2,3 ...) and the weighted accumulation DC balance Z (t) of scrambled data.
Z (t)=ρ (Y (t)+Z (t-1))=ρ Y (t)+(ρ ^2) Y (t-1)+(ρ ^3) Y (t-2)+... Formula (1)
In following formula, Z (0) is set to 0.Under the situation of ρ=0, formula (1) is only represented the DC balance of present frame, and under the situation of ρ=1, formula (1) expression does not have the model of the decay in the past value.Through suitably setting the coefficient ρ that is used for weighting, weighted accumulation DC balance can be used in various types of transmission/receiving equipments and the transfer path aptly.
Be used as under the situation of evaluation criteria in weighted accumulation DC balance, assessed value calculating part 702a and 702b (Fig. 5) calculate DC balance Y0 (t) and the Y1 (t) of T0 and T1 respectively.Will be according to the flow chart description of Fig. 6 processing procedure of detection unit 703 in the case.
Respectively from the DC balance Y0 (t) of assessed value calculating part 702a and 702b input T0 and T1 and Y1 (t) time (step S800), the absolute value (step S801) of the weighted accumulation DC balance of detection unit 703 comparison Y0 (t) and Y1 (t).According to formula (1); For Y0 (t); As the present frame assessed value Y0 (t) and the absolute value of the addition results of assessed value Z (t-1) in the past | Y0 (t)+Z (t-1) | is obtained as the value that will compare, and for Y1 (t), | Y1 (t)+Z (t-1) | obtained the value that conduct will be compared.
Corresponding in above relatively demonstration with the assessed value of T0 | Y0 (t)+Z (t-1) | under the less situation (" being " among the S801); Detection unit 703 judges that the assessed value of T0 is optimum (step S802), and will give scrambler 502 about the feedback information of this judgement.In addition, in order to prepare for the assessment of subsequent data piece (t+1), detection unit 703 utilizes the Y0 (t) of present frame to upgrade weighted accumulation DC balance Z (t) (step S803) according to Z (t)=ρ (Y0 (t)+Z (t-1)).
On the other hand; Corresponding with the assessed value of T1 | Y1 (t)+Z (t-1) | under the less situation (" denying " among the S801); Detection unit 703 judges that the assessed value of T1 is optimum (step S804). then, detection unit 703 utilizes the Y1 (t) of present frame to upgrade weighted accumulation DC balance Z (t) (step S805) according to Z (t)=ρ (Y1 (t)+Z (t-1)).
[assessed value model 2]
As another example of the assessed value model that uses accumulation DC balance, can enumerate the method for the scrambled data of using nearest constant, numbers.Suppose that constant frame number is K+1, then the accumulation DC balance of this model can be by defining with following formula (2).
Z (t)=Y (t)+Y (t-1)+... + Y (t-K+1) | formula (2)
Under the situation of K=1, the same with the situation of ρ=0 in the formula (1), formula (2) expression is based on the assessed value model of the DC balance of present frame.In addition, the also accumulation DC balance that obtains from the combination of formula (1) and (2) of definable.In the implementation of preserving Z (t), the renewal of the Z (t) in the formula (2) can be carried out as represented with following formula (3).In this model, must preserve the DC equilibrium valve of a nearest K frame.
Z (t)=Y (t)+Z (t-1)-Y (t-K+1) formula (3)
[assessed value model 3]
Except the DC balance, the maximum run length of scrambled data also can be used as assessed value.This model is " 0 " run length or " 1 " run length (number of continuous " 0 " or " 1 ") among inspection T0 and the T1 and to utilize its maximum be the method for maximum run length as assessed value.In the assessment of this model, judge that for example maximum run length is more little, the bit sequence characteristic is just good more.
[assessed value model 4]
Can consider to use above-mentioned two types of assessed values promptly to accumulate the assessed value model of DC balance and maximum run length.To the processing procedure of detection unit 703 in the case be described according to the flow chart of Fig. 7.Below, suppose that using the method (Fig. 6) of weighted accumulation DC balance is first evaluation criteria, and the method for use maximum run length is second evaluation criteria.The priority of first evaluation criteria is set to such an extent that be higher than the priority of second evaluation criteria.
On the other hand; Difference between the assessed value of T0 and T1 is not more than under the situation of threshold value (" denying " among the S901); Detection unit 703 is judged between the assessed value based on the T0 of first evaluation criteria and T1 and is not had big-difference, and carries out another based on second evaluation criteria and judge (based on the judgement of maximum run length) (step S903).Then, detection unit 703 feeds back to scrambler 502 (step S904) to result of determination.
Through setting second evaluation criteria being result of determination with the information setting of T0 all the time; Promptly through exporting the optimum result of determination of assessed value of T0 under the situation that between based on two assessed values in the assessment of first evaluation criteria, does not have big-difference all the time; Can realize a model, just carry out when wherein the more only difference between assessed value between the assessed value surpasses threshold value.This has reduced the frequency of the correct operation of carrying out in the scrambler 502.
[assessed value model 5]
As the modification of the method (Fig. 7) of two types of evaluation criterias of above-mentioned use, available have a method of using random bit sequence.The processing procedure of the method is shown in Fig. 8.In illustrated process, this method uses weighted accumulation DC balance as first evaluation criteria, and this method adopts the alternative at random that uses random bit sequence as the second virtual evaluation criteria simultaneously.Below, with only describe with Fig. 7 in the difference of process.
Under the situation that is not more than threshold value based on the difference between the absolute value of the T0 of weighted accumulation DC balance and T1 (" denying " among the S901), detection unit 703 is read random bit sequence (step S1001).Random bit sequence can be arbitrarily, as long as it can not be inferred by the third party fully.For example, random bit sequence can be part value or the time parameter of the LFSR in the scrambler 502.
Do not correspond under the situation of predicted value (" denying " among the step S 1002) in random bit sequence, detection unit 703 judges that the scrambled data with optimum assessed value is T0 (step S1003).On the other hand, under the situation of random bit sequence corresponding to predicted value, detection unit 703 judges that T1 is optimum (step S1004).Thereby, adopt at random the alternative method to make and can improve the resistance of antagonism the attack of scrambled data.
As stated, according to this exemplary embodiment, can realize that redundancy has obtained the transmission that suppresses and have the scrambled data of the bit sequence characteristic that is suitable for sending.This feasible quality that can improve high-speed communication.
In this exemplary embodiment, the recipient of scrambled data only need be provided with existing motor synchronizing descrambler.That is to say that the head mistake in the scrambled data that receives does not require special layout.
The circuit scale of expection transmit leg possibly approximately be that traditional twice is big; Yet scrambler itself is a little circuit, thereby the increase of this circuit is very little for the influence of the scale of whole transmitter.In addition, the increase of the delay during transmission is just so short with about corresponding time of piece.
Be set under the situation with pseudo-random characteristics at correction sequence M, the improvement of DC balance is that " 0 " or " 1 " are randomness based on head; Yet in fact, the distribution of DC balance can be greatly improved.For example, suppose the extreme model that uses the accumulation DC balance do not have the decay in the past value, then accumulate DC and be equilibrated at and present even distribution when using existing scrambler; And, can obtain the zero-mean exponential distribution according to this exemplary embodiment.In addition, select correction sequence M to make by this way and can improve the assessed value such as maximum run length except that the DC balance.
＜＜example＞＞
With the more specifically example of describing above-mentioned exemplary embodiment.In order to realize above exemplary embodiment, must preestablish the corrected value 601 (Fig. 4) of LFSR and the output sequence M (Fig. 5) of the portion of correction sequence generation at that time 701.For example; The generator polynomial of supposing LFSR is that " g (x)=x^8+x^6+x^5+x^4+1 " and data block length N are 32 (frame length=33); Then corrected value 601 is set to " 1000_0100 " (8 bit), and correction sequence M is set to " 1011_0001_1110_1000_0111_1111_1001_0000_1 " (33 bit).
The obtaining of the result of determination from the end of data block to assessment detection unit 504, exist under the situation about postponing, corrected value 601 is considered this delay and is set.In the case, depend on the scrambling head of previous data block, proofread and correct to the beginning application delay of the current data block of buffer 503 according to retardation.Assessment detection unit 504 begins to handle after this correction is accomplished.
Correction sequence M preferably has the value that makes T0 and T1 not have correlation and with regard to DC balance, maximum run length and randomness, has superperformance.Under the situation of 64b/66b coding, use by the scrambler of representing with the generator polynomial of following formula (4).
G (x)=x^59+x^19+1 formula (4)
According to formula (4), correction sequence M is included in " 1 " continuous afterwards 38 bits " 0 " of beginning, and under the situation of N=32, seems for the not influence of scrambling head.In actual realization the of the present invention, need avoid this scrambler.
Simultaneously, when adopting with following formula (5) as generator polynomial, correction sequence M presents a full sequence under the situation of N=32.That is to say,, with regard to CIMT or accumulation DC balance, can obtain identical effect through generator polynomial being set at following formula (5).
G (x)=x^63+x^62+1 formula (5)
Fig. 9 shows according to the realization example that upgrades the detection unit 703 of weighted accumulation DC balance Z (t) with following formula (1).Illustrated detection unit 703 comprises the register 1101 that is used for storing in order Z (t), be used for the adder 1102 of the output of register 1101 and Y (t+1) addition and be used for the multiply each other multiplier 1103 of (constant times) of above addition results and weight coefficient ρ.When for example ρ=0.875, can realize ρ times with a subtraction through displacement once.
Figure 10 shows the realization example (K=4) according to the detection unit 703 of the accumulation DC balance Z (t) that upgrades a limited number of frame with following formula (3).Detection unit 703 in the case comprises adder 1102, be used to store shift register 1201 and the register 1202 that is used to store Z (t) of the Y (t) of a nearest K=4 frame.
Figure 11 and 12 diagrammatic sketch show separately in weighted accumulation DC balance and are used as the distribution that (Fig. 6) obtains under the situation of assessed value.The diagrammatic sketch of Figure 11 shows the distribution that under the situation of ρ=0.9, obtains, and the diagrammatic sketch of Figure 12 shows the distribution that under the situation of ρ=1.0, obtains.Under two kinds of situation, data block length N is set to 63 (frame length is 64), and the number of piece is 1,000,000, and the input data generate at random.
The distribution of accumulation DC balance indicates the value that (Y (t)+Z (t-1))/2 counting is obtained through in each data block.The vertical axis of diagrammatic sketch is a logarithmic scale.As the generator polynomial of LFSR, use with following formula (6).
G (x)=x^63+x^62+x^57+x^40+x^34+x^17+1 formula (6)
The distribution of each width of cloth figure among Figure 11 and 12 " traditional scheme " is the value that for each data block (64 bit) accumulation DC balance counting is obtained through under the situation of using typical scrambling.Can find out from the diagrammatic sketch of Figure 11 and 12, in example of the present invention, significantly improve the distribution of accumulation DC balance.For example, in Figure 11, suppose that the absolute value of accumulation DC balance surpasses 20, then the situation lower frequency in the typical scrambling that is indicated by " traditional scheme " becomes more than 1/100, and frequency for once reaches 1/1,000,000 in this example.Especially, in the model of the ρ shown in Figure 12=1.0, in " traditional scheme ", obtain evenly to distribute, and index access distributes in example of the present invention.
The accumulation DC balance that the diagrammatic sketch of Figure 13 shows under the setting identical with the situation of the diagrammatic sketch of Figure 11 and 12 based on a limited number of frame (K=4) of formula (3) is used as the distribution that obtains under the situation of evaluation criteria.Can find out that similar with the situation of Figure 11, in example of the present invention, the distribution of accumulation DC balance is improved.For example, the absolute value in accumulation DC balance among Figure 13 becomes more than 1/100 in " traditional scheme " above the relative frequency under 20 the situation, and in example of the present invention, is 1/10,000.
Exemplary embodiment of the present invention is not limited to above-mentioned exemplary embodiment, but can in the scope of following claim, revise as required.For example, though the bit number of scrambling head is 1 bit in above exemplary embodiment, it can be 2 bits or more.In this case, calculate the 2^d head assessed value (T0, T1 ... each is (N+d) bit naturally), and from 2^d assessed value, select of the best.
The assessment detection unit 504 of above exemplary embodiment is configured to the content of result of determination and how all feeds back result of determination.Yet as replacement, assessment detection unit 504 only can be configured to when result of determination indication T1, and promptly only (S409, Fig. 3), ability feeds back to scrambler 502 with result of determination when needs utilize corrected value 601 correction LFSR.
Though realize that according to communicator 500 available hardware of exemplary embodiment of the present invention it also can be by computer realization, this computer reads from computer readable recording medium storing program for performing and makes this computer can be used as the program of communicator 500 and carry out this program.
Though realize that according to the communication means available hardware of exemplary embodiment of the present invention it also can be by computer realization, this computer reads from computer readable recording medium storing program for performing and makes this computer can carry out the program of this method and carry out this program.
Above-mentioned exemplary embodiment is the preferred embodiments of the present invention, but scope of the present invention is not only limited to this exemplary embodiment, can carry out various modifications to it, does not depart from spirit of the present invention as long as these are revised.
The application incorporates the full content of this application into based on (on July 10th, 2009 submitted to) Japanese patent application No.2009-163798 and require its priority according to Paris Convention formerly here by reference.
Though described exemplary embodiment of the present invention in detail, should be appreciated that and to make various changes, substitute and replace it, and do not break away from the spirit and scope of the present invention that are defined by the following claims.In addition, the inventor hopes, even revised claim in course of the review, and also all equivalents of the invention of beachhead demand protection.
The part of above embodiment or all can be described as following remarks but is not limited thereto.
(remarks 1) a kind of method for scrambling comprises:
The beginning of fiducial value being added to data block as head is to form reference frame;
Through using the motor synchronizing scrambler to generate the scrambled data of said reference frame;
Through the scrambled data addition of correction sequence and said reference frame being generated the scrambled data of comparison frame, the value different with said fiducial value is used as head and added said data block in this comparison frame;
According to evaluation criteria, calculating is about the assessed value of the bit sequence characteristic of the scrambled data of said reference frame with about said relatively another assessed value of the bit sequence characteristic of the scrambled data of frame;
From the assessed value that calculates, select the assessed value of expression optimum bit sequence characteristic for transmission;
When selected assessed value during corresponding to said reference frame, the scrambled data of sending said reference frame; And
When selected assessed value during corresponding to said relatively frame; The scrambled data that transmission obtains through the scrambled data addition with said correction sequence and said reference frame; The value that the shift register of said scrambler is preserved is corrected to the value of when considering the completion of the said relatively scrambled data of frame, confirming, and calibrated value is applied to the reference frame of new data block.
(remarks 2) also comprises according to remarks 1 described method for scrambling:
When the DC balance of using each scrambled data is as the bit sequence characteristic, utilize the accumulation of assessed value in the past to calculate said assessed value;
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past; And
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
(remarks 3) is according to remarks 2 described method for scrambling, wherein
Said assessed value is used the coefficient weighting with the value in the preset range.
(remarks 4) is according to remarks 1 described method for scrambling, wherein
Said assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
(remarks 5) also comprises according to remarks 1 described method for scrambling:
Calculate the assessed value of each scrambled data according to first evaluation criteria;
When the difference between the assessed value that calculates surpasses threshold value, select to represent the assessed value of said optimum bit sequence characteristic according to said first evaluation criteria; And
When the difference between the assessed value that calculates is not more than said threshold value, according to the assessed value that second evaluation criteria different with said first evaluation criteria calculated the assessed value of each scrambled data and said optimum bit sequence characteristic is represented in selection according to said second evaluation criteria from the assessed value that calculates.
(remarks 6) is according to remarks 5 described method for scrambling, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate; And this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate, and
The assessed value of being represented by said second evaluation criteria selects from said first assessed value and said second assessed value, with the different value of representing by said first evaluation criteria of assessed value.
(remarks 7) is according to remarks 6 described method for scrambling, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said first assessed value is by with the coefficient weighting with the value in the preset range.
(remarks 8) is according to remarks 6 or remarks 7 described method for scrambling; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, then said method for scrambling also comprises:
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past, and
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
(remarks 9) comprises according to remarks 1 described method for scrambling:
Calculate the assessed value of each scrambled data according to first evaluation criteria;
When the difference between the assessed value that calculates surpasses threshold value, select to represent the assessed value of said optimum bit sequence characteristic according to said first evaluation criteria;
When the difference between the assessed value that calculates is not more than said threshold value, obtain random bit sequence;
When said random bit sequence during, select the scrambled data of the scrambled data of said relatively frame as assessed value with the said optimum bit sequence characteristic of expression corresponding to predicted value; And
When said random bit sequence does not correspond to said predicted value, select the scrambled data of the scrambled data of said reference frame as assessed value with the said optimum bit sequence characteristic of expression.
(remarks 10) is according to remarks 9 described method for scrambling, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
(remarks 11) is according to remarks 10 described method for scrambling, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said first assessed value is by with the coefficient weighting with the value in the preset range.
(remarks 12) is according to remarks 10 or remarks 11 described method for scrambling; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, then said method for scrambling also comprises:
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past, and
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
(remarks 13) is according to any one the described method for scrambling in the remarks 1 to 12, wherein
The bit number of said head is 1 bit.
(remarks 14) a kind of communicator comprises:
Head interpolation portion, this head interpolation portion add fiducial value to the beginning of data block to form reference frame as head;
Scrambling portion, this scrambling portion generates the scrambled data of said reference frame through using the motor synchronizing scrambler;
The assessment detection unit; This assessment detection unit: through the scrambled data addition of correction sequence and said reference frame being generated the scrambled data of comparison frame; The value different with said fiducial value is used as head and added said data block in this comparison frame; According to evaluation criteria; Calculating is selected the assessed value of expression optimum bit sequence characteristic for transmission about the assessed value of the bit sequence characteristic of the scrambled data of said reference frame with about said relatively another assessed value of the bit sequence characteristic of the scrambled data of frame from the assessed value that calculates; And export said correction sequence or null sequence according to said selection; And
Adder, this adder is with the scrambled data addition of said correction sequence or said null sequence and said reference frame and send addition results,
Wherein, When selected assessed value during corresponding to said relatively frame; Said assessment detection unit offers the result of said selection said scrambling portion and said correction sequence is outputed to said adder; And the value that said scrambling portion preserves the shift register of said scrambler when the result of said selection is sent out is corrected to the value of when considering the completion of the said relatively scrambled data of frame, confirming, and calibrated value is applied to the reference frame of new data block.
(remarks 15) is according to remarks 14 described communicators, wherein
Said assessment detection unit utilizes the accumulation of assessed value in the past to calculate said assessed value when the DC balance of using each scrambled data is as the bit sequence characteristic; Utilize the assessed value of the said optimum bit sequence characteristic of expression to upgrade the accumulation of the assessed value in said past, and utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
(remarks 16) is according to remarks 15 described communicators, wherein
Said assessment detection unit comes said assessed value weighting with the coefficient with the value in the preset range.
(remarks 17) is according to remarks 14 described communicators, wherein
Said assessment detection unit calculates said assessed value when the maximum run length of using each scrambled data is as the bit sequence characteristic.
(remarks 18) is according to remarks 14 described communicators, wherein
Said assessment detection unit calculates the assessed value of each scrambled data according to first evaluation criteria;, the difference between the assessed value that calculates selects to represent the assessed value of said optimum bit sequence characteristic when surpassing threshold value according to said first evaluation criteria; And when the difference between the assessed value that calculates is not more than said threshold value, according to the assessed value that second evaluation criteria different with said first evaluation criteria calculated the assessed value of each scrambled data and said optimum bit sequence characteristic is represented in selection according to said second evaluation criteria from the assessed value that calculates.
(remarks 19) is according to remarks 18 described communicators, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate; And this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate, and
The assessed value of being represented by said second evaluation criteria selects from said first assessed value and said second assessed value, with the different value of representing by said first evaluation criteria of assessed value.
(remarks 20) is according to remarks 19 described communicators, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said assessment detection unit comes the said first assessed value weighting with the coefficient with the value in the preset range.
(remarks 21) is according to remarks 19 or remarks 20 described communicators; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, so
The utilization of said assessment detection unit representes that the assessed value of said optimum bit sequence characteristic upgrades the accumulation of the assessed value in said past, and utilizes through the accumulation of upgrading and calculate the assessed value about the scrambled data of new data block.
(remarks 22) is according to remarks 14 described communicators, wherein
Said assessment detection unit: the assessed value of calculating each scrambled data according to first evaluation criteria; When the difference between the assessed value that calculates surpasses threshold value; The assessed value of said optimum bit sequence characteristic is represented in selection according to said first evaluation criteria; When the difference between the assessed value that calculates is not more than said threshold value; Obtain random bit sequence, during corresponding to predicted value, select the scrambled data of the scrambled data of said relatively frame as assessed value with the said optimum bit sequence characteristic of expression in said random bit sequence; And when said random bit sequence does not correspond to said predicted value, select the scrambled data of the scrambled data of said reference frame as assessed value with the said optimum bit sequence characteristic of expression.
(remarks 23) is according to remarks 22 described communicators, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
(remarks 24) is according to remarks 23 described communicators, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said assessment detection unit with coefficient with the value in the preset range to the said first assessed value weighting.
(remarks 25) is according to remarks 23 or remarks 24 described communicators; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, so
The utilization of said assessment detection unit representes that the assessed value of said optimum bit sequence characteristic upgrades the accumulation of the assessed value in said past, and utilizes through the accumulation of upgrading and calculate the assessed value about the scrambled data of new data block.
(remarks 26) is according to any one the described communicator in the remarks 14 to 25, wherein
Said head interpolation portion adds a bit value as said head to said data block.
(remarks 27) a kind of program makes computer serve as according to any one the described communicator in the remarks 14 to 26.
{ industrial applicability }
The present invention is suitable to be applied to the line coding in the for example optical communication.
Claims (27)
1. method for scrambling comprises:
The beginning of fiducial value being added to data block as head is to form reference frame;
Through using the motor synchronizing scrambler to generate the scrambled data of said reference frame;
Through the scrambled data addition of correction sequence and said reference frame being generated the scrambled data of comparison frame, the value different with said fiducial value is used as head and added said data block in this comparison frame;
According to evaluation criteria, calculating is about the assessed value of the bit sequence characteristic of the scrambled data of said reference frame with about said relatively another assessed value of the bit sequence characteristic of the scrambled data of frame;
From the assessed value that calculates, select the assessed value of expression optimum bit sequence characteristic for transmission;
When selected assessed value during corresponding to said reference frame, the scrambled data of sending said reference frame; And
When selected assessed value during corresponding to said relatively frame; The scrambled data that transmission obtains through the scrambled data addition with said correction sequence and said reference frame; The value that the shift register of said scrambler is preserved is corrected to the value of when considering the completion of the said relatively scrambled data of frame, confirming, and calibrated value is applied to the reference frame of new data block.
2. method for scrambling according to claim 1 also comprises:
When the DC balance of using each scrambled data is as the bit sequence characteristic, utilize the accumulation of assessed value in the past to calculate said assessed value;
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past; And
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
3. method for scrambling according to claim 2, wherein
Said assessed value is used the coefficient weighting with the value in the preset range.
4. method for scrambling according to claim 1, wherein
Said assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
5. method for scrambling according to claim 1 also comprises:
Calculate the assessed value of each scrambled data according to first evaluation criteria;
When the difference between the assessed value that calculates surpasses threshold value, select to represent the assessed value of said optimum bit sequence characteristic according to said first evaluation criteria; And
When the difference between the assessed value that calculates is not more than said threshold value, according to the assessed value that second evaluation criteria different with said first evaluation criteria calculated the assessed value of each scrambled data and said optimum bit sequence characteristic is represented in selection according to said second evaluation criteria from the assessed value that calculates.
6. method for scrambling according to claim 5, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate; And this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate, and
The assessed value of being represented by said second evaluation criteria selects from said first assessed value and said second assessed value, with the different value of representing by said first evaluation criteria of assessed value.
7. method for scrambling according to claim 6, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said first assessed value is by with the coefficient weighting with the value in the preset range.
8. according to claim 6 or the described method for scrambling of claim 7; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, then said method for scrambling also comprises:
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past, and
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
9. method for scrambling according to claim 1 comprises:
Calculate the assessed value of each scrambled data according to first evaluation criteria;
When the difference between the assessed value that calculates surpasses threshold value, select to represent the assessed value of said optimum bit sequence characteristic according to said first evaluation criteria;
When the difference between the assessed value that calculates is not more than said threshold value, obtain random bit sequence;
When said random bit sequence during, select the scrambled data of the scrambled data of said relatively frame as assessed value with the said optimum bit sequence characteristic of expression corresponding to predicted value; And
When said random bit sequence does not correspond to said predicted value, select the scrambled data of the scrambled data of said reference frame as assessed value with the said optimum bit sequence characteristic of expression.
10. method for scrambling according to claim 9, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
11. method for scrambling according to claim 10, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said first assessed value is by with the coefficient weighting with the value in the preset range.
12. according to claim 10 or the described method for scrambling of claim 11; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, then said method for scrambling also comprises:
Utilize the assessed value of representing said optimum bit sequence characteristic to upgrade the accumulation of the assessed value in said past, and
Utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
13. according to any one the described method for scrambling in the claim 1 to 12, wherein
The bit number of said head is 1 bit.
14. a communicator comprises:
Head interpolation portion, this head interpolation portion add fiducial value to the beginning of data block to form reference frame as head;
Scrambling portion, this scrambling portion generates the scrambled data of said reference frame through using the motor synchronizing scrambler;
The assessment detection unit, this assessment detection unit: through the scrambled data addition of correction sequence and said reference frame being generated the scrambled data of comparison frame, the value different with said fiducial value is used as head and added said data block in this comparison frame; According to evaluation criteria; Calculating is about the assessed value of the bit sequence characteristic of the scrambled data of said reference frame with about said relatively another assessed value of the bit sequence characteristic of the scrambled data of frame; From the assessed value that calculates, select the assessed value of expression optimum bit sequence characteristic for transmission, and export said correction sequence or null sequence according to said selection; And
Adder, this adder is with the scrambled data addition of said correction sequence or said null sequence and said reference frame and send addition results,
Wherein, When selected assessed value during corresponding to said relatively frame; Said assessment detection unit offers the result of said selection said scrambling portion and said correction sequence is outputed to said adder; And the value that said scrambling portion preserves the shift register of said scrambler when the result of said selection is sent out is corrected to the value of when considering the completion of the said relatively scrambled data of frame, confirming, and calibrated value is applied to the reference frame of new data block.
15. communicator according to claim 14, wherein
Said assessment detection unit utilizes the accumulation of assessed value in the past to calculate said assessed value when the DC balance of using each scrambled data is as the bit sequence characteristic; Utilize the assessed value of the said optimum bit sequence characteristic of expression to upgrade the accumulation of the assessed value in said past, and utilize through the accumulation of upgrading and calculate assessed value about the scrambled data of said new data block.
16. communicator according to claim 15, wherein
Said assessment detection unit comes said assessed value weighting with the coefficient with the value in the preset range.
17. communicator according to claim 14, wherein
Said assessment detection unit calculates said assessed value when the maximum run length of using each scrambled data is as the bit sequence characteristic.
18. communicator according to claim 14, wherein
Said assessment detection unit calculates the assessed value of each scrambled data according to first evaluation criteria;, the difference between the assessed value that calculates selects to represent the assessed value of said optimum bit sequence characteristic when surpassing threshold value according to said first evaluation criteria; And when the difference between the assessed value that calculates is not more than said threshold value, according to the assessed value that second evaluation criteria different with said first evaluation criteria calculated the assessed value of each scrambled data and said optimum bit sequence characteristic is represented in selection according to said second evaluation criteria from the assessed value that calculates.
19. communicator according to claim 18, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate; And this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate, and
The assessed value of being represented by said second evaluation criteria selects from said first assessed value and said second assessed value, with the different value of representing by said first evaluation criteria of assessed value.
20. communicator according to claim 19, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said assessment detection unit comes the said first assessed value weighting with the coefficient with the value in the preset range.
21. according to claim 19 or the described communicator of claim 20; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, so
The utilization of said assessment detection unit representes that the assessed value of said optimum bit sequence characteristic upgrades the accumulation of the assessed value in said past, and utilizes through the accumulation of upgrading and calculate the assessed value about the scrambled data of new data block.
22. communicator according to claim 14, wherein
Said assessment detection unit: the assessed value of calculating each scrambled data according to first evaluation criteria; When the difference between the assessed value that calculates surpasses threshold value; The assessed value of said optimum bit sequence characteristic is represented in selection according to said first evaluation criteria; When the difference between the assessed value that calculates is not more than said threshold value; Obtain random bit sequence, during corresponding to predicted value, select the scrambled data of the scrambled data of said relatively frame as assessed value with the said optimum bit sequence characteristic of expression in said random bit sequence; And when said random bit sequence does not correspond to said predicted value, select the scrambled data of the scrambled data of said reference frame as assessed value with the said optimum bit sequence characteristic of expression.
23. communicator according to claim 22, wherein
The assessed value of being represented by said first evaluation criteria is the value of from first assessed value and second assessed value, selecting; This first assessed value is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is when the maximum run length of using each scrambled data is as the bit sequence characteristic, to calculate.
24. communicator according to claim 23, wherein
When utilizing in as the bit sequence characteristic accumulation of assessed value in the past to calculate said first assessed value with the DC balance of each scrambled data, said assessment detection unit with coefficient with the value in the preset range to the said first assessed value weighting.
25. according to claim 23 or the described communicator of claim 24; Wherein, If the assessed value of being represented by said first evaluation criteria is when the DC balance of using each scrambled data is as the bit sequence characteristic, to utilize first evaluation criteria of the accumulation calculating of assessed value in the past, so
The utilization of said assessment detection unit representes that the assessed value of said optimum bit sequence characteristic upgrades the accumulation of the assessed value in said past, and utilizes through the accumulation of upgrading and calculate the assessed value about the scrambled data of new data block.
26. according to any one the described communicator in the claim 14 to 25, wherein
Said head interpolation portion adds a bit value as said head to said data block.
27. a program makes computer serve as according to any one the described communicator in the claim 14 to 26.
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| PCT/JP2010/061531 WO2011004838A1 (en) | 2009-07-10 | 2010-07-07 | Scrambling method and communication apparatus |
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| WO2017193787A1 (en) * | 2016-05-11 | 2017-11-16 | Huawei Technologies Co., Ltd. | Method and apparatus for indicating control information in a wireless frame |
| US11330465B2 (en) | 2016-05-11 | 2022-05-10 | Huawei Technologies Co., Ltd. | Method and apparatus for indicating control information in a wireless frame |
| US11743766B2 (en) | 2016-05-11 | 2023-08-29 | Huawei Technologies Co., Ltd. | Method and apparatus for indicating control information in a wireless frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102474481B (en) | 2014-09-24 |
| WO2011004838A1 (en) | 2011-01-13 |
| JP5182424B2 (en) | 2013-04-17 |
| JPWO2011004838A1 (en) | 2012-12-20 |
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