CN102497215B - Miniature wireless signal receiving and processing circuit - Google Patents
Miniature wireless signal receiving and processing circuit Download PDFInfo
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- CN102497215B CN102497215B CN201110328642.0A CN201110328642A CN102497215B CN 102497215 B CN102497215 B CN 102497215B CN 201110328642 A CN201110328642 A CN 201110328642A CN 102497215 B CN102497215 B CN 102497215B
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- signal receiving
- processing circuit
- receiving processing
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Abstract
The invention relates to a miniature wireless signal receiving and processing circuit, which comprises a wireless signal receiving circuit, a signal receiving and processing circuit, a trigger circuit, a timing signal generating circuit, a collision switch circuit, a delayed output circuit, an auxiliary pulse generating circuit, a voltage-stabilizing circuit and a transient voltage protecting circuit, wherein the wireless signal receiving circuit is used for receiving setting signals, the signal receiving and processing circuit is used for decoding the setting signals into setting code signals, the timing signal generating circuit is used for generating timing signals, the collision switch circuit is switched on when being collided by external force, the auxiliary pulse generating circuit is used for outputting auxiliary pulse signals, the voltage-stabilizing circuit is respectively connected with the timing signal generating circuit, the signal receiving and processing circuit, the delayed output circuit and the auxiliary pulse generating circuit, and the transient voltage protecting circuit is switched on when voltage of a power source exceeds regulated peak voltage. The miniature wireless signal receiving and processing circuit has complete functions and high safety and is small in size.
Description
Technical field
The present invention relates to a kind of reception of wireless signals treatment circuit.
Background technology
Wireless fusee signal receives and treatment circuit, needs on-the-spot reception to set signal, and makes device by the instruction works that sets signal.Existing this type of circuit, owing to limited by installation volume, does not generally have the functions such as circuit protection, security protection, self-disabling, and the fail safe of circuit is reduced greatly; And available circuit size is generally bigger than normal, minimum circuit size is about 30mm * 30mm, makes it cannot be for less device.
Summary of the invention
The reception of wireless signals treatment circuit that the object of this invention is to provide a kind of telotism, small volume, this circuit has the functions such as transient voltage protection, voltage stabilizing, security protection, working mode selection, self-disabling, and volume is much smaller than available circuit.
For achieving the above object, the technical solution used in the present invention is:
A Miniature wireless signal receiving processing circuit, it comprises
Wireless signal receiving circuit, described wireless signal receiving circuit sets signal by responding to continuous reception, and carries out exporting after full-wave rectification, filtering, dividing potential drop;
Signal receiving processing circuit, the first input end of described signal receiving processing circuit is connected with the output of described wireless signal receiving circuit, the output output of described wireless signal receiving circuit sets signal to the first input end of described signal receiving processing circuit, described signal receiving processing circuit becomes to set code signal by the described signal decoding that sets, and produces output signal according to the described code signal that sets;
Circuits for triggering, the first input end of described circuits for triggering is connected with power supply, and the second input of described circuits for triggering is connected with the output of described signal receiving processing circuit, and described circuits for triggering trigger according to described output signal;
It also comprises
Timing signal produces circuit, and the output of described timing signal generation circuit is connected with the second input of described signal receiving processing circuit, and described timing signal produces circuit and produces timing signal;
Impact switch circuit, described impact switch circuit is connected with the 3rd input of described signal receiving processing circuit, conducting when described impact switch circuit is subject to external impacts;
Time delay output circuit, the output of described time delay output circuit is connected with the 3rd input of described circuits for triggering;
False impulse produces circuit, and described false impulse produces the output output auxiliary pulse signal of circuit; After described auxiliary pulse signal output, described signal receiving processing circuit is through the delay time of regulation, after the pulse number producing through described timing signal generation circuit, or receive after the Continuity signal of described impact switch circuit, it is to described circuits for triggering output high level signal;
Voltage stabilizing circuit, the input of described voltage stabilizing circuit is connected with described power supply, the output of described voltage stabilizing circuit is connected with described timing signal generation circuit, described signal receiving processing circuit, described time delay output circuit, described false impulse generation circuit respectively, and described voltage stabilizing circuit is stabilized in input supply voltage under the required operating voltage of each circuit;
Transient voltage protection circuit, described transient voltage protection circuit is connected between described power supply and ground, when described supply voltage surpasses the peak voltage of regulation, described transient voltage protection circuit conducting.
Preferably, described timing signal produces circuit and comprises signal amplification unit, signal comparing unit, and described signal comparing unit comprises comparator; The input input transducing signal of described signal amplification unit, described signal amplification unit amplifies rear output amplifying signal by described transducing signal, and the reference level of the signal comparing unit that described amplifying signal input is described and described comparator relatively and by described comparator is exported square-wave signal.
Preferably, described signal amplification unit comprises one stage signal amplification module, second signal amplification module, and output described and signal amplification module is connected with the input of described second signal amplification module.
Preferably, the described code signal that sets is 23 signals, and it comprises 18 binary-coded decimal delay time informations, 1 working method information, 4 bit check codes; Described working method information determines the working method of described signal receiving processing circuit.
Preferably, described signal receiving processing circuit comprises the first working method and two kinds of working methods of the second working method, when described working method information is 0, described signal receiving processing circuit is in the first described working method, when described working method information is 1, described signal receiving processing circuit is in the second described working method;
Described signal receiving processing circuit has the tenth end and the tenth one end; The tenth described end is connected with described impact switch circuit, and when described impact switch circuit turn-on, the tenth described end becomes high level; The tenth described one end becomes high level after described signal receiving processing circuit powers on a period of time;
When described signal receiving processing circuit is during in described the first working method, through described delay time information, after determined time of delay or the tenth described one end and the tenth described end all become the described output signal of the backward described circuits for triggering output of high level high level to described signal receiving processing circuit;
When described signal receiving processing circuit is during in described the second working method, described signal receiving processing circuit only after the tenth described one end and the tenth described end all become high level to the described output signal of described circuits for triggering output high level.
Preferably, when described in described signal receiving processing circuit set signal set correct after, described signal receiving processing circuit is locked by data receiver function, no longer receive the described signal that sets, described timing signal produces circuit and starts working, if check errors receives the described signal that sets again.
Preferably, described voltage stabilizing circuit comprises low-dropout regulator.
Preferably, described time delay output circuit is the comparator that carries reference level, between the in-phase end of described comparator and ground, be connected with electric capacity, when the voltage at described electric capacity two ends surpasses the reference level of described comparator, described comparator output high level makes described circuits for triggering conducting.
Because technique scheme is used, the present invention compared with prior art has following advantages: Miniature wireless signal receiving processing circuit telotism of the present invention, the fail safe of circuit is higher, and its volume is small and exquisite.
Accompanying drawing explanation
Accompanying drawing 1 is the circuit block diagram of Miniature wireless signal receiving processing circuit of the present invention.
Accompanying drawing 2 is the circuit diagram of the voltage stabilizing circuit of Miniature wireless signal receiving processing circuit of the present invention.
Accompanying drawing 3 is the circuit diagram that the timing signal of Miniature wireless signal receiving processing circuit of the present invention produces the one stage signal amplification module of circuit.
Accompanying drawing 4 is the circuit diagram that the timing signal of Miniature wireless signal receiving processing circuit of the present invention produces the second signal amplification module of circuit.
Accompanying drawing 5 is the circuit diagram that the timing signal of Miniature wireless signal receiving processing circuit of the present invention produces the signal comparing unit of circuit.
Accompanying drawing 6 is the circuit diagram of the wireless signal receiving circuit of Miniature wireless signal receiving processing circuit of the present invention.
Accompanying drawing 7 is the circuit diagram of the signal receiving processing circuit of Miniature wireless signal receiving processing circuit of the present invention.
Accompanying drawing 8 is the circuit diagram of the circuits for triggering of Miniature wireless signal receiving processing circuit of the present invention.
Accompanying drawing 9 is the circuit diagram of the time delay output circuit of Miniature wireless signal receiving processing circuit of the present invention.
In above accompanying drawing: 1, voltage stabilizing circuit; 2, false impulse produces circuit; 3, transient voltage protection circuit; 4, timing signal produces circuit; 5, wireless signal receiving circuit; 6, signal receiving processing circuit; 7, circuits for triggering; 8, impact switch circuit; 9, time delay output circuit.
Embodiment
Below in conjunction with embodiment shown in the drawings, the invention will be further described.
Embodiment mono-: shown in accompanying drawing 1.
A Miniature wireless signal receiving processing circuit, it comprises that wireless signal receiving circuit 5, signal receiving processing circuit, circuits for triggering 7, timing signal produce circuit 4, impact switch circuit 8, time delay output circuit 9, false impulse generation circuit 2, voltage stabilizing circuit 1, transient voltage protection circuit 3.
Wireless signal receiving circuit 5 receives and sets signal.Shown in accompanying drawing 6, setter constantly transmitting sets signal, and by responding to continuous acceptance, this sets signal to wireless signal receiving circuit 5, and carries out exporting after full-wave rectification, filtering, dividing potential drop.
The output of wireless signal receiving circuit 5 is connected with the first input end of signal receiving processing circuit 6, through wireless signal receiving circuit 5, sets signal input signal receiving processing circuit 6.
Shown in accompanying drawing 7, signal receiving processing circuit 6 will set signal decoding and become to set code signal, and carry out verification, judgement, locking, and it produces output signal according to setting code signal.
Setting code signal is 23 signals, and it comprises 18 binary-coded decimal delay time informations, 1 working method information, 4 bit check codes; Working method information determines the working method of signal receiving processing circuit 6.
Signal receiving processing circuit 6 comprises the first working method and two kinds of working methods of the second working method, when working method information is 0, signal receiving processing circuit 6 is in the first working method, and when working method information is 1, signal receiving processing circuit 6 is in the second working method.
Signal receiving processing circuit 6 has the tenth end and the tenth one end.The tenth end is the 3rd input of signal receiving processing circuit 6 and is connected with impact switch circuit 8.Conducting when impact switch circuit 8 is subject to external impacts; When 8 conducting of impact switch circuit, the tenth end becomes high level.And the tenth one end becomes high level after signal receiving processing circuit 6 powers on a period of time.
When signal receiving processing circuit 6 is during in the first working method, signal receiving processing circuit 6 is exported high level after after determined time of delay or the tenth one end and the tenth end all become high level through delay time information.When signal receiving processing circuit 6 is during in the second working method, signal receiving processing circuit 6 is only exported high level after the tenth one end and the tenth end all become high level.
Shown in accompanying drawing 8, the first input end of circuits for triggering 7 is connected with power supply, and the second input of circuits for triggering 7 is connected with the output of signal receiving processing circuit 6.Circuits for triggering 7 comprise storage capacitor, thyristor etc., and the high level that it is exported according to signal receiving processing circuit 6 triggers.After powering on, storage capacitor is recharged, when thyristor grid is triggered, and thyristor conducting, storage capacitor passes through load discharge.Shown in accompanying drawing 9, the output of time delay output circuit 9 is connected with the 3rd input of circuits for triggering 7.Time delay output circuit 9, for carrying the comparator of reference level, is connected with electric capacity between the in-phase end of comparator and ground, when the voltage at electric capacity two ends surpasses the reference level of comparator, comparator output high level makes circuits for triggering 7 conductings.Under normal circumstances, now circuits for triggering 7 conducting, thereby time delay output circuit 9 is inoperative.When making for a certain reason signal receiving processing circuit 6 not export high level, time delay output circuit 9 makes circuits for triggering 7 conductings.
Timing signal produces the output of circuit 4 and the second input of signal receiving processing circuit 6 is connected, and timing signal produces circuit 4 and produces timing signal.Timing signal produces circuit 4 and comprises signal amplification unit, signal comparing unit.
Signal amplification unit comprises one stage signal amplification module, second signal amplification module, and the output of signal amplification module is connected with the input of second signal amplification module.Shown in accompanying drawing 3 and accompanying drawing 4, the input of signal amplification unit input transducing signal, first signal amplification unit carries out filtering, biasing to the weak signal of the μ V level of transducer input, then amplifies.Adopting two-stage to amplify can make multiplication factor reach 80dB.
Shown in accompanying drawing 5, signal comparing unit comprises comparator.After amplifying unit amplifies, the amplifying signal input signal comparing unit of output, relatively and by comparator exports square-wave signal with the reference level of comparator.Like this, just the comfortable μ V level weak signal of transducer has been changed into the square-wave signal of CMOS level, this square-wave signal input signal receiving processing circuit 6, as timing signal.In signal receiving processing circuit 6, set signal set correct after, signal receiving processing circuit 6 is locked by data receiver function, no longer receives and sets signal, timing signal produces circuit 4 and starts working.If check errors again receives and sets signal.
False impulse produces the output output auxiliary pulse signal of circuit 2.After auxiliary pulse signal output, signal receiving processing circuit 6 is through the time of delay of regulation, after the pulse number producing through timing signal generation circuit 4, or receive after impact switch circuit 8 Continuity signals, it is to circuits for triggering 7 output high level signals.
Shown in accompanying drawing 2, the input of voltage stabilizing circuit 1 is connected with power supply, the output of voltage stabilizing circuit 1 produces circuit 2 and is connected with timing signal generation circuit 4, signal receiving processing circuit 6, time delay output circuit 9, false impulse respectively, and it is stabilized under the required operating voltage of each circuit by input supply voltage and offers each circuit.Because input supply voltage value constantly reduces in time, for making full use of power supply, voltage stabilizing circuit 1 adopts low-dropout regulator, and the input of voltage stabilizing circuit 1 can be low to moderate only than the high 0.2V of normal output.
Transient voltage protection circuit 3 is connected between power supply and ground; when supply voltage is during in normal fluctuation range; it is inoperative; when supply voltage surpasses the peak voltage of regulation; transient voltage protection circuit 3 conductings; thereby the high-energy that peak voltage is produced discharges, play the effect of protection voltage stabilizing circuit 1.
Above-mentioned Miniature wireless signal receiving processing circuit has the functions such as transient voltage protection, voltage stabilizing, security protection, working mode selection, self-disabling, and circuit size is 14mm * 16mm, much smaller than the volume of available circuit.Can be in minimum at present device.
Above-described embodiment is only explanation technical conceive of the present invention and feature, and its object is to allow person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, within all should being encompassed in protection scope of the present invention.
Claims (8)
1. a Miniature wireless signal receiving processing circuit, it comprises
Wireless signal receiving circuit, described wireless signal receiving circuit sets signal by responding to continuous reception, and carries out exporting after full-wave rectification, filtering, dividing potential drop;
Signal receiving processing circuit, the first input end of described signal receiving processing circuit is connected with the output of described wireless signal receiving circuit, the output output of described wireless signal receiving circuit sets signal to the first input end of described signal receiving processing circuit, described signal receiving processing circuit becomes to set code signal by the described signal decoding that sets, and produces output signal according to the described code signal that sets;
Circuits for triggering, the first input end of described circuits for triggering is connected with power supply, and the second input of described circuits for triggering is connected with the output of described signal receiving processing circuit, and described circuits for triggering trigger according to described output signal;
It is characterized in that: it also comprises
Timing signal produces circuit, and the output of described timing signal generation circuit is connected with the second input of described signal receiving processing circuit, and described timing signal produces circuit and produces timing signal;
Impact switch circuit, described impact switch circuit is connected with the 3rd input of described signal receiving processing circuit, conducting when described impact switch circuit is subject to external impacts;
Time delay output circuit, the output of described time delay output circuit is connected with the 3rd input of described circuits for triggering;
False impulse produces circuit, and described false impulse produces the output output auxiliary pulse signal of circuit; After described auxiliary pulse signal output, described signal receiving processing circuit is through the delay time of regulation, after the pulse number producing through described timing signal generation circuit, or receive after the Continuity signal of described impact switch circuit, it is to described circuits for triggering output high level signal;
Voltage stabilizing circuit, the input of described voltage stabilizing circuit is connected with described power supply, the output of described voltage stabilizing circuit is connected with described timing signal generation circuit, described signal receiving processing circuit, described time delay output circuit, described false impulse generation circuit respectively, and described voltage stabilizing circuit is stabilized in input supply voltage under the required operating voltage of each circuit;
Transient voltage protection circuit, described transient voltage protection circuit is connected between described power supply and ground, when described supply voltage surpasses the peak voltage of regulation, described transient voltage protection circuit conducting.
2. Miniature wireless signal receiving processing circuit according to claim 1, is characterized in that: described timing signal produces circuit and comprises signal amplification unit, signal comparing unit, and described signal comparing unit comprises comparator; The input input transducing signal of described signal amplification unit, described signal amplification unit amplifies rear output amplifying signal by described transducing signal, and the reference level of the signal comparing unit that described amplifying signal input is described and described comparator relatively and by described comparator is exported square-wave signal.
3. Miniature wireless signal receiving processing circuit according to claim 2, it is characterized in that: described signal amplification unit comprises one stage signal amplification module, second signal amplification module, the output of described one stage signal amplification module is connected with the input of described second signal amplification module.
4. Miniature wireless signal receiving processing circuit according to claim 1, is characterized in that: the described code signal that sets is 23 signals, and it comprises 18 binary-coded decimal delay time informations, 1 working method information, 4 bit check codes; Described working method information determines the working method of described signal receiving processing circuit.
5. Miniature wireless signal receiving processing circuit according to claim 4, it is characterized in that: described signal receiving processing circuit comprises the first working method and two kinds of working methods of the second working method, when described working method information is 0, described signal receiving processing circuit is in the first described working method, when described working method information is 1, described signal receiving processing circuit is in the second described working method;
Described signal receiving processing circuit has the tenth end and the tenth one end; The tenth described end is connected with described impact switch circuit, and when described impact switch circuit turn-on, the tenth described end becomes high level; The tenth described one end becomes high level after described signal receiving processing circuit powers on a period of time;
When described signal receiving processing circuit is during in described the first working method, through described delay time information, after determined time of delay or the tenth described one end and the tenth described end all become the described output signal of the backward described circuits for triggering output of high level high level to described signal receiving processing circuit;
When described signal receiving processing circuit is during in described the second working method, described signal receiving processing circuit only after the tenth described one end and the tenth described end all become high level to the described output signal of described circuits for triggering output high level.
6. Miniature wireless signal receiving processing circuit according to claim 1, it is characterized in that: when described in described signal receiving processing circuit set signal set correct after, described signal receiving processing circuit is locked by data receiver function, no longer receive the described signal that sets, described timing signal produces circuit and starts working, if check errors receives the described signal that sets again.
7. Miniature wireless signal receiving processing circuit according to claim 1, is characterized in that: described voltage stabilizing circuit comprises low-dropout regulator.
8. Miniature wireless signal receiving processing circuit according to claim 1, it is characterized in that: described time delay output circuit is the comparator that carries reference level, between the in-phase end of described comparator and ground, be connected with electric capacity, when the voltage at described electric capacity two ends surpasses the reference level of described comparator, described comparator output high level makes described circuits for triggering conducting.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110328642.0A CN102497215B (en) | 2011-10-26 | 2011-10-26 | Miniature wireless signal receiving and processing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110328642.0A CN102497215B (en) | 2011-10-26 | 2011-10-26 | Miniature wireless signal receiving and processing circuit |
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| CN102497215A CN102497215A (en) | 2012-06-13 |
| CN102497215B true CN102497215B (en) | 2014-08-20 |
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| CN104165747B (en) * | 2014-09-04 | 2017-08-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of portable detector of mechanical switch falling weight impact test |
| CN109211036B (en) * | 2018-09-06 | 2019-11-05 | 北方电子研究院安徽有限公司 | A kind of decoding circuit wirelessly set in fuse |
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| US5867775A (en) * | 1994-10-28 | 1999-02-02 | The Nippon Signal Co., Ltd. | Fail-safe signal transmitting apparatus producing a logical product of an input signal and a carrier signal |
| US20050136835A1 (en) * | 2003-12-17 | 2005-06-23 | Matsushita Electric Industrial Co., Ltd. | Radio relay device |
| CN1858770A (en) * | 2006-04-26 | 2006-11-08 | 孟友新 | RFID device based on 802.11 b |
| CN1849991A (en) * | 2006-05-26 | 2006-10-25 | 清华大学 | Integrated circuit system for bidirectional digital wineless endoscope capsule |
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Granted publication date: 20140820 Termination date: 20171026 |