CN102522393A - 封装器件及封装多个集成电路的组件 - Google Patents

封装器件及封装多个集成电路的组件 Download PDF

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CN102522393A
CN102522393A CN2011104050701A CN201110405070A CN102522393A CN 102522393 A CN102522393 A CN 102522393A CN 2011104050701 A CN2011104050701 A CN 2011104050701A CN 201110405070 A CN201110405070 A CN 201110405070A CN 102522393 A CN102522393 A CN 102522393A
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integrated circuit
pad
packaging
lead
package substrates
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CN102522393B (zh
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V·R·万卡纳尔
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Apple Inc
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Apple Computer Inc
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Abstract

本发明涉及封装器件及封装多个集成电路的组件。在一个实施例中，集成电路包括相应于第一接口的第一物理层接口电路，集成电路通过第一接口与外部通信，第一物理层接口电路包括在形成第一接口的每个导线上通信的电路，并沿着所述集成电路的第一边被物理定位；和相应于第二接口的第二物理层接口电路，集成电路通过第二接口与外部通信，第二物理层接口电路包括在形成第二接口的每个导线上通信的电路，并沿着集成电路的第二边被物理定位，第二边与第一边相邻。应用集成电路(IC)和其它IC的封装方案，可以支持应用IC和其它IC的叠层芯片封装以及应用IC和其它IC的层叠封装两者。消除了对层叠封装方案的支持并减小了封装基底的大小。

Description

封装器件及封装多个集成电路的组件
本申请是于2010年3月12日提交的题为“集成电路及其封装器件及封装多个集成电路的方法和组件”的专利申请第201010135302.1号的分案申请。 
技术领域
本发明涉及集成电路领域，并且更具体地，涉及集成电路的封装。 
背景技术
通常封装集成电路芯片，以便提供与其它组件诸如电路板的更方便并且更可靠的连接，以防止集成电路损坏等。最初，每种集成电路芯片被容纳在其自己的封装(package，或称“封装器件”)内，该封装被焊接或以其它方式被电气并且物理连接到电路板上，其中在该电路板上还连接有其它集成电路(每个集成电路在其自己的封装内)和其它电子组件。 
更近以来，已经使用层叠封装连接(package-on-package connection)以便减小包括集成电路的器件的大小。在这种情况下，第一集成电路被封装在包括连接电路板的引脚并且还包括与另一个集成电路的引脚相匹配的安装点的封装内。另一个集成电路可被通过安装点安装到第一集成电路上。 
正在开始使用的另一种策略是叠层芯片封装(chip-on-chip package)。在叠层芯片封装中，多个集成电路芯片被堆叠在一起，并且彼此直接连接(例如，没有介于中间的封装)。在叠层芯片(chip-on-chip)方案中，芯片以相同取向被堆叠(即，“面向上”)。叠层中的最大芯片在底部，并且从最大芯片的顶部沿着较小芯片的侧 面向上，例如，在较小芯片的侧面之上，通过从较小芯片上的焊盘延伸的丝焊环(wire bond loop)形成连接。堆叠的芯片被包括在用于连接到其它组件的单个封装内。叠层芯片封装提供了比层叠封装方案更小的整体体积。 
每种封装方案同样具有相关联的风险。层叠封装技术具有比将单独封装的电路安装到电路板上更大的风险(例如，在部件操作不正确并且必须在制造时被去除的方面，在由于较新技术中尚未显现的缺陷引起的过早失效方面，在由于单个芯片失效引起的部件过早失效方面等)。叠层芯片封装也具有比层叠封装技术更大的风险。因此，在考虑产品组件的封装时，产品设计者要在风险和产品目标之间进行权衡。 
发明内容
在一个实施例中，提供了一种用于应用集成电路(IC)和一个或多个其它IC的封装方案。该封装方案可以支持应用IC(倒装芯片连接(flip-chip connection)到封装基底)和其它IC(非倒装芯片取向)的叠层芯片封装。该封装方案还可以支持应用IC和其它IC的层叠封装式封装。封装基底可以包括与应用IC相邻的第一组焊盘，以便支持与其它IC的叠层芯片连接。这些焊盘可被连接到在应用IC之下延伸的导线，以便连接到倒装芯片安装的应用IC。第二组焊盘可被连接到用于层叠封装方案的封装引脚。如果叠层芯片方案证明是可靠的，可以消除对层叠封装方案的支持，并且可以减小封装基底的大小。 
附图说明
下面的详细描述参考了附图，现在简要描述这些附图。 
图1是示出了集成电路的一个实施例的方框图； 
图2是用于该集成电路的封装的一个实施例的方框图； 
图3是经封装的集成电路的一个实施例的侧视图； 
图4是该集成电路和两个其它集成电路的叠层芯片封装的一个实施例的方框图； 
图5是该集成电路和两个其它集成电路的层叠封装式封装的一个实施例的方框图； 
图6是该集成电路和两个其它集成电路的叠层芯片封装的另一个实施例的方框图； 
图7是封装该集成电路的一个实施例的流程图； 
图8是一种系统的一个实施例的方框图。 
虽然容易对本发明进行各种修改和各种形式的替换，在附图中以示例的方式示出了特定实施例，并且此处将对这些特定实施例进行详细说明。然而，应当理解，附图和详细说明不旨在将本发明局限于公开的特定形式，而是相反，本发明覆盖落在由所附权利要求限定的本发明的精神和范围内的所有修改、等同物和替换方案。此处使用的标题仅用于组织目的，并且不意味着被用于限制描述的范围。如本申请中使用的，单词“可以”被用于许可含义(即，意味着具有可能)，而不是强制含义(即，意味着必须)。类似地，单词“包括”(“include”，“including”和“includes”)意味着包括但不限于仅仅包括。 
各种单元、电路或其它组件可被描述为“配置为”执行一种任务或多个任务。在这种上下文中，“配置为”是对这样的结构的宽泛表述，该结构一般意味着“具有这样的电路”，该电路在操作过程中执行该任务或多个任务。从而，即使当该单元/电路/组件当前未被接通时，该单元/电路/组件也可被配置为执行该任务。一般地，构成相应于“配置为”的结构的电路可以包括硬件电路和/或存储可以执行以便实现所述操作的程序指令的存储器。存储器可以包括诸如静态或动态随机访问存储器的易失存储器和/或诸如光盘或磁盘存储设备、闪存、可编程只读存储器等的非易失存储器。类似地，出于描述方便起见，各种单元/电路/组件可被描述为执行任务或多个任务。这种描述应当被解释为包括短语“配置为”。单元/电路/组件配置为执行一种或多种任务的表述在表述上不旨在涉及35U.S.C.§112第6段对单元/电路/组件的解释。 
具体实施方式
在一个实施例中，一种封装方案可以支持叠层芯片封装(chip-on-chip packaging)，并且还可以保持对用于相同芯片的层叠封装式封装(package-on-package packaging)的支持。层叠封装实现可以是经证实的技术(与叠层芯片实现相比)，并且因此其风险因子可能低于叠层芯片实现。叠层芯片实现可以具有更高的风险因子，但是还可以减小整个封装器件的大小。如果叠层芯片实现证实是可靠的，可以去除对层叠封装方案的支持，并且可以减小封装器件大小。在另一方面，如果叠层芯片实现证实不可靠，在层叠封装方案中可以使用相同的封装将叠层底部的集成电路与其它集成电路的单独封装实例(instance)封装在一起。因此，通过使用相同的封装基底保持对层叠封装实现的支持，此处描述的封装方案可以允许叠层芯片封装，同时弥补叠层芯片封装的风险。 
在某些实施例中，可以使用该封装方案支持任意一种封装选择。例如，叠层芯片实现可能更昂贵，并且因此可能希望用于这种费用可能是合理的终端产品中。其它终端产品可能不支持较高成本，但是可能对空间较不敏感，并且可以使用层叠封装实现。 
在一个实施例中，该封装方案可以支持底部集成电路的倒装芯片附接，以及两个或更多个集成电路在底部集成电路上面的堆叠。该封装方案可以包括具有连接到集成电路的倒装芯片连接的导线的封装基底。该导线可以从所述集成电路之下向外延伸，并且可以包括靠近所述集成电路侧面的第一组焊盘。这些焊盘可用于连接堆叠在该集成电路顶部上的芯片。所述导线还可以延伸到第二组焊盘，提供这些焊盘以便连接封装引脚。封装引脚可以支持该封装方案的层叠封装部分。 
在一个实施例中，所述导线可以包括连接到底部集成电路上的两个物理层接口电路的两组导线。这两个物理层接口电路可被沿着所述集成电路的两个相邻边物理定位，并且用于所述两组导线的相应焊盘可被分别定位在这两个边附近。堆叠在顶部的集成电路芯片可以在集成电路的一个边上具有焊盘，并且可以与封装基底上的焊盘对齐。通过以彼此正交的取向堆叠集成电路，可以形成两组独立的连接。 
例如，在一个实施例中，堆叠在顶部的集成电路芯片可以是诸如动态随机存取存储器(DRAM)、静态RAM(SRAM)、闪存等的存储器集成电路。所述物理层接口电路可以是用于对接这些存储器的物理层(例如，驱动地址和控制信号，并且根据操作驱动或接收数据信号)。底部集成电路(此处被称为应用集成电路)中可以存在相应的存储器控制器。 
下面将使用具有堆叠存储器集成电路的应用集成电路作为例子。然而，可以使用集成电路的任意集合。在一个实施例中，应用集成电路可以具有堆叠在顶部的两个或更多个集成电路(例如，存储器集成电路，或可被连接到应用集成电路的任意其它类型的集成电路)。堆叠的集成电路可以具有彼此相同的类型，并且可以与应用集成电路不同。 
现在转到图1，图1示出了应用集成电路(IC)10的一个实施例的方框图。在示出的实施例中，应用IC 10包括核心电路12、存储器控制器14A-14B和存储器控制器物理层接口(PHY)电路16A-16B。如图1所示，核心电路12耦接到存储器控制器14A-14B，存储器控制器14A-14B分别耦接到PHY电路16A-16B。可控塌陷芯片连接(controlled collapse chip connection)(C4)凸点(bump)位于PHY电路16A-16B之上，诸如PHY电路16A之上的C4凸点18A-18B以及PHY电路16B之上的C4凸点18C-18D。 
物理层接口电路一般可包括在信号线上通信以便形成接口的电路。一般地，该接口可以包括在信号线上驱动和接收的信号，以及对驱动/接收这些信号的电气要求和用于使用这些信号进行通信的协议的集合。例如，在通用接口上通常使用总线或分组协议。可以定义定制接口以便与特定类型的芯片或其它设备通信(例如，用于与存储器芯片通信的存储器接口)。该接口可以具有任意定义和协议，并且信号线的整体传输执行所述协议并且提供所述通信。物理层接口电路可以至少执行驱动和接收所述信号的电气要求，包括定时要求。如果使用线编码(例如，8b-10b编码)，则物理层还可以执行编码和解码。 
PHY电路16A-16B可以是用于存储器接口的物理层接口电路。因此，PHY电路16A-16B被配置为将存储器接口的信号传递到要在封装中堆叠在应用IC 10之上(或如下面更详细描述的，被连接到在层叠封装实现内)的存储器IC。 
图1的实施例旨在示出PHY电路16A-16B沿着应用IC 10的边的物理位置。PHY电路16A-16B可以不占据所述边的整个长度，但是沿着所述边被定位。具体地，PHY电路16A-16B被沿着应用IC10的相邻边定位。IC的相邻边可以是终止于公共点的边。以另一种方式看，如果使用方形或矩形IC 10，则相邻边可以彼此正交。因此在图1中，左边与上边和下边相邻，并且上边和下边还和右边相邻。如图1所示，PHY电路16A-16B被定位在右边和上边上。然而，上下左右全都相对于特定视角，在这个例子中为图1所示的取向。 
在各种情况下，将PHY电路16A-16B连接到封装器件的信号线的C4凸点位于相应的PHY电路16A-16B之上。因此，相应于两个存储器接口的C4凸点也沿着相邻边被定位。图1示出了两行C4凸点，但是一般可以提供任意数目的行，以便提供用于存储器接口的连接。C4凸点可被应用于应用IC 10的顶面(图1中可见的表面)，并且与应用IC 10内的最后一层金属接触。信号数目取决于存储器接口定义，并且它们一般可以包括地址线、控制线和数据线。图中示出的C4凸点的数目(并且类似地，如下面更详细讨论的其它焊盘的数目)不旨在表示信号线的完整数目。 
存储器控制器14A-14B和核心电路12可以不必如图1所示那样被物理定位。存储器控制器14A-14B可被耦接到相应的PHY电路16A-16B，并且一般可以包括与核心电路12通过接口连接以便接收存储器请求的电路、用于存储所述存储器请求的队列、用于选择将被传输的请求的电路等。核心电路12执行为应用IC 10设计好的操作。一般地，可以针对任意操作集合设计应用IC。例如，在一个实施例中，应用IC 10可以包括被配置为执行在一种指令集体系内定义的指令的一个或多个处理器核心。应用IC 10可以是芯片级系统(SOC)，并 且除了处理器核心之外，可以实现各种外围电路(例如，音频和/或视频处理、图形、直接存储器访问(DMA)引擎、输入/输出桥电路等)。在其它实施例中，应用IC 10可以是不包括处理器的固定功能的集成电路。 
集成电路一般可以包括形成在单个半导体基底上的任意电路。其上形成有电路的基底也被称为芯片。通过在半导体基底的一个平面附近向基底注入杂质，并且在该平面上构造诸如铝、铜、多晶硅等的导电材料层，以便形成晶体管和其它组件并且将它们连接在一起，可以在半导体基底的一个平面上形成电路。还可以应用绝缘层，以便提供导电材料之间的绝缘。集成电路的边可以是所述平面上靠近该集成电路外围的区域。 
现在转到图2，图2示出了封装基底20的一部分的方框图。封装基底20与封装引脚并且可能还有塑料封装保护层(或金属盖)一起形成应用IC 10(以及如果适用，包括在叠层芯片封装内的堆叠IC)的封装。应用IC 10在封装基底20上的覆盖区(footprint)以虚线框22表示。虽然为了方便绘图，该覆盖区被示出为在图2中的一侧上，在某些实施例中，封装基底20实际上可以从应用IC 10的每个边延伸相等距离。该覆盖区一般可以指当封装基底20安装在应用IC 10上时应用IC 10将位于封装基底20上的面积。在倒装芯片安装的实施例中，该覆盖区包括将连接应用IC 10的C4凸点的端点。 
封装基底20包括布置为当应用IC 10被以倒装芯片的取向安装在封装基底20上时，连接应用IC 10上的C4凸点的导线集合。导线24，例如，可以连接到PHY电路16A中的C4凸点，并且导线26可以连接到PHY电路16B中的C4凸点。由于C4凸点在应用IC 10的顶面上并且在应用IC 10的外围之内，导线24和26在应用IC 10的覆盖区下延伸。每个导线24和26包括连接到应用IC 10上的C4凸点的端点28。如下所述，端点28可以是焊盘。 
导线24和26在应用IC 10的覆盖区下从端点28向外延伸。紧挨着应用IC 10的覆盖区的外侧，在导线24和26上形成一组焊盘30。 因此，焊盘30靠近(或邻近)应用IC 10的两个相邻侧。在某些情况下，焊盘30可以接触应用IC 10的覆盖区，或甚至可以略微延伸到该覆盖区之下。由于焊盘30将被用于接触连接到叠层芯片安装内的堆叠IC的导线，可能希望焊盘30尽可能靠近该覆盖区。 
导线24和26还从焊盘30向外延伸到封装基底20上的第二组焊盘32。焊盘32被形成为具有连接封装器件的封装引脚的尺寸。具体地，焊盘32和相应的封装引脚被布置为在层叠封装配置中连接到经封装的IC。在示出的实施例中，层叠封装配置包括封装基底20顶面的边附近的引脚(如图2所示)。取决于封装的IC的大小，还可以向着封装基底20的顶面的内部提供引脚。还可以提供封装基底20的顶面除图2所示的边之外的其它边上的引脚。在这些实施例中，导线24和26可以从焊盘30布线到其它边。 
因此，图2的封装基底20支持叠层芯片(使用焊盘30)和层叠封装方案(使用焊盘32)两者。可以使用某个数目的原始部件验证叠层芯片方案，并且如果该技术证明可靠，可以通过去除焊盘32和从焊盘30延伸到焊盘32的导线，然后减小封装基底的大小来减小封装基底20(并且从而减小封装器件大小)。如果叠层芯片方案证明不可靠(例如，正确操作的部件的产量太低，部件寿命太低等)，则封装基底20已经支持更加确定的层叠封装方案，并且可以使用封装基底20生产层叠封装部件。在验证叠层芯片方案时发现/执行的对封装基底20的任意调试/修改被反映在层叠封装方案使用的封装基底20内，并且从而可以用相同的封装基底20立刻开始生产。 
除了连接到导线24和26的端点28之外，封装基底20还可以包括其它端点34以便连接到应用IC 10的其它C4凸点。与这些C4凸点相关联的信号线可用于连接未包括在利用应用IC 10实施的叠层芯片或层叠封装方案中的其它组件。即，应用IC 10到这些其它组件的连接可以通过电路板或其它常规连接机制。端点32可被通过封装基底20的各种层耦接到封装基底20的底面(与图2中可见的面的相对)。封装器件可以包括用于连接电路板或其它互连结构的封装基底20底 面处的封装引脚。虽然在一个实施例中，类似于应用于封装基底20的可见的面的引脚，该封装引脚也是焊料球，底面处的封装引脚不必与顶面处的封装引脚相同。 
因此，封装基底20可以包括导线层和绝缘体层，以便允许将端点34连接到封装基底20底面上的正确引脚。封装基底20内的层数可以基于将C4凸点连接到正确引脚时遇到的布线拥塞(wiring congestion)数量，每个导线所需的电流容量等而改变。封装基底20可以类似于较小规模的印刷电路板技术。封装基底20中使用的导电材料(包括导线24和26)可以包括铜、金、铝、任意前面材料彼此的合金以及任意前面材料和其它材料的合金等中的一个或多个。绝缘层可由任意绝缘材料制成(例如，塑料、陶瓷等)。 
一般地，可以用以附图标记36指示的绝缘层覆盖图2中可见的封装基底20的顶面。该绝缘层可以覆盖大部分导线24和26。然而，在端点28和34以及焊盘30和32处在绝缘层32中形成开口。这些开口允许到端点/焊盘的电连接。焊盘一般可以为平面，可以相对于该平面形成电连接。焊盘可以简单地就是所述开口，或该开口可被填充有诸如上述任意导电材料的导电材料。焊盘可以比导线大(例如，导线24和26)，以便简化连接焊盘的机械处理。 
如此处使用的，封装引脚一般可以是可用于形成封装的集成电路和诸如电路板的其它组件之间的电气连接以及至少部分机械连接的任意导体。可以使用各种封装引脚，诸如上述的焊料球(以及由其它导电的并且机械稳定的材料形成的球)。封装引脚还可以是诸如在引脚栅格阵列(PGA)上使用的相对直的金属引脚，这些引脚可被焊接到其它组件或被插入插槽内。其它引脚可能不是直的(例如，用于表面安装的鸥翼或勾脚(J lead)设计)。封装引脚还可以包括导电焊盘，诸如在焊区栅格阵列(LGA)封装中使用的导电焊盘。 
如前所述，在这个实施例中，针对应用IC 10的倒装芯片安装设计封装基底20。即，如图1所示IC10的顶面面对封装基底20的顶面，并且顶面上的C4凸点与端点28和34电连接。因此，如果应用IC 10 被安装到图2中的封装基底20上，从图2的视角可以看到应用IC 10的背面(与图1中可见的表面相对的表面)。C4凸点可由焊料制成，虽然其它替换方案可以包括金球或模压支线(molded stud)、导电塑料、电镀凸点等。倒装芯片安装与“面向上”丝焊技术形成对照。 
图3是封装的应用IC 10的一个实施例的侧视图。在这个实施例中封装器件40包括封装基底20、封装引脚42和用于层叠封装安装的封装引脚44。例如，如果叠层芯片方案被认为可靠，其它实施例可以不包括封装引脚44。在这个实施例中封装引脚42和44都是焊料球，但是其它实施例可以为引脚42和/或44实现其它引脚。为了避免使得图3中的IC10模糊不清，未示出全部封装引脚44。在某些实施例中，如果需要，引脚44可以沿着封装基底20的长度和/或绕着封装基底20的表面区域延伸，以便与将在层叠封装配置中附接到引脚44的封装的IC中的引脚汇合。 
如图3所示，焊料球44的高度高于应用IC 10，以便支持层叠封装安装。这种高度差异一般足以确保在焊料球回流以便连接其它IC(例如，在一个实施例中，存储器IC)之后，可以在封装器件40和其它IC的封装之间形成坚固的机械和电连接。在某些实施例中，可以给应用IC 10应用粘合材料，以便帮助形成机械连接。 
图3中未示出塑封，但是其可被可选择地用于某些实施例中，可以给封装基底20的顶面和附加在该顶面上的应用IC 10应用塑封。塑封可以保护应用IC 10不被损坏。在这些实施例中，焊料球44的高度可以大于应用IC 10和该塑封。 
如图3所示，引脚42一般可以布置在应用IC 10之下。在某些实施例中，引脚42可以延伸出应用IC 10的覆盖区，但是可以集中在该覆盖区周围，以便允许如果以后消除层叠封装选项，减小封装基底20。 
图4示出了封装基底20的视图，其中应用IC 10倒装芯片安装在封装基底20上，并且两个IC50和52(例如，存储器IC)堆叠在应用IC 10上。IC50和52可被以“面向上”的取向堆叠(例如，与应 用IC 10的倒装芯片取向相反)。 
在示出的实施例中，IC50和52沿着IC50和52的一个边包括相应的焊盘54和56。焊盘54和56布置为当IC50和52被堆叠在IC10上时与封装基底20上的焊盘30对齐。这种配置可以允许叠层芯片方案与IC10以及IC50和52的相对大小无关。在某些实施例中(例如，如果当改进IC10的设计时改变了IC10的大小)，这种无关性是有用的。 
在示出的实施例中，IC50和52被以彼此正交的取向堆叠。如此处关于IC的取向所使用的，术语正交一般可以指它们在近似平行于IC50和52的在其上形成有IC电路(以及焊盘54和56)的表面的平面内相差大约90度地定向。术语正交一般可以包括由于机械公差、定位不精确等引起的略微偏离90度取向。以另一种方式看，正交取向名义上可被视为垂直90度，但是允许由于IC机械定位不完美而在特定实例中产生的改变。 
在示出的实施例中，IC52在IC50的顶部上错开，暴露出用于连接的焊盘54。其它实施例可以应用从焊盘54向外延伸的丝焊环路，可以使用丝焊环路形成与焊盘30的连接，并且从而不需要错开的堆叠。 
采用如图4所示堆叠的IC50和52(以及以IC50和52之间以及IC50和应用IC 10之间的绝缘粘合层保持到位)，可以分别应用导线以便将焊盘30连接到焊盘54和56。例如，导线58将焊盘30连接到IC50上的焊盘54，并且导线60将焊盘30连接到IC52上的焊盘56。导线58或60可被连接到焊盘30，并且当向着相应焊盘54或56抬离封装基底20的表面时，可贴附在IC10、50和52的侧面上。然后导线可以“弯折”，以便形成从图4的立体图中看到的到IC50和52顶面上的相应焊盘54和56的电连接。导线58和60可以在大体垂直的方向上抬离封装基底20的平坦表面，沿着IC50和52的侧面向上，然后水平形成与焊盘54和56的连接。 
可以用任意方式形成导线58和60。例如，可以通过从适合的高 精度溅射设备溅射导电环氧树脂形成导线58和60，所述高精度溅射设备诸如是可从Asymtek(Carlsbad，CA)获得的Axiom分配器。例如，该处理可以类似于Vertical Circuits公司(Scotts Valley，CA)使用的处理。 
注意，虽然图4示出了两个IC50和52，但在其它实施例中，可以在IC10上堆叠更多的IC。例如，如果IC50和52是存储器IC，可以堆叠附加的存储器IC50和52，它们的取向与IC50和IC52的取向形成交替。可以连接与IC50在相同方向上定向的IC，以便形成存储器控制器14A-14B之一的存储器通道。可以连接与IC50在相同方向上定向的IC，以便形成另一个存储器控制器14A-14B的存储器通道。存储器通道可以包括：形成存储器IC群组以便提供到/来自IC10的更宽的数据传输宽度、交错存储器IC以便提供更低延迟的存取和/或形成存储器IC组。 
如果堆叠多于两个IC，堆叠还可以包括类似于图4所示的错开IC，以便暴露每个IC用于连接的焊盘。对于并联连接的信号线，导线58和60可以分别连接到焊盘54和56，并且然后可以在用于避免与IC的顶面电连接的绝缘粘合物之上水平跨越IC50和52的顶面延伸(分别)，然后垂直沿着堆叠IC的侧面向上延伸到下一个焊盘。可替换地，如果使用丝焊环路，堆叠可以如前所述那样错开。对于非并联信号线，可以用类似方式形成导线，但是可以使用绝缘粘合物以便避免在堆叠中连接到较低IC上的焊盘。 
在某些实施例中，可以给封装基底20的顶面、应用IC 10、IC50和52以及导线58和60应用封装物(例如，塑料)，以便保护该组件不受损害。注意，每个焊盘30可被通过导线58或60连接到相应的焊盘54或56。为了附图的简单性，图4中未示出所有导线58和60。 
图5是如图3所示的封装器件40中的封装后的应用IC 10的侧视图，其中具有层叠封装方案中的附加的封装存储器IC70和72。在这种情况下，存储器IC70和72是DRAM，但是其它实施例可以实现任意存储器IC。另外，可以使用不是存储器IC的其它IC。 
图6示出了消除了对层叠封装方案的支持的已经减小了封装基底20的实施例。例如，如果断定叠层芯片方案可靠到足以消除层叠封装方案，可以执行这种减小。在示出的实施例中，封装基底20被减小到支持焊盘30的大小。在其它实施例中，封装基底20底部上的引脚42可以是控制数量或减小的因素。即，可以在仍然支持封装基底20底部上的引脚42以及封装基底20顶部上的焊盘30的同时，尽可能地减小封装基底20。 
图7是示出了使用上述封装方案封装应用IC 10的一个实施例的流程图。虽然为了易于理解以特定顺序示出了这些方框，但是可以使用其它顺序。还可以并行执行这些方框。图7中的流程图示出了一个封装IC10的创建，并且可以重复以便产生附加的封装IC10。 
可以提供在应用IC的相邻边处具有存储器控制器PHY电路的应用IC(方框80)。例如，可以提供类似于图1所示的应用IC 10。附加地，可以提供沿着IC的一个边包括焊盘的存储器IC(方框82)。例如，可以提供类似于IC50和52的具有焊盘的存储器IC。存储器IC供应商可以将其IC设计为具有可针对所希望的引脚输出进行定制的重新分配层。可以指示存储器IC供应商定制该重新分配层，以便沿着一个边提供焊盘。可以提供包括用于叠层芯片封装的垂直导线的焊盘，并且还包括用于层叠封装的焊料球或其它封装引脚的焊盘的封装基底(方框84)。例如，可以提供类似于图2所示的封装基底20的封装基底。应用IC可以被倒装芯片安装到封装基底上(方框86)。 
如果使用叠层芯片封装将应用IC与存储器IC封装在一起(判断框88的“是”分支)，两个或更多个存储器IC(没有封装)可被正交地堆叠在应用IC上(方框90)。存储器IC可被连接到封装基底上的应用IC的侧面附近的焊盘(方框92)。如果不选择叠层芯片封装(判断框88的“否”分支)，则两个或更多个封装的存储器IC可被附加到层叠封装方案的封装基底顶部上的焊料球(方框94)。 
在积累关于叠层芯片方案的可靠性的统计量之后，该方法可以包括确定叠层芯片封装是否可靠(判断框96)。在各种实施例中，可以 基于可测量的统计量的任意阈值进行这种可靠性确定。如果确定叠层芯片封装可靠(判断框96的“是”分支)，则可以修改封装基底设计，以便去除用于层叠封装方案的焊盘，并且根据封装引脚和用于叠层芯片方案的焊盘缩小封装基底(方框98)。如果叠层芯片封装不能提供足够的可靠性(判断框96的“否”分支)，则可以使用层叠封装方案而不用对已有的封装基底进行任何修改(方框100)。 
现在转到图8，图8示出了系统110的一个实施例的方框图。在示出的实施例中，系统110包括应用IC 10的至少一个实例112和耦接到一个或多个外设114的存储器IC50和52(或是叠层芯片封装或是层叠封装)。在某些实施例中，可以包括应用IC和存储器IC的多于一个的实例。 
取决于系统110的类型，外设114可以包括任意所希望的电路。例如，在一个实施例中，系统110可以是移动设备，并且外设114可以包括用于各种类型的无线通信的设备，诸如wifi、蓝牙、蜂窝、全球定位系统等。外设114还可以包括附加的存储设备，包括RAM存储设备、固态存储设备或盘存储设备。外设114可以包括用户接口设备，诸如包括触摸显示屏或多点触摸显示屏的显示屏、键盘或其它按键、麦克风、扬声器等。 
根据一个实施例，提供了一种集成电路，包括：相应于第一接口的第一物理层接口电路，所述集成电路被配置为通过所述第一接口与所述集成电路外部通信，其中所述第一物理层接口电路包括在形成第一接口的每个导线上通信的电路，并且其中所述第一物理层接口电路沿着所述集成电路的第一边被物理定位；和相应于第二接口的第二物理层接口电路，所述集成电路被配置为通过所述第二接口与所述集成电路外部通信，其中所述第二物理层接口电路包括在形成第二接口的每个导线上通信的电路，并且其中所述第二物理层接口电路沿着所述集成电路的第二边被物理定位，其中第二边与第一边相邻。 
在所述集成电路中，第一接口和第二接口是相同接口的实例。其中所述相同接口是连接到一个或多个存储器集成电路的存储器接口， 并且其中所述集成电路包括耦接到第一物理层接口电路的第一存储器控制器以及耦接到第二物理层接口电路的第二存储器控制器。 
所述集成电路还包括：布置在第一物理层接口电路之上的第一多个可控塌陷芯片连接凸点，以及布置在第二物理层接口电路之上的第二多个可控塌陷芯片连接凸点，其中所述第一多个可控塌陷芯片连接凸点和所述第二多个可控塌陷芯片连接凸点为第一接口和第二接口提供到所述集成电路的封装的倒装芯片连接。其中所述第一多个可控塌陷芯片连接凸点布置在一个或多个第一行内，并且其中所述第二多个可控塌陷芯片连接凸点布置在与所述一个或多个第一行正交的一个或多个第二行内。 
根据一个实施例，提供了一种用于集成电路的封装器件，该封装器件包括：封装基底，所述封装基底包括第一多个导线和形成所述封装基底的第一表面的绝缘层，其中所述第一多个导线中的每一个包括第一端点，其中所述第一端点被布置为当所述集成电路被安装到所述封装基底上时，以倒装芯片配置连接到所述集成电路，并且其中所述绝缘层包括用于每个第一端点的开口；和其中所述第一多个导线中的每一个延伸到所述封装基底的第一表面上的各自相应的第一焊盘，形成各自相应的第一焊盘与封装引脚的连接；和其中所述第一多个导线中的每一个包括当所述集成电路被安装在所述封装基底上时邻近所述集成电路的第一侧的各自相应的第二焊盘，并且其中所述绝缘层包括用于每个各自相应的第二焊盘的开口。 
在所述封装器件中，所述封装基底还包括第二多个导线，其中所述第二多个导线中的每一个包括布置为当所述集成电路被安装到所述封装基底上时，以倒装芯片配置连接到所述集成电路的第一端点，并且其中所述绝缘层包括用于每个第一端点的开口；和其中所述第二多个导线中的每一个延伸到所述封装基底的第一表面上的各自相应的第一焊盘，形成各自相应的第一焊盘与封装引脚的连接；和其中所述第二多个导线中的每一个包括当所述集成电路被安装在所述封装基底上时邻近所述集成电路的第二侧的各自相应的第三焊盘，并且其中第二 边与第一边正交，并且其中所述绝缘层包括用于每个各自相应的第三焊盘的开口。 
所述封装器件还包括：附接到各自相应的第一焊盘上的封装引脚，其中所述封装引脚在层叠封装配置中总体地提供用于一个或多个经封装的集成电路的安装点。其中所述封装引脚是焊料球。所述封装器件还包括：附接到所述封装基底的与第一侧相对的第二侧的第二组封装引脚，其中所述第二组封装引脚提供到电路板的连接。 
根据一个实施例，还提供了一种用于封装多个集成电路的组件，包括：如上所述的封装器件；倒装芯片安装到所述封装基底上的第一集成电路，其中所述封装基底包括邻近第一集成电路的第一侧的第一多个焊盘，以及邻近第一集成电路的第二侧的第二多个焊盘；第二集成电路，沿着第二集成电路的一个边具有第三多个焊盘，所述第二集成电路堆叠在所述第一集成电路上，所述第三多个焊盘和所述第一多个焊盘对齐；第三集成电路，沿着第三集成电路的一个边具有第四多个焊盘，所述第三集成电路以与第二集成电路正交的取向堆叠在所述第二集成电路上，并且所述第四多个焊盘和所述第二多个焊盘对齐；和多个导线，将所述第一多个焊盘中的每一个连接到所述第三多个焊盘中的相应一个，并且将所述第二多个焊盘中的每一个连接到所述第四多个焊盘中的相应一个。 
其中所述第二集成电路和所述第三集成电路以非倒装芯片取向安装。 
其中所述第二集成电路和所述第三集成电路是相同集成电路的实例。 
其中所述第三集成电路相对于所述第二集成电路偏离，以便暴露所述第二多个焊盘。 
其中所述第二集成电路和所述第三集成电路是存储器集成电路。 
其中所述第一多个焊盘连接到相应于所述第一集成电路中的第一存储器控制器的第一存储器接口，并且其中所述第二多个焊盘连接到相应于所述集成电路中的第二存储器控制器的第二存储器接口。 
其中所述第一多个焊盘和所述第二多个焊盘还连接到第五多个焊盘中的相应的一个，所述第五多个焊盘被连接到多个封装引脚。 
其中所述多个封装引脚中的每一个是焊料球。 
根据一个实施例，还提供了一种用于封装多个集成电路的方法，包括：提供用于集成电路的封装器件，所述封装器件包括封装基底，所述封装基底包括连接到所述集成电路的第一多个导线和第二多个导线，所述第一多个导线中的每一个包括邻近所述集成电路的第一侧的第一焊盘，并且所述第二多个导线中的每一个包括邻近所述集成电路的第二侧的第二焊盘，其中第二侧与第一侧相邻，并且其中所述第一多个导线和所述第二多个导线中的每一个延伸到第二多个焊盘，封装引脚连接到所述第二多个焊盘；为两个或更多个集成电路中的第一集成电路使用第一导线上的第一焊盘，并且为所述集成电路中的第二集成电路使用第二导线上的第二焊盘，使用叠层芯片封装连接所述两个或更多个集成电路，其中所述第一集成电路被定向为与所述第二集成电路正交；确定所述叠层芯片封装是可靠的；和通过消除所述第二多个焊盘和所述第一多个导线和第二多个导线到所述第二多个焊盘的延伸，为后续集成电路减小封装基底。 
所述方法还包括：提供所述封装的第二实例；和以层叠封装配置将两个或更多个经封装的集成电路连接到所述封装引脚。 
一旦完全理解了上述公开，本领域的技术人员将明了各种变形和修改。下面的权利要求旨在被解释为包含所有这些变形和修改。 

Claims (13)

1.一种用于集成电路的封装器件，该封装器件包括：
封装基底，所述封装基底包括第一多个导线和形成所述封装基底的第一表面的绝缘层，其中所述第一多个导线中的每一个包括第一端点，其中所述第一端点被布置为当所述集成电路被安装到所述封装基底上时，以倒装芯片配置连接到所述集成电路，并且其中所述绝缘层包括用于每个第一端点的开口；
其中所述第一多个导线中的每一个延伸到所述封装基底的第一表面上的相应的第一焊盘，形成相应的第一焊盘与封装引脚的连接；和
其中所述第一多个导线中的每一个包括当所述集成电路被安装在所述封装基底上时邻近所述集成电路的第一边的相应的第二焊盘，并且其中所述绝缘层包括用于每个相应的第二焊盘的开口；
在所述第一表面上的第一组封装引脚，其中所述第一组封装引脚中的每一个封装引脚与一个第一焊盘连接，并且其中所述第一组封装引脚在层叠封装配置中总体地提供用于一个或多个经封装的集成电路的安装点；
附接到所述封装基底的与所述第一表面相对的第二表面的第二组封装引脚，其中所述第二组封装引脚提供到电路板的连接；以及
在所述第一表面上的第二组端点，所述第二组端点中的每一个端点通过所述封装基底连接至所述第二组封装引脚的一个相应的引脚，并且所述第二组端点被布置为与第一端点分离地连接至所述集成电路。
2.如权利要求1所述的封装器件，其中：
所述封装基底还包括第二多个导线，其中所述第二多个导线中的每一个包括布置为当所述集成电路被安装到所述封装基底上时，以倒装芯片配置连接到所述集成电路的第一端点，并且其中所述绝缘层包括用于每个第一端点的开口；和
其中所述第二多个导线中的每一个延伸到所述封装基底的第一表面上的相应的第一焊盘，形成相应的第一焊盘与封装引脚的连接；和
其中所述第二多个导线中的每一个包括当所述集成电路被安装在所述封装基底上时邻近所述集成电路的第二边的相应的第二焊盘，并且其中第二边与第一边正交，并且其中所述绝缘层包括用于每个相应的第二焊盘的开口。
3.如权利要求1所述的封装器件，其中所述封装引脚是焊料球。
4.一种组件，包括：
如权利要求2所述的封装器件；
倒装芯片安装到所述封装基底上的集成电路；
第二集成电路，沿着第二集成电路的一个边具有第三多个焊盘，所述第二集成电路堆叠在所述第一集成电路上，所述第三多个焊盘沿着所述第一边和相应的第二焊盘对齐；
第三集成电路，沿着第三集成电路的一个边具有第四多个焊盘，所述第三集成电路以与第二集成电路正交的取向堆叠在所述第二集成电路上，并且所述第四多个焊盘沿着所述第二边和相应的第二焊盘对齐；和
多个导线，将所述相应的第二焊盘中的每一个沿着所述第一边连接到所述第三多个焊盘中的相应一个，并且将所述相应的第二焊盘中的每一个沿着所述第二边连接到所述第四多个焊盘中的相应一个。
5.如权利要求4所述的组件，其中所述第二集成电路和所述第三集成电路以非倒装芯片取向安装。
6.如权利要求4所述的组件，其中所述第二集成电路和所述第三集成电路是相同集成电路的实例。
7.如权利要求6所述的组件，其中所述第三集成电路相对于所述第二集成电路偏离，以便暴露所述第三多个焊盘。
8.如权利要求6所述的组件，其中所述第二集成电路和所述第三集成电路是存储器集成电路。
9.如权利要求8所述的组件，其中所述第一多个焊盘连接到相应于所述第一集成电路中的第一存储器控制器的第一存储器接口，并且其中所述第二多个焊盘连接到相应于所述集成电路中的第二存储器控制器的第二存储器接口。
10.如权利要求4所述的组件，其中所述第一多个焊盘和所述第二多个焊盘还连接到第五多个焊盘中的相应的一个，所述第五多个焊盘被连接到多个封装引脚。
11.如权利要求10所述的组件，其中所述多个封装引脚中的每一个是焊料球。
12.一种方法，包括：
提供用于集成电路的封装器件，所述封装器件包括封装基底，所述封装基底包括连接到所述集成电路的第一多个导线和第二多个导线，所述第一多个导线中的每一个包括邻近所述集成电路的第一侧的第一焊盘，并且所述第二多个导线中的每一个包括邻近所述集成电路的第二侧的第二焊盘，其中第二侧与第一侧相邻，并且其中所述第一多个导线和所述第二多个导线中的每一个延伸到第二多个焊盘，封装引脚连接到所述第二多个焊盘；
使用叠层芯片封装连接所述两个或更多个集成电路，其中为所述两个或更多个集成电路中的第一集成电路使用第一导线上的第一焊盘，并且为所述两个或更多个集成电路中的第二集成电路使用第二导线上的第二焊盘，其中所述第一集成电路被定向为与所述第二集成电路正交；
确定所述叠层芯片封装是可靠的；和
通过消除所述第二多个焊盘和所述第一多个导线和第二多个导线到所述第二多个焊盘的延伸，为后续集成电路减小封装基底。
13.如权利要求12所述的方法，还包括：
提供所述封装的第二实例；和
以层叠封装配置将两个或更多个经封装的集成电路连接到所述封装引脚。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105074918A (zh) * 2013-03-13 2015-11-18 苹果公司 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101142338B1 (ko) * 2010-06-17 2012-05-17 에스케이하이닉스 주식회사 반도체 칩 및 그의 제조방법 및 이를 이용한 스택 패키지
US8587088B2 (en) 2011-02-17 2013-11-19 Apple Inc. Side-mounted controller and methods for making the same
WO2013023153A1 (en) * 2011-08-10 2013-02-14 Marvell World Trade Ltd. Intelligent phy with security detection for ethernet networks
US8826447B2 (en) * 2011-10-10 2014-09-02 Marvell World Trade Ltd. Intelligent connectors integrating magnetic modular jacks and intelligent physical layer devices
US8868820B2 (en) * 2011-10-31 2014-10-21 Microsemi SoC Corporation RAM block designed for efficient ganging
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
US8806407B2 (en) 2012-12-31 2014-08-12 Synopsys, Inc. Multiple-instantiated-module (MIM) aware pin assignment
KR102110984B1 (ko) 2013-03-04 2020-05-14 삼성전자주식회사 적층형 반도체 패키지
US9674957B2 (en) 2014-02-04 2017-06-06 Samsung Display Co., Ltd. Display device and method of manufacturing the same
US9646952B2 (en) * 2015-09-17 2017-05-09 Intel Corporation Microelectronic package debug access ports
US20170083461A1 (en) * 2015-09-22 2017-03-23 Qualcomm Incorporated Integrated circuit with low latency and high density routing between a memory controller digital core and i/os
KR102392083B1 (ko) 2016-06-27 2022-04-29 애플 인크. 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템
US10164358B2 (en) * 2016-09-30 2018-12-25 Western Digital Technologies, Inc. Electrical feed-through and connector configuration
US20200006306A1 (en) * 2018-07-02 2020-01-02 Shanghai Denglin Technologies Co. Ltd Configurable random-access memory (ram) array including through-silicon via (tsv) bypassing physical layer
JP7226358B2 (ja) * 2020-02-05 2023-02-21 株式会社デンソー 電子機器
US11742253B2 (en) * 2020-05-08 2023-08-29 Qualcomm Incorporated Selective mold placement on integrated circuit (IC) packages and methods of fabricating
CN112261781A (zh) * 2020-10-20 2021-01-22 Oppo广东移动通信有限公司 一种封装模组及终端
US11791326B2 (en) 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196526A (ja) * 2000-01-06 2001-07-19 Seiko Epson Corp マルチベアチップ実装体、マルチチップパッケージ、半導体装置、ならびに電子機器
US20070096291A1 (en) * 2005-10-27 2007-05-03 Takeshi Kawabata Stacked semiconductor device and lower module of stacked semiconductor device
US20070262436A1 (en) * 2006-05-12 2007-11-15 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
CN101083243A (zh) * 2006-05-12 2007-12-05 美国博通公司 集成电路封装及其制造方法
US20080157393A1 (en) * 2006-12-27 2008-07-03 Chikaaki Kodama Semiconductor device

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG46176A1 (en) 1989-09-15 1998-02-20 Ibm Design system for vlsi chips arranged on a carrier and module thus designed
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US6486528B1 (en) * 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
US5583749A (en) 1994-11-30 1996-12-10 Altera Corporation Baseboard and daughtercard apparatus for reconfigurable computing systems
US5696031A (en) * 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
TW449844B (en) * 1997-05-17 2001-08-11 Hyundai Electronics Ind Ball grid array package having an integrated circuit chip
SG75873A1 (en) * 1998-09-01 2000-10-24 Texas Instr Singapore Pte Ltd Stacked flip-chip integrated circuit assemblage
US6586266B1 (en) * 1999-03-01 2003-07-01 Megic Corporation High performance sub-system design and assembly
US6140710A (en) 1999-05-05 2000-10-31 Lucent Technologies Inc. Power and ground and signal layout for higher density integrated circuit connections with flip-chip bonding
JP2000315776A (ja) 1999-05-06 2000-11-14 Hitachi Ltd 半導体装置
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
KR100831235B1 (ko) * 2002-06-07 2008-05-22 삼성전자주식회사 박막 트랜지스터 기판
US8837161B2 (en) 2002-07-16 2014-09-16 Nvidia Corporation Multi-configuration processor-memory substrate device
US6858945B2 (en) * 2002-08-21 2005-02-22 Broadcom Corporation Multi-concentric pad arrangements for integrated circuit pads
JP4105524B2 (ja) * 2002-10-23 2008-06-25 株式会社東芝 半導体装置
JP4264640B2 (ja) 2003-08-19 2009-05-20 ソニー株式会社 半導体装置の製造方法
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US7205178B2 (en) * 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
US7215018B2 (en) * 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7245021B2 (en) * 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US7459772B2 (en) * 2004-09-29 2008-12-02 Actel Corporation Face-to-face bonded I/O circuit die and functional logic circuit die system
DE102004057239A1 (de) * 2004-11-26 2006-06-01 Austriamicrosystems Ag Vorrichtung und Verfahren zum Laden und zur Ladungskontrolle eines Akkumulators
CN1828890A (zh) * 2005-03-03 2006-09-06 因芬尼昂技术股份公司 具有重新路由层集成电路及堆叠管芯组
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
KR20080067328A (ko) 2005-09-06 2008-07-18 비욘드 블라데스 리미티드 3ｄｍｃ 아키텍처
US20080284716A1 (en) * 2005-12-13 2008-11-20 Koninklijke Philips Electronics, N.V. Display Devices With Ambient Light Sensing
JP2007250935A (ja) * 2006-03-17 2007-09-27 Renesas Technology Corp 半導体装置と半導体装置の製造方法
JP5259059B2 (ja) * 2006-07-04 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
KR100800161B1 (ko) * 2006-09-30 2008-02-01 주식회사 하이닉스반도체 관통 실리콘 비아 형성방법
KR100780966B1 (ko) * 2006-12-07 2007-12-03 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR100851072B1 (ko) 2007-03-02 2008-08-12 삼성전기주식회사 전자 패키지 및 그 제조방법
WO2008115744A1 (en) * 2007-03-16 2008-09-25 Vertical Circuits, Inc. Vertical electrical interconnect formed on support prior to die mount
JP2008299997A (ja) * 2007-06-01 2008-12-11 Toshiba Corp 半導体記憶装置
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US20080303154A1 (en) * 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
US7923349B2 (en) * 2007-06-19 2011-04-12 Vertical Circuits, Inc. Wafer level surface passivation of stackable integrated circuit chips
KR100871381B1 (ko) * 2007-06-20 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 칩 스택 패키지
US20080315407A1 (en) * 2007-06-20 2008-12-25 Vertical Circuits, Inc. Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196526A (ja) * 2000-01-06 2001-07-19 Seiko Epson Corp マルチベアチップ実装体、マルチチップパッケージ、半導体装置、ならびに電子機器
US20070096291A1 (en) * 2005-10-27 2007-05-03 Takeshi Kawabata Stacked semiconductor device and lower module of stacked semiconductor device
US20070262436A1 (en) * 2006-05-12 2007-11-15 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
CN101083243A (zh) * 2006-05-12 2007-12-05 美国博通公司 集成电路封装及其制造方法
US20080157393A1 (en) * 2006-12-27 2008-07-03 Chikaaki Kodama Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105074918A (zh) * 2013-03-13 2015-11-18 苹果公司 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计
CN105074918B (zh) * 2013-03-13 2017-12-26 苹果公司 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计

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US8097956B2 (en) 2012-01-17
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WO2010104703A1 (en) 2010-09-16

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