CN102540701A - Self alignment type secondary imaging method - Google Patents
Self alignment type secondary imaging method Download PDFInfo
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- CN102540701A CN102540701A CN2010106117491A CN201010611749A CN102540701A CN 102540701 A CN102540701 A CN 102540701A CN 2010106117491 A CN2010106117491 A CN 2010106117491A CN 201010611749 A CN201010611749 A CN 201010611749A CN 102540701 A CN102540701 A CN 102540701A
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Abstract
The invention discloses an improved self alignment type secondary imaging method. The method comprises the following steps of: forming first photoresist on an image transfer layer on a substrate; performing a first exposure process to form a first graph on the first photoresist; transferring the formed first graph to the image transfer layer through etching to remove the first photoresist from a surface; forming side walls on two sides of the first graph of the image transfer layer; removing the image transfer layer and remaining a second graph formed by the side walls on the surface of the substrate; forming the other photoresist again on the second graph, performing the other exposure process to expose the side wall part which is not required; and etching to remove the side wall part which is not required and removing the other photoresist. Therefore, the defect that the side walls formed by the self alignment type secondary imaging technology must be symmetrical to each other is improved, and any number of required lines are obtained, so the difficulty in layout design is reduced.
Description
Technical field
The present invention relates to the photolithographic fabrication field of SIC (semiconductor integrated circuit), more specifically, relate to repeatedly imaging and photo-etching method of a kind of autoregistration formula.
Background technology
Photoetching is important step during integrated circuit is made, and also is to promote the main drive that the integrated circuit size reduces.But when the live width size is reduced to 32nm and when following, existing lithographic equipment all can not reach needed resolution, therefore in order to reach the 32nm processing procedure, people have adopted the secondary imaging technology.Autoregistration formula secondary imaging technology (SADP Double Pattern) is one of secondary imaging technology of present main flow, and it is lower than other secondary imaging technology to the requirement of machine alignment precision, therefore receives pursuing of people.But should certain defective also be arranged technology; Because the side wall of growth all is symmetrical in the figure both sides; For layout design has been made many difficulties, thereby for example must consider when layout design that there are redundant lines in this symmetrical structure at the fringe region of figure, thereby waste useful area.
Referring to figs. 1 to Fig. 6,, be mainly used in the resolution that improves existing lithographic equipment and reach 32nm and thinner lines for existing autoregistration formula secondary imaging technology.Fig. 1 to Fig. 4 be through conventional lithography process with the figure transfer on the photoresist to the figure transfer layer.Particularly, at first as shown in Figure 1, semiconductor wafer comprises silicon substrate 1, on substrate 1, is formed with one deck figure transfer layer 2, and its composition can be materials such as monox or agraphitic carbon, and on figure transfer layer 2, forms photo-induced etching agent 3 (also being called photoresist).Secondly, as shown in Figure 2, exposure is also developed, the identical D1 of being of spacing between the photoresist 3 lines part that wherein stays with mask plate, and himself width is D2.Then, as shown in Figure 3, etching is up to exposing substrate 1.Then, as shown in Figure 4, remove photoresist 3, on substrate 1, stay and have figure transfer layer 2 part consistent with mask graph, the spacing between figure transfer layer 2 lines that the obtain part also is D1.Fig. 5 is through the method that for example chemical vapor phase epitaxy (CVD) or rotation the apply side wall 4 of growing on the both sides of figure transfer layer 2 part consistent with mask graph.Fig. 6 is the structure that etches away behind the figure transfer layer 2; Spacing between the final bargraphs that obtains is lines self width D 2 that figure transfer layer 2 stays part; The lines space D 1 that stays part than figure transfer layer 2 is little, can see through traditional autoregistration formula secondary imaging technology obtaining equally spaced hachure structure.But, figure forms because all being the side wall that is symmetrical distribution by former lines both sides; The structure of therefore this technology preparation all is the even numbers lines, in some lines is the graphic structure of linear and some non-parallel lines of odd number, also makes the even numbers lines, has wasted chip area; Make the enlarged areas that integral layout wiring is required; Be difficult to improve integrated level, thereby improved the difficulty of layout design, also improved the IC manufacturing cost indirectly.
In view of this, need a kind of easy autoregistration formula photoetching method, can access asymmetrical sidewall structure; Thereby can obtain the particularly lines of odd number of arbitrary number; Redundant lines when having eliminated placement-and-routing have reduced chip area, greatly reduce the difficulty of layout design.
Summary of the invention
The objective of the invention is to reduce the layout design difficulty of self aligned photoresist process.
For this reason, the invention provides a kind of method, be used to improve autoregistration formula secondary imaging technology, comprising: on the image transfer layer on the substrate, form first photoresist; Carry out first exposure technology, in order on said first photoresist, to form first figure; Through over etching first figure transfer that forms to said image transfer layer, and remove said first photoresist on surface; The said first figure both sides at said image transfer layer form side wall; Remove said figure transfer layer, stay the second graph that said side wall constitutes at said substrate surface; On said second graph, form another photoresist again, carry out another exposure technology, expose unwanted side wall part; Be etched away said unwanted side wall part and remove said another photoresist.
Wherein, said substrate is body silicon, SOI, SiC, sapphire or SiGe and combination thereof.Said image transfer layer is monox or agraphitic carbon.Said first photoresist bottom or top also comprise ARC.The lines spacing of said second graph is less than the lines spacing of said first figure.
Wherein, the step that forms said side wall comprises: through the method for the chemical vapor phase epitaxy said side wall of growing in the both sides of first figure.
Pass through to introduce photoetching for the second time according to photoetching method of the present invention; Protect needed side wall to get rid of the method for unwanted use etching with photoresist; Mainly being used for improving the technological side wall that forms of autoregistration formula secondary imaging must be this shortcoming of symmetry, thereby can obtain the particularly lines of odd number of arbitrary number, can access asymmetrical sidewall structure; Need not in some lines is the graphic structure of linear and some non-parallel lines of odd number, also to make the even numbers lines; Redundant lines when having eliminated placement-and-routing have reduced chip area, greatly reduce the difficulty of layout design.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Fig. 1 is the wafer initial configuration sectional view of prior art;
Fig. 2 is the sectional view of figure on the photoresist after the photoetching of prior art;
Fig. 3 be prior art pass through etching with the sectional view of figure transfer on the photoresist to the figure transfer layer of lower floor;
Fig. 4 is the figure sectional view behind the photoresist of getting rid of of prior art;
Fig. 5 is the sectional view behind the method growth side wall of employing chemical vapor phase epitaxy of prior art;
Fig. 6 is the sectional view after prior art the figure transfer layer is thoroughly removed;
Fig. 7 is for accordinging to the sectional view that unwanted side wall is come out of the present invention;
Fig. 8 is for removing the sectional view behind the unwanted side wall according to of the present invention through etching; And
Fig. 9 is according to the final graphics behind the removal photoresist of the present invention.
The symbol description of figure
1 substrate, 2 figure transfer layers
The side wall of 3 first photoresist 4CVD growth
5 second photoresists
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score, " thick ", " approaching " or the like can be used for modifying various device architectures.These are modified is not space, order or the hierarchical relationship of hint institute modification device architecture unless stated otherwise.
At first as shown in Figure 1, semiconductor wafer is provided, have substrate 1, can be silicon on body silicon or the dielectric substrate (SOI), also can be SiC, sapphire, SiGe etc.On substrate 1, be formed with figure transfer layer 2, its composition can be materials such as monox or agraphitic carbon.Rotation applies first photo-induced etching agent 3 (also being called first photoresist 3) and toasts at a certain temperature to solidify photoresist and improve tack on figure transfer layer 2, and especially, the photoresist 3 that shows among Fig. 1 is positive glue.In addition; Also can be on figure transfer layer 2 first PVD depositing TiN or nitrogen silicide be used as bottom ARC (BARC; Not shown) and then apply first photoresist 3, or after applying first photoresist 3, spray reflection coating provided (TAR, not shown) at its top; Can reduce standing wave effect like this, avoid live width to increase.
Secondly, as shown in Figure 2, use first mask plate that photoresist 3 is made public; By the part generation hydrolysis of the photoresist 3 of the positive glue type of first mask covering, do not re-use alkaline solution and develop, the part that is covered by first mask remains; Pyroprocessing can be as the mask of subsequent etching so that post bake makes photoresist 3 parts that stay constitute first figure subsequently; The identical D1 of being with mask plate of spacing between first pattern line that wherein the stays part, himself width is D2.
Once more, as shown in Figure 3, etching is up to exposing substrate 1.Can use the figure transfer layer 2 of the etching liquid wet etching monox that is generally hydrofluorite for large-size device, then use carbon fluorine-based plasma dry etching figure transfer layer 2 so that improve etching precision for small size device.
Then; As shown in Figure 4; Use acetone and aromatic organic solvent or use the inorganic solvent of sulfuric acid and oxydol to remove photoresist 3; On substrate 1, stay and have figure transfer layer 2 part consistent with first mask graph, the spacing between figure transfer layer 2 lines that the obtain part also is D1.
Then, as shown in Figure 5, the method that applies through for example chemical vapor phase epitaxy (CVD) or the rotation side wall 4 of growing on the both sides of figure transfer layer 2 part consistent with mask graph.Can be earlier on total, preferably have with figure transfer layer 2 and select than big material through the CVD deposition; Nitride for example; Be in particular silicon nitride or silicon oxynitride; Carry out etching then and form the sidewall structure 4 of figure transfer layer 2 both sides, also promptly adopt hot phosphoric acid to carry out wet etching or adopt the fluorine-based plasma gas dry etching of carbon to remove bottom and the nitride material at top between figure transfer layer 2 bargraphs, stay remaining sidewall structure in figure transfer layer 2 bargraphs side.Also can adopt spin coated on figure transfer layer 2, to form spin-coating glass (SOG), after hot reflux makes it smooth again etching form side wall.Spacer material can also be a metal, is used to form wiring or weld pad.Preferably, adopt dry etching to form the side wall of various materials,, avoid wet etching to make the fineness of bargraphs reduce for the lateral corrasion of side wall to guarantee the vertical property of bargraphs.Particularly, the width of sidewall structure is D3.
Subsequently, as shown in Figure 6, for etching away the structure behind the figure transfer layer 2, the figure transfer layer 2 that adopts the hydrofluorite wet method to remove monox stays not the nitride with the hydrofluorite reaction, perhaps uses the fluorine-based particularly CHF of carbon
3Plasma etching gas come dry etching to remove figure transfer layer 2, obtain second graph, the spacing between the lines of second graph be figure transfer layer 2 stay the part lines self width D 2.Can know by Fig. 6; Because second graph is formed in the first figure both sides; Therefore the lines number that comprises of second graph must be an even number, will fully take into account symmetry when this just requires layout design, must reserve enough redundant and can't be used by follow-up placement-and-routing between the lines; Cause chip area to be difficult to reduce significantly, improved the layout design difficulty.
The present invention mainly is in order to improve this drawback of autoregistration formula secondary imaging technology, to have introduced the second step photoetching.As shown in Figure 7, after sidewall structure 4 forms, on the entire wafer surface, apply one deck second photoresist 5 again, then through with conventional lithographic techniques like aforesaid first lithography type, unwanted side wall part 4 ' is come out.Particularly, just be to use second mask plate, its figure be only expose unwanted side wall part 4 ' and all the other overwhelming majority for the masked part.Said unwanted side wall part 4 ' refers to those to be needed to stay the part into blank according to placement-and-routing in layout design; Space between the interval region between the metal connecting line, the IC module or the like for example; Left white space after these unwanted side wall parts 4 ' are removed; Can be used as the space of follow-up cabling, also can give over to insulation and isolate used.The unwanted side wall part 4 ' that shows among the figure is the wall scroll bargraphs that is positioned at wafer or domain edge, yet alternatively, unwanted side wall part 4 ' also can be positioned at wafer or domain center, can also be the combination of many bargraphss arbitrarily.
Then; As shown in Figure 8; Method through etching is removed unwanted side wall part 4 ', particularly, and for the side wall part 4 ' of nitride formation; Can adopt hot phosphoric acid to come wet etching to remove, also can adopt the fluorine-based plasma etching gas of carbon to come dry etching to remove the side wall that other materials constitutes.
The inorganic solvent that uses acetone and aromatic organic solvent at last or use sulfuric acid and oxydol constitutes the 3rd figure with the side wall part 4 of second photoresist, 5 removals with regard to finally having obtained staying, and is as shown in Figure 9.Can remove through the initiate second step photoetching and not hope the side wall that occurs, count lines thereby obtain any bar that we want, and can access asymmetrical sidewall structure.Can confirm beyond all doubtly directly that by accompanying drawing 4-6 the width D 3 of the 3rd figure and/or second graph is less than the width D 2 of first figure.
Thus; Through introducing photoetching for the second time, protect needed side wall to get rid of the method for unwanted use etching according to photoetching method of the present invention with photoresist, mainly be used for improving the technological side wall that forms of autoregistration formula secondary imaging this shortcoming that must be symmetry; Thereby can obtain the particularly lines of odd number of arbitrary number; Can access asymmetrical sidewall structure, need not in some lines is the graphic structure of linear and some non-parallel lines of odd number, also to make the even numbers lines, the redundant lines when having eliminated placement-and-routing; Reduce chip area, greatly reduced the difficulty of layout design.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and the method that forms device architecture is made various suitable changes and equivalents.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (10)
1. a method is used to improve autoregistration formula secondary imaging method, comprising:
On the image transfer layer on the substrate, form first photoresist;
Carry out first exposure technology, in order on said first photoresist, to form first figure;
Through over etching first figure transfer that forms to said image transfer layer, and remove said first photoresist on surface;
The said first figure both sides at said image transfer layer form side wall;
Remove said figure transfer layer, stay the second graph that said side wall constitutes at said substrate surface;
On said second graph, form second photoresist again, carry out second exposure technology, expose unwanted side wall part;
Be etched away said unwanted side wall part and remove said second photoresist, stay the 3rd figure.
2. the method for claim 1, wherein said substrate is body silicon, SOI, SiC, sapphire or SiGe and combination thereof.
3. the method for claim 1, wherein said image transfer layer is monox or agraphitic carbon.
4. the method for claim 1, wherein said first photoresist bottom or top also comprise ARC.
The method of claim 1, wherein the lines spacing of said second graph less than the lines spacing of said first figure.
6. the step that the method for claim 1, wherein forms said side wall comprises:
The method that applies through chemical gaseous phase extension or rotation forms the material that constitutes said side wall in the both sides of first figure.
7. method as claimed in claim 6, wherein, form after the said spacer material through dry etching remove the first figure top and between the bottom spacer material and on first pattern side wall, stay said side wall.
8. the method for claim 1, wherein said second graph is even number bar lines, and said the 3rd figure is odd number bar lines.
9. the method for claim 1, wherein said unwanted side wall partly is to need to stay the bargraphs into blank according to the laying out pattern wiring, is positioned at domain edge or center.
The method of claim 1, wherein the said the 3rd and/or the width of second graph less than the width of said first figure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010611749.1A CN102540701B (en) | 2010-12-28 | 2010-12-28 | Self alignment type secondary imaging method |
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| CN201010611749.1A CN102540701B (en) | 2010-12-28 | 2010-12-28 | Self alignment type secondary imaging method |
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| CN102540701B CN102540701B (en) | 2014-04-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996602A (en) * | 2014-06-09 | 2014-08-20 | 上海华力微电子有限公司 | Method for forming ultra-small pattern with double-side-wall technology |
| CN104462635A (en) * | 2013-09-24 | 2015-03-25 | 格罗方德半导体公司 | Methods of generating circuit layouts that are to be manufactured using SADP techniques |
| CN109427555A (en) * | 2017-09-05 | 2019-03-05 | 南亚科技股份有限公司 | The close sectional hole patterns forming method of semiconductor element |
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| JP2009004535A (en) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | Pattern forming method |
| US20090246706A1 (en) * | 2008-04-01 | 2009-10-01 | Applied Materials, Inc. | Patterning resolution enhancement combining interference lithography and self-aligned double patterning techniques |
| CN101923285A (en) * | 2009-06-09 | 2010-12-22 | Asml荷兰有限公司 | Lithographic method and arrangement |
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| US5200355A (en) * | 1990-12-10 | 1993-04-06 | Samsung Electronics Co., Ltd. | Method for manufacturing a mask read only memory device |
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| JP2009004535A (en) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | Pattern forming method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104462635A (en) * | 2013-09-24 | 2015-03-25 | 格罗方德半导体公司 | Methods of generating circuit layouts that are to be manufactured using SADP techniques |
| CN104462635B (en) * | 2013-09-24 | 2017-03-29 | 格罗方德半导体公司 | The method that circuit layout is manufactured using SADP technologies |
| CN103996602A (en) * | 2014-06-09 | 2014-08-20 | 上海华力微电子有限公司 | Method for forming ultra-small pattern with double-side-wall technology |
| CN103996602B (en) * | 2014-06-09 | 2016-08-31 | 上海华力微电子有限公司 | A kind of method using bilateral wall technique to form ultralow size figure |
| CN109427555A (en) * | 2017-09-05 | 2019-03-05 | 南亚科技股份有限公司 | The close sectional hole patterns forming method of semiconductor element |
| CN109427555B (en) * | 2017-09-05 | 2021-07-13 | 南亚科技股份有限公司 | Method for forming dense hole pattern of semiconductor element |
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Effective date of registration: 20201214 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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Effective date of registration: 20220424 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |