CN102543205B - Semiconductor storage unit and test circuit and test operation method thereof - Google Patents

Abstract

The invention discloses semiconductor storage unit and test circuit thereof and test operation method.A kind of semiconductor storage unit includes: multiple memory banks, the plurality of memory bank each includes multiple first memory unit and multiple second memory unit；First I/O unit, is configured to transmit the first data between described first memory unit and multiple first data pads；Second I/O unit, is configured to transmit the second data between described second memory unit and multiple second data pads；Path selection unit, is configured to during test pattern, transmits described first data via described first data pads input to described first memory unit and described second memory unit；And test pattern control unit, it is configured to during described test pattern, first data of the first data of described first memory unit with described second memory unit are compared, controls at least one in described first data pads to represent malfunction based on comparative result.

Description

Semiconductor storage unit and test circuit and test operation method thereof

Technical field

The exemplary embodiment of the present invention relates to a kind of semiconductor storage unit, deposits more particularly to a kind of quasiconductor Memory device and test circuit and test operation method thereof.

Background technology

The dynamic random access memory (DRAM) being widely used in memory device includes for storing the multiple of data Memory cell.Along with the number of integrated memory cell in the semiconductor device increases, in testing semiconductor memory devices Memory cell to take more time and money.Therefore, develop and have employed concurrent testing scheme to test wafer scale Or the memory cell in the semiconductor storage unit of package level.

According to concurrent testing scheme, test data be input in the memory bank of semiconductor storage unit is two or more In memory cell.Memory cell stores and outputs test data.The relatively test data of output, to determine memory cell Whether there is defect.

Existing semiconductor storage unit includes the additional testing pin on chip, i.e. tests knot exporting comparative result Really.In order to reduce chip size, need one can test semiconductor memory in the case of not having additional testing pin Part and the circuit of testing time can be reduced.

Summary of the invention

The exemplary embodiment of the present invention relates to the quasiconductor of a kind of testing time that can reduce multiple unit cell and deposits Memory device.

According to one exemplary embodiment of the present invention, a kind of semiconductor storage unit includes: multiple memory banks, described many Individual memory bank each includes multiple first memory unit and multiple second memory unit；First I/O unit, institute State the first I/O unit to be configured between described first memory unit and multiple first data pads transmit first Data；Second I/O unit, described second I/O unit is configured at described second memory unit with many The second data are transmitted between individual second data pads；Path selection unit, described path selection unit is configured at test mould During formula, transmit described first data via described first data pads input to described first memory unit and described the Two memory cells；And test pattern control unit, described test pattern control unit is configured at described test pattern Period, the first data of the first data of described first memory unit with described second memory unit are compared, with And control at least one in described first data pads to represent malfunction based on comparative result, and wherein, described test One in described first data pads is controlled as adhesion state after read operation completes by mode controlling unit.

According to another exemplary embodiment of the present invention, a kind of method of testing semiconductor memory devices includes following step Rapid: the data inputted via data pads are sent to first memory unit and the second memory unit of memory bank；By institute The data of the data and described second memory unit of stating first memory unit compare with based on comparative result output event Barrier detection signal；Touched in response to the test mode signal being activated during described test pattern with when reading order inputs The gating signal sent out, produces fault latch signal by being latched by described fault detection signal；Believe based on described fault latch Number and described test mode signal produce fault-signal；And based on described fault-signal, drive in described data pads At least one is to represent fault adhesion state.

Accompanying drawing explanation

Fig. 1 is the block diagram that the semiconductor storage unit according to one exemplary embodiment of the present invention is described.

Fig. 2 is the test pattern control unit shown in explanatory diagram 1, output driver and the block diagram of pipeline latch unit.

Fig. 3 is the circuit diagram of the comparing unit shown in explanatory diagram 2.

Fig. 4 A is the circuit diagram of the latch unit shown in explanatory diagram 2.

Fig. 4 B is the sequential chart of the operation that the latch unit according to one exemplary embodiment of the present invention is described.

Fig. 5 is the block diagram of the test signal generating unit shown in explanatory diagram 2.

Fig. 6 is the circuit diagram of the fail signal output unit shown in explanatory diagram 2 and output driver.

Fig. 7 A and Fig. 7 B is the operation that the semiconductor storage unit according to one exemplary embodiment of the present invention is described Sequential chart.

Detailed description of the invention

It is described more fully the exemplary embodiment of the present invention below with reference to accompanying drawings.But, the present invention can be with not Same mode is implemented, and should not be construed as limited to embodiments set forth herein.Exactly, it is provided that these are implemented Example is to make this specification understand and completely, and will pass on the scope of the present invention completely to those skilled in the art.? In this specification, identical reference represents identical parts in each drawings and Examples of the present invention.

Fig. 1 is the block diagram that semiconductor storage unit according to an embodiment of the invention is described.

See Fig. 1, semiconductor storage unit include such as four memory banks 110 to 140 of multiple memory bank, the overall situation input/ Output (GIO) line drive 112 to 144, write driver 150 and 161, pipeline latch unit 151 and 169, multiplexing Device 162, input/output (I/O) driver 172 and 174 and test pattern control unit 200.

I/O driver 172 and 174 is configured to respectively by from data pads LDQ and the input/output of data pads UDQ Data are driven.More specifically, I/O driver 172 and 174 has been respectively provided input buffer 154 and output driver 158 and input buffer 164 and output driver 168.Input buffer 154 and 164 receive respectively from data pads LDQ and The data of UDQ input.The data that input buffer 154 output receives are to write driver 150 and multiplexer 162.Input The data that buffer 164 output receives are to multiplexer 162.Latch it addition, output driver 158 and 168 receives from pipeline The data of device unit 151 and 169 output, and data are exported respectively to data pads LDQ and UDQ.Basis according to the present invention Exemplary embodiment, in test mode, output driver 158 is in response to fault adhesion (fail-stuck) signal FAIL_ STUCKD, driving data pad LDQ are to keep high adhesion state (high-stuck state).

Write driver 150 and 161 transfers data to the corresponding memory cell of memory bank 110 and 140.Pipeline latch The data of corresponding GIO line GIO_L and GIO_U are exported to data by unit 151 and 169 respectively via output driver 158 and 168 Pad LDQ and UDQ.Memory cell included in memory bank 110 to 140 stores data, and via corresponding GIO line GIO_ Data stored by L and GIO_U output.

According to the present embodiment of the present invention, in test mode, multiplexer 162 is in response to test mode signal TDRM Path is selected between write driver 161 and input buffer 154.Here, test mode signal TDRM is to deposit at quasiconductor The signal being activated during the test pattern of memory device.As a result, when the survey that write driver 150 will input from data pads LDQ When examination data are sent to the memory cell coupled with GIO line GIO_L, write driver 161 also will input from data pads LDQ Same test data be sent to the memory cell that couples with GIO line GIO_U.It is to say, write driver 150 and 161 Both receive test data, and each storage test data being sent in memory bank 110 to 140 from data pads LDQ Device unit.

In the normal mode, multiplexer 162 is in response to the test mode signal being deactivated during normal mode TDRM, and select the path between write driver 161 and input buffer 164.As a result, write driver 150 will be from data The data of pad LDQ input are sent to the memory cell corresponding with write driver 150, i.e. with GIO line GIO_L phase coupling The memory cell connect；And the data inputted from data pads UDQ are sent to and write driver 161 by write driver 161 Corresponding memory cell, i.e. the memory cell coupled with GIO line GIO_U phase.It is to say, write driver 150 He 161 each receive corresponding data the memorizer list being sent to memory bank 110 to 140 from data pads LDQ and UDQ Unit.

Test pattern control unit 200 receives the data from GIO line GIO_L and GIO_U output.In test mode, survey The data of the data of GIO line GIO_U with GIO line GIO_L are carried out by examination mode controlling unit 200 in response to test pattern letter TDRM Relatively, and based on comparative result fault adhesion signal FAIL_STUCKD is exported.

Fig. 2 is the block diagram of the test pattern control unit 200 shown in explanatory diagram 1.Below, for simplicity, will be with It is described as a example by such a exemplary cases, in described exemplary cases, it is provided that 8 GIO line GIO_U and 8 GIO line GIO_L, and provide 8 data pads LDQ and 8 data pads UDQ.

Seeing Fig. 2, test pattern control unit 200 includes fault detection unit 210 and latch unit 220, test letter Number generating unit 230 and fail signal output unit 250.

Fault detection unit 210 is by the data UDQ x GIO<0:7 of GIO line GIO_U>and data LDQ of GIO line GIO_L X GIO<0:7>compare to export fault detection signal GIO128SUM.Fault detection signal GIO128SUM is at GIO line The data UDQ x GIO<0:7 of GIO_U>in the data LDQ x GIO<0:7 of any data and GIO line GIO_L>corresponding number It is deactivated during according to difference.

Latch unit 220 is in response to test mode signal TDRM and gating signal GIOSTRB, by fault detection signal GIO128SUM latches to export fault latch signal GIOA.Gating signal GIOSTRB can be based on pipeline latch unit 151 With 169 in the pipeline Tong Bus with reading order that use input gating signal PINSTB and produce.This example according to the present invention Property embodiment, during packaging and testing pattern, latch unit 220 exports and is deactivated at fault detection signal GIO128SUM Adhesion (stcuk) is at the fault latch signal GIOA of predetermined logic level afterwards, regardless of gating signal GIOSTRB such as What.

Test signal generating unit 230 produces test letter based on fault latch signal GIOA and test mode signal TDRM Number FAIL_STUCK.

Fail signal output unit 250 receives test signal FAIL_STUCK also in response to test output signal TDRM_OUT Output fault adhesion signal FAIL_STUCKD.Here, at pipeline latch unit 151 at test pattern such as packaging and testing mould Export the test data of GIO line GIO_L under formula via the first to the 8th data pads LDQ0 to LDQ7 after, test output signal TDRM_OUT is activated.Here, fail signal output unit 250 exports fault adhesion signal FAIL_STUCKD, with by the first number It is driven to high/low adhesion state according to pad LDQ0.

As it has been described above, in the normal mode, pipeline latch unit 151 from GIO line GIO_L receive data LDQ xGIO < 0:7>, and export data DATA<0:7>to output driver 158.As a result, data DATA<0:7>are exported by output driver 158 Corresponding data pad among to first to the 8th data pads LDQ0 to LDQ7, thus read operation normally performs.

On the contrary, in test mode, test pattern control unit 200 is by the data UDQ xGIO < 0:7 of GIO line GIO_U >with the data LDQ x GIO<0:7 of GIO line GIO_L>compare, and export fault adhesion signal in response to comparative result FAIL_STUCKD.As a result, when a failure occurs, output driver 158 in response to fault adhesion signal FAIL_STUCKD by One data pads LDQ0 drives paramount adhesion state, thus the first data pads LDQ0 represents the fault of semiconductor storage unit.

In fig. 2, fault adhesion signal FAIL_STUCKD is input to drive the output of the first data pads LDQ0 to drive Device 158.But, in a preferred embodiment, fault adhesion signal FAIL_STUCKD can be input to drive first to All output drivers 158 of eight data pads LDQ0 to LDQ7 so that all of data pads LDQ0 to LDQ7 can table Show the fault of semiconductor storage unit.In another embodiment, can fail signal output unit 250 with drive second to Between each in the output driver 158 of the 8th data pads LDQ1 to LDQ7, switch element is set.Switch element can be by Fault adhesion signal FAIL STUCKD is supplied to any number of output driver 158 chosen, to control data pads LDQ0 Which pad to LDQ7 represents the fault of semiconductor device.Furthermore it is possible to controlled switch element by external command, or Person can realize switch element with metal option parts (metal option).

Fig. 3 is the circuit diagram of the fault detection unit 210 shown in explanatory diagram 2.

Seeing Fig. 3, fault detection unit 210 includes comparing unit 212 and sum unit 214.Comparing unit 212 such as wraps Include multiple biconditional gate 212_1 to 212_64, the plurality of biconditional gate 212_1 to 212_64 to be configured to receive each data UDQ x GIO<0:7>and LDQ x GIO<0:7>.Sum unit 214 include such as with door 216, described be configured to door 216 Receive the output of the plurality of biconditional gate 212_1 to 212_64.

At corresponding data UDQ x GIO<0:7>with data LDQ x GIO<0:7>be equal to each other time, biconditional gate 212_ Each in 1 to 212_64 outputs it signal activation.Complete in the output signal of biconditional gate 212_1 to 212_64 with door 216 When portion is activated, fault detection signal GIO128SUM is activated, and in the output signal of biconditional gate 212_1 to 212_64 By fault detection signal GIO128SUM deexcitation when any one is deactivated.

Therefore, fault detection unit 210 is at data UDQ x GIO<0:7>in any one with data LDQ xGIO<0: 7 > corresponding one different time, just by fault detection signal GIO128SUM deexcitation.

Fig. 4 A is the circuit diagram of the latch unit 220 shown in explanatory diagram 2.

Seeing Fig. 4 A, latch unit 220 includes delay control unit 221, assembled unit 225, d type flip flop 227 and anti- Phase device 228.

Delay control unit 221 is enabled in response to test mode signal TDRM, and by gating signal GIOSTRB postpone with Gating signal GIOSTRBD that output postpones.As reference, gating signal GIOSTRB is postponed and event by delay control unit 221 Barrier detector unit 210 produces time that fault detection signal GIO128SUM spent corresponding retardation.As a result, delay Gating signal GIOSTRBD is Tong Bu with fault detection signal GIO128SUM.Here, gating signal GIOSTRB be based on reading The pipeline that command synchronization produces inputs gating signal PINSTB and produces.

Assembled unit 225 is by gating signal GIOSTRBD of delay and the fault latch signal fed back from phase inverter 228 GIOA combines, to export clock signal GIOSTRBD_D of d type flip flop 227.Specifically, assembled unit 225 includes nor gate 225_1 and phase inverter 225_2, described nor gate 225_1 and phase inverter 225_2 are to feeding back the fault latch signal GIOA come and prolonging Slow gating signal GIOSTRBD performs inclusive-OR operation.

D type flip flop 227 detects signal GIO128SUM with clock signal GIOSTRBD_D synchronously latch fault.Here, D Trigger 227 is reset in response to test mode signal TDRM.Finally, phase inverter 228 is by the output by d type flip flop 227 Signal inversion exports fault latch signal GIOA.

Below, the operation of latch unit 220 is described in detail with reference to Fig. 4 A and Fig. 4 B.

Fig. 4 B is the sequential chart of the operation that latch unit 220 is described.

In test mode, each memorizer that test data input from data pads LDQ and are sent to memory bank Unit.

After reading order inputs, the test data in each memory cell being stored in memory bank are loaded in As data UDQ x GIO<0:7 on corresponding GIO line GIO_L and GIO_U>and LDQ x GIO<0:7>.Latch unit 220 Delay control unit 221 be enabled in response to test mode signal TDRM, and by by gating signal GIOSTRB postpone come Gating signal GIOSTRBD that output postpones.Assembled unit 225 gating signal GIOSTRBD based on delay is by clock signal GIOSTRBD_D exports to d type flip flop 227, and d type flip flop 227 detects signal with clock GIOSTRBD_D synchronously latch fault GIO128SUM.Finally, phase inverter 228 is by exporting fault latch signal GIOA by anti-phase for the output signal of d type flip flop 227.

Assume that fault detection signal GIO128SUM is deactivated under packaging and testing pattern.Now, assembled unit 225 base In the fault latch signal GIOA fed back from d type flip flop 227 and phase inverter 228, output is fixed to the clock of logic high Signal GIOSTRBD_D.As a result, d type flip flop 227 is in adhesion state (stuck state), thus fault latch signal GIOA It is latched to logic high.Therefore, under packaging and testing pattern, once breaking down, latch unit 220 just latches and defeated Go out to have the fault latch signal GIOA of logic high.

Fig. 5 is the block diagram of the test signal generating unit 230 shown in explanatory diagram 2.

Seeing Fig. 5, test signal generating unit 230 includes NAND gate 232 and phase inverter 234.NAND gate 232 and phase inverter 234 couples of test mode signal TDRM and fault latch signal GIOA perform AND operation, and export test signal FAIL_STUCK. Therefore, when test mode signal TDRM is activated under packaging and testing pattern, test signal generating unit 230 is by fault latch Signal GIOA output is as test signal FAIL_STUCK.

Fig. 6 is the fail signal output unit 250 shown in explanatory diagram 2 and the circuit diagram of output driver 158.

Seeing Fig. 6, fail signal output unit 250 includes fault adhesion signal output unit 252, and described fault adhesion is believed Number output unit 252 receives test signal FAIL_STUCK with output fault adhesion letter in response to test output signal TDRM_OUT Number FAIL_STUCKD to node NODE_A.Fault adhesion signal output unit 252 can realize with such as transmission gate 252_1, Described transmission gate 252_1 is configured in response to test output signal TDRM_OUT and optionally exports test signal FAIL_ STUCK is as fault adhesion signal FAIL_STUCKD.

In the case of test output signal TDRM_OUT is activated, transmission gate 252_1 will test signal FAIL_STUCK Output is as fault adhesion signal FAIL_STUCKD.On the contrary, situation about being deactivated at test output signal TDRM_OUT Under, transmission gate 252_1 is prohibited, in order to do not transmit test signal FAIL_STUCK as fault adhesion signal FAIL_ STUCKD.Here, under packaging and testing pattern, in the test data of GIO line GIO_L by pipeline latch unit 151 via number After exporting according to pad LDQ, test output signal TDRM_OUT is activated.

It addition, output driver 158 includes transmission gate 158_2, phase inverter 158_3 and 158_5, pullup driver 158_4 With pull-down driver 158_7.

Transmission gate 158_2 receives data DATA of input to node NODE_A in response to clock signal clk _ DO.Phase inverter 158_3 is by the signal inversion at node NODE_A to drive pullup driver 158_4, and phase inverter 158_5 is by node NODE_A Signal inversion to drive pull-down driver 158_7.Pullup driver 158_4 and pull-down driver 158_7 are respectively responsive to instead The output of phase device 158_3 and 158_5 and switched on/turn off.

In the normal mode, test signal FAIL_STUCK is deactivated.During read operation, output driver 158 In response to clock signal clk _ DO, input data DATA are driven to pullup or pulldown.Although not shown, complete read operation Afterwards, pullup driver 158_4 and pull-down driver 158_7 can be driven into shutoff.As a result, data pads LDQ exists Read operation completes to be in afterwards high-impedance state.

During packaging and testing pattern, due to test output signal TDRM_OUT be GIO line GIO_L data export extremely Being activated after data pads LDQ, therefore fault adhesion signal output unit 252 is based on test signal FAIL_STUCK output Fault adhesion signal FAIL_STUCKD.When fault adhesion signal FAIL_STUCKD is activated because of fault, pullup driver 158_4 is switched on and pull-down driver 158_7 is turned off.Therefore, data pads LDQ is in response to fault adhesion signal FAIL_ STUCKD becomes mains voltage level, and keeps high adhesion state.

The operation of semiconductor storage unit is described in detail referring to Fig. 1 to Fig. 7 B.

Fig. 7 A and Fig. 7 B is the operation that the semiconductor storage unit according to one exemplary embodiment of the present invention is described Sequential chart.More specifically, Fig. 7 A is the sequential chart that operation in the normal mode is described, and Fig. 7 B is that packaging and testing mould is described The sequential chart of the operation of formula.

See Fig. 7 A, in the normal mode, when reading order inputs, each memory cell in memory bank is stored up The data deposited are loaded into corresponding GIO line GIO_L and GIO_U.Pipeline latch unit 151 and 169 latches in response to pipeline Input control signal PIN<0:4>receives and latches the data of GIO line GIO_L and GIO_U, and latches output control in response to pipeline Signal POUT<0:4 processed>by data output to data pads LDQ and UDQ.As reference, although not shown, read behaviour each After completing, pullup driver 158_4 and pull-down driver 158_7 are both driven into shutoff.As a result, in each reading After having operated, data pads LDQ is in high-impedance state.

See Fig. 7 B, under packaging and testing pattern, when reading order inputs, be stored in each memorizer list of memory bank Data in unit are loaded on corresponding GIO line GIO_L and GIO_U.The fault detection unit of test pattern control unit 200 210 by the data UDQ x GIO<0:7 of GIO line GIO_U>with the data LDQ x GIO<0:7 of GIO line GIO_L>compare with Output fault detection signal GIO128SUM.Latch unit 220 is in response to the gating signal of activation Tong Bu with each reading order GIOSTRB carrys out latch fault detection signal GIO128SUM.

Data UDQ x GIO<0:7 as GIO line GIO_U>in any one data LDQ x with GIO line GIO_L GIO<0:7>in corresponding one different time, fault detection signal GIO128SUM is deactivated and fault latch signal GIOA quilt Activate.Now, the fault latch signal GIOA of activation is fed back to assembled unit 225, and assembled unit 225 output wants adhesion to exist Clock signal GIOSTRBD_D of specific logic level.As a result, once fault detection signal GIO128SUM is deactivated, lock Just output adhesion is at the fault latch signal GIOA of specific logic level, regardless of gating signal for storage unit 220 GIOSTRB how.

Test signal generating unit 230 produces test signal based on fault latch signal GIOA and test mode signal TDRM FAIL_STUCK.When test output signal TDRM_OUT quilt after the data of GIO line GIO_L export via data pads LDQ During activation, fail signal output unit 250 by fault adhesion signal FAIL_STUCKD activate with driving data pad LDQ paramount/ Low adhesion state.Therefore, under packaging and testing pattern, after the data of GIO line GIO_L export via data pads LDQ, number High/low adhesion state can be driven into, in order to malfunction is shown according to pad LDQ.

According to this exemplary embodiment of the present invention, in test mode, from the data of data pads LDQ input by simultaneously It is sent to GIO line GIO_L and GIO_U coupled with the multiple unit cells in memory bank, and test pattern control unit is by GIO The data of line GIO_U compare to export fault-signal based on comparative result with the data of GIO line GIO_L.Therefore, it can subtract Few/to reduce the time for testing the multiple unit cells in memory bank.

It addition, according to the exemplary embodiment of the present invention, it is provided that various for representing fault shape according to test pattern The method of state.Such as, under packaging and testing pattern, the defective memory cell of tool once being detected, test pattern controls single Unit's just output keeps the fault-signal of predetermined logic level.Afterwards, data, in response to test output signal, are welded by output driver Dish LDQ drives into adhesion in high/low state.

Although the exemplary embodiment with reference to the present invention has been particularly shown and described the present invention, people in the art Member will be understood that on the premise of the spirit and scope limited without departing from claims, can in form and Various change is carried out in details.

Therefore, aforementioned it is merely exemplary, and is not restrictive.Such as, illustrated and described herein any The number of element is merely exemplary.The present invention is limited only as defined in the following claims and equivalents thereof.

Claims (16)

1. a semiconductor storage unit, including:

Multiple memory banks, the plurality of memory bank each includes multiple first memory unit and multiple second memory list Unit；

First I/O unit, described first I/O unit is configured at described first memory unit with multiple The first data are transmitted between first data pads；

Second I/O unit, described second I/O unit is configured at described second memory unit with multiple The second data are transmitted between second data pads；

Path selection unit, described path selection unit is configured to during test pattern, transmits via described first data Described first data of pad input are to described first memory unit and described second memory unit；And

Test pattern control unit, described test pattern control unit is configured to during described test pattern, by described First data of one memory cell compare with the first data of described second memory unit, control based on comparative result Making at least one in described first data pads to represent malfunction, wherein, described test pattern control unit is reading One in described first data pads being controlled after having operated is adhesion state,

Wherein, described test pattern control unit includes:

Fault detection unit, described fault detection unit be configured to by described first data of described first memory unit with Described first data of described second memory unit compare, to export fault detection signal based on comparative result；

Latch unit, described latch unit is configured in response to the test pattern being activated during described test pattern Signal and the gating signal being triggered when reading order inputs, latch described fault detection signal and output fault latch letter Number；

Test signal generating unit, described test signal generating unit is configured to based on described fault latch signal and described survey Examination mode signal produces test signal；And

Fail signal output unit, described fail signal output unit is configured in response to described test signal and via institute State the test output signal being activated after the first data pads output data, export fault-signal.

2. semiconductor storage unit as claimed in claim 1, also includes input/output driver, and described input/output drives Device is configured in response to described fault-signal to drive described first data pads to represent malfunction.

3. semiconductor storage unit as claimed in claim 1, wherein, described fault detection unit includes:

Multiple comparing units, the plurality of comparing unit be configured to by described first data of described first memory unit with Described first data of described second memory unit compare；And

Sum unit, described sum unit is configured to output based on described comparing unit and exports described fault detect letter Number.

4. semiconductor storage unit as claimed in claim 3, wherein, described comparing unit each includes biconditional gate, institute State biconditional gate and each activate its output signal when corresponding first data are equal to each other.

5. semiconductor storage unit as claimed in claim 3, wherein, described sum unit includes gate, with to described ratio The output of relatively unit performs AND operation.

6. semiconductor storage unit as claimed in claim 1, wherein, the most described fault detection signal is deactivated, described Just output adhesion is at the described fault latch signal of specific logic levels, regardless of described gating signal such as latch unit What.

7. semiconductor storage unit as claimed in claim 1, wherein, described latch unit includes:

Delay control unit, described delay control unit is configured to described gating signal be postponed and export the gating letter of delay Number；

Assembled unit, described assembled unit is configured to gating signal based on described delay and described fault latch signal and defeated Go out clock signal；And

D type flip flop, described d type flip flop be configured to by with described clock signal synchronization latch described fault detection signal come Export described fault latch signal.

8. semiconductor storage unit as claimed in claim 7, wherein, described delay control unit has and described fault detect Unit produces time of being spent of described fault detection signal corresponding retardation, in order to by the gating signal of described delay with Described fault detection signal synchronizes.

9. semiconductor storage unit as claimed in claim 7, wherein, described delay control unit and the response of described d type flip flop It is enabled in described test mode signal.

10. semiconductor storage unit as claimed in claim 7, wherein, described assembled unit includes:

First gate, described first gate is configured to the gating signal to described delay and described fault latch signal is held Row negative OR operation；And

Second gate, described second gate is configured to anti-phase for the output of described first gate to export described clock Signal.

11. semiconductor storage units as claimed in claim 1, wherein, described fault is locked by described test signal generating unit Deposit signal and described test mode signal performs AND operation.

12. semiconductor storage units as claimed in claim 1, wherein, described fail signal output unit includes transmission gate, institute State transmission gate and be configured in response to the described test output signal described test signal of output as described fault-signal.

The method of 13. 1 kinds of testing semiconductor memory devices, said method comprising the steps of:

The data inputted via data pads are sent to first memory unit and the second memory unit of memory bank；

The data of described first memory unit are compared with the data of described second memory unit with based on comparing knot Fruit output fault detection signal；

In response to the test mode signal being activated during test pattern and the gating letter being triggered when reading order inputs Number, produce fault latch signal by being latched by described fault detection signal；

Test signal is produced based on described fault latch signal and described test mode signal；

Produce based on described test signal and the test output signal being activated after via described data pads output data Raw fault-signal；And

Based on described fault-signal, drive at least one in described data pads to represent fault adhesion state, wherein, described Data pads completes to be driven to described adhesion state afterwards at read operation.

14. methods as claimed in claim 13, wherein, when described fault detection signal is deactivated, described fault latch Regardless of described gating signal how signal is generated as adhesion in specific logic level,.

15. methods as claimed in claim 13, wherein, the step producing described fault latch signal comprises the following steps:

Described gating signal is postponed the gating signal postponed with output；

Gating signal based on described delay and described fault latch signal produce clock signal；And

By with described clock signal synchronization latch described fault detection signal and export described fault latch signal.

16. methods as claimed in claim 15, wherein, postpone to make gating signal and the institute of described delay by described gating signal State the retardation required for fault detection signal synchronizes.