CN102544094B - Nanowire field effect transistor with split-gate structure - Google Patents
Nanowire field effect transistor with split-gate structure Download PDFInfo
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- CN102544094B CN102544094B CN201010606167.4A CN201010606167A CN102544094B CN 102544094 B CN102544094 B CN 102544094B CN 201010606167 A CN201010606167 A CN 201010606167A CN 102544094 B CN102544094 B CN 102544094B
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- channel region
- splitting bar
- dielectric layer
- region
- gate dielectric
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Abstract
The invention discloses a nanowire field effect transistor with a split-gate structure. The transistor is formed by a split-gate electrode, a source region, a drain region, a channel region and a gate dielectric layer, wherein the channel region is columnar and is positioned in the center of the nanowire field effect transistor, and a material forming the channel region is a semiconductor material; the gate dielectric layer totally encircles the channel region coaxially; the split-gate electrode is positioned outside the gate dielectric layer and totally encircles the gate dielectric layer coaxially, and materials forming the split-gate electrode include two kinds of different materials; and the source region and the drain region are positioned at two sides of the channel region respectively. The introduction of the split-gate electrode structure can effectively improve the on-state current of nanowire transistors in prior arts and improve the current switch ratio and the working speed of devices. Simultaneously, the transistor is less affected by threshold voltage shift and drain induced barrier lowering effect resulted from short channel effect, and the performance of size reduction is more excellent.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit device, particularly a kind of nano-wire field effect transistor of splitting bar structure.
Background technology
The pursuit of integrated circuit industry to more speed, more high integration, more low-power consumption promotes semiconductor technology and advances, and the characteristic size of semiconductor device is more and more less.Because under nano-scale, conventional field effect transistor is subject to the restrictions such as short-channel effect, hydraulic performance decline.New device architecture is suggested, and comprises silicon-on-insulator, double grid, three grid and nano-wire field effect transistor.Wherein nano-wire field effect transistor can provide high current on/off ratio, causes potential barrier reduction effects less by short-channel effect and leakage simultaneously.Current on/off ratio is improved further in the basis of existing nano-wire field effect transistor, improve size reduce performance to manufacture high speed, low-power consumption semiconductor integrated circuit significant.
Summary of the invention
The object of this invention is to provide a kind of nano-wire field effect transistor device of splitting bar structure.
The nano-wire field effect transistor of splitting bar structure provided by the invention, is made up of splitting bar electrode, source region, drain region, channel region and gate dielectric layer;
Wherein, described channel region is column, and described channel region is positioned at the center of described nano-wire field effect transistor, and the material forming described channel region is semi-conducting material; Described gate dielectric layer coaxially surrounds described channel region entirely; Described splitting bar electrode is positioned at outside described gate dielectric layer, and coaxial complete surrounds described gate dielectric layer, and the material forming described splitting bar electrode is two kinds of different materials; Described source region and drain region lay respectively at the both sides of described channel region.
In above-mentioned nano-wire field effect transistor, the material forming described gate dielectric layer is silica.The length and the thickness that form this transistor split gate electrode structure are all adjustable, and the material forming this transistor split gate electrode structure is adjustable, two gate electrode doping types of division and concentration adjustable.Form the work function of work function higher than the material of the splitting bar electrode near drain region of the material of the splitting bar electrode near source region.The diameter of described splitting bar electrode is 10-50 nanometer, preferably 20 nanometers, and thickness is 5-20 nanometer, preferably 10 nanometers; Preferably, the material forming described splitting bar electrode is boron doping concentration is 7 × 10
12cm
-3polysilicon or phosphorus doping density be 5 × 10
13cm
-3polysilicon, the work function of described splitting bar electrode is 4.40-4.77 volt, specifically can be 4.40 volts or 4.77 volts.The thickness in described source region is 10-50 nanometer, preferably 30 nanometers; The thickness in described drain region is 10-50 nanometer, preferably 30 nanometers; The radius of described channel region is 5-25 nanometer, preferably 10 nanometers, and length is 20-100 nanometer, preferably 30 nanometers; The thickness of described gate dielectric layer is 1.0-3.0 nanometer, preferably 1.5 nanometers.Doping type and the concentration of channel region are adjustable, are 1 × 10 as can be boron doping concentration
11cm
-3silicon, source, to leak the semi-conducting material at two ends, doping type and concentration all adjustable, is 1 × 10 as being phosphorus doping density
20m
-3silicon.
The nano-wire field effect transistor of splitting bar structure provided by the invention, compared with traditional nano-wire transistor, in identical channel material and doping content, source-drain area material and doping content, gate insulator layer material and thickness, under the condition of identical channel region length, channel region radius, effectively can improve the ON state current of device after introducing splitting bar structure, keep less off-state current simultaneously, thus improve current on/off ratio and the operating rate of device.The simultaneously introducing of splitting bar structure can make nano-wire field effect transistor cause potential barrier by short-channel effect and leaking to reduce the threshold voltage shift that effect causes and reduce, and hot carrier's effect is also effectively suppressed, and improves the performance of device dimensions shrink.The present invention is the optimization of nano-wire field effect transistor device performance, and structure optimization specifies a new direction, and the integrated circuit being particularly useful for low-power consumption high speed uses.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of the nano-wire field effect transistor of splitting bar structure provided by the invention.
Fig. 2 is the impact of other parameter splitting bar structures on transistor channel region Electric Field Distribution of fixed crystal pipe.
Fig. 3 is the impact of other parameter splitting bar structures on transistor ON state current of fixed crystal pipe.
Fig. 4 is the impact of other parameter splitting bar structures on transistor off-state currents of fixed crystal pipe.
Fig. 5 is the impact of other parameter splitting bar structures on transistor channel region Potential Distributing of fixed crystal pipe.
Fig. 6 is that the length of other parameter change splitting bar structure two parts grid materials of fixed crystal pipe causes potential barrier reduction Benefit Transfer to the leakage of transistor under different channel lengths.
Embodiment
Below in conjunction with specific embodiment, the present invention is further elaborated, but the present invention is not limited to following examples.Described method is conventional method if no special instructions.Described material all can obtain from open commercial sources if no special instructions.
The nano-wire field effect transistor of embodiment 1, splitting bar structure and Performance Detection thereof
As shown in Figure 1, this transistor is made up of splitting bar electrode 1 and 2, source region 3, drain region 4, channel region 5 and gate dielectric layer 6 structural representation of the nano-wire field effect transistor of this splitting bar structure; Wherein, channel region 5, in column, is positioned at the center of this nano-wire field effect transistor; The coaxial full encirclement channel region 5 of gate dielectric layer 6; Splitting bar electrode 1 and 2 to be positioned at outside gate dielectric layer 6 and coaxially entirely to surround channel region 5, and the material forming splitting bar electrode 1 and 2 is two kinds of different materials; Splitting bar electrode 1 and 2 external identical electrical biass; Source region 3 and drain region 4 lay respectively at the both sides of channel region 5.
The diameter of splitting bar electrode 1 and 2 is 20 nanometers, and thickness is 10 nanometers, and wherein, the material of formation splitting bar electrode 1 is boron doping concentration is 7 × 10
12cm
-3polysilicon, its work function is 4.77 volts, and the material forming splitting bar electrode 2 is phosphorus doping density is 5 × 10
13cm
-3polysilicon, work function is 4.40 volts.It is 1 × 10 that the material in formation source region 3 and drain region 4 is phosphorus doping density
20cm
-3silicon, the length in source region and drain region is 30 nanometers.The material in constituting channel district 5 is boron doping concentration is 1 × 10
11cm
-3silicon, the radius of this channel region is 10nm, and length is 30 nanometers.The material forming gate dielectric layer 6 is silica, and the thickness of this gate dielectric layer is 1.5nm.
This transistor is prepared according to existing method, and preparation flow is summarized as follows:
1) on silicon wafer, silicon post is etched by circular silicon nitride hard mask;
2) high-temperature oxydation, corrosion reduce silicon column diameter and reach set point; Heat growth gate dielectric layer;
3) depositing polysilicon, boron doping forms splitting bar electrode 1; Depositing polysilicon, phosphorus doping forms splitting bar electrode 2; Wide-angle is injected phosphorus and is annealed, and prepares source-drain area 3 and 4;
4) standard CMOS process completes electrode preparation.
Below the performance of the nano-wire field effect transistor of this splitting bar structure and influencing factor are detected:
1) impact of splitting bar structures on transistor channel region Electric Field Distribution
As shown in Figure 2, the introducing of splitting bar structure makes transistor channel region surface field become bimodal distribution from the distribution of original single peak, and new peak value appears at the boundary of two kinds of grid materials.Bimodal distribution improves near source channel region Electric Field Distribution, thus makes charge carrier can obtain enough acceleration in this region, and therefore whole channel region charge carrier average speed also improve.The increase of charge carrier average speed determines the increase of channel current.Meanwhile, the peak electric field near drain electrode reduces, and this reduces the impact of hot carrier's effect.
2) splitting bar structure is on the impact of device current on-off ratio
As shown in Figure 3, splitting bar structure adds the ON state current of device.Although concerning Conventional nano field of line effect transistor, reducing grid material work function (being equivalent to increase grid voltage) also can the ON state current of increased device, but the off-state current of device also enlarges markedly simultaneously, as shown in Figure 4, and increasing degree is more much bigger than the increasing degree of ON state current.This causes the current on/off ratio of device from 10
10suddenly drop to 10
5.Therefore splitting bar structure is utilized to increase the ON state current of device thus the method better effects if of raising devices function speed.
3) impact of splitting bar structures on transistor channel region Potential Distributing
As shown in Figure 5, the introducing of splitting bar structure makes transistor channel region surface potential distribution occur an obvious ladder breakover point, and this breakover point is just in time below the boundary of two kinds of grid materials.Upper as can be seen from figure, when drain bias rises, the channel region surface potential be positioned at below splitting bar electrode 1 distributes substantially constant, the drain bias of increase mainly absorb by the channel region below splitting bar electrode 2.Therefore, splitting bar structure provides screen effect, by below splitting bar electrode 1 channel region shielding get up, be not subject to drain bias change impact, thus inhibit leakage cause potential barrier reduce effect.
4) length changing splitting bar structure two parts grid material under different channel lengths leaks the impact causing potential barrier reduction effect on device
Change the length of the channel region of this transistor into 30-50 nanometer, be spaced apart 5 nanometers, radius is constant, is still 10nm.The transistor of corresponding each channel length, the length of splitting bar electrode 1 and 2 is respectively 2: 1,1: 1 and 1: 2.As shown in Figure 6, splitting bar STRUCTURE DEPRESSION is leaked and is caused potential barrier and reduce effect, and larger near the relative length of the splitting bar electrode 2 in drain region 4, leaks to cause potential barrier to reduce the threshold voltage reduction that effect causes less.The relative length size of the splitting bar electrode 1 near source region 3 is comparatively large on the impact of device ON state current, and therefore splitting bar electrode 1 is otherwise known as " control gate ", adjusting means size of current; Splitting bar electrode 2 is called as " shield grid ", provides shielding action.
As from the foregoing, the nano-wire field effect transistor of splitting bar structure provided by the invention, can improve the ON state current of Conventional nano field of line effect transistor, faster devices operating rate, improves current on/off ratio; This device more effectively can also suppress short-channel effect simultaneously, suppresses leakage to cause potential barrier and reduces effect, improve the performance of device dimensions shrink.
Claims (7)
1. a nano-wire field effect transistor for splitting bar structure, is made up of splitting bar electrode, source region, drain region, channel region and gate dielectric layer;
Wherein, described channel region is column, and described channel region is positioned at the center of described nano-wire field effect transistor, and the material forming described channel region is semi-conducting material;
Described gate dielectric layer coaxially surrounds described channel region entirely;
Described splitting bar electrode is positioned at outside described gate dielectric layer, and coaxial complete surrounds described gate dielectric layer, and the material forming described splitting bar electrode is two kinds of different materials; Form the work function of work function higher than the material of the splitting bar electrode near drain region of the material of the splitting bar electrode near source region;
Described source region and drain region lay respectively at the both sides of described channel region;
The material forming described splitting bar electrode is boron doping concentration is 7 × 10
12cm
-3polysilicon or phosphorus doping density be 5 × 10
13cm
-3polysilicon, the work function of described splitting bar electrode is 4.40-4.77 volt;
The diameter of described splitting bar electrode is 10-50 nanometer, and thickness is 5-20 nanometer;
The thickness in described source region is 10-50 nanometer; The thickness in described drain region is 10-50 nanometer;
The radius of described channel region is 5-25 nanometer, and length is 20-100 nanometer; The thickness of described gate dielectric layer is 1-3 nanometer.
2. transistor according to claim 1, is characterized in that: it is 1 × 10 that the material forming described source region and drain region is phosphorus doping density
20cm
-3silicon.
3. transistor according to claim 1, is characterized in that: the material forming described channel region is boron doping concentration is 1 × 10
11cm
-3silicon.
4. transistor according to claim 1, is characterized in that: the material forming described gate dielectric layer is silica.
5. transistor according to claim 1, is characterized in that: the diameter of described splitting bar electrode is 20 nanometers, and thickness is 10 nanometers.
6. transistor according to claim 1, is characterized in that: the thickness in described source region is 30 nanometers; The thickness in described drain region is 30 nanometers.
7. transistor according to claim 1, is characterized in that: the radius of described channel region is 10 nanometers, and length is 30 nanometers; The thickness of described gate dielectric layer is 1.5 nanometers.
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| CN102544094B true CN102544094B (en) | 2015-06-17 |
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| CN102983170A (en) * | 2012-12-11 | 2013-03-20 | 北京大学深圳研究院 | Independent gate controlled junctionless nanowire field effect transistor |
| CN104241521B (en) * | 2013-06-18 | 2017-05-17 | 北京大学 | memory array and operation method and manufacturing method thereof |
| CN108389896B (en) * | 2018-01-22 | 2020-12-29 | 电子科技大学 | Double-gate tunneling field effect transistor capable of effectively restraining bipolar current |
| CN110164958B (en) * | 2019-04-25 | 2020-08-04 | 华东师范大学 | Asymmetric reconfigurable field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714412A (en) * | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
| CN1655340A (en) * | 2004-02-10 | 2005-08-17 | 株式会社瑞萨科技 | Semiconductor memory and making method thereof |
| CN101740619A (en) * | 2008-11-13 | 2010-06-16 | 北京大学 | Nano-wire field effect transistor |
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| US7893476B2 (en) * | 2006-09-15 | 2011-02-22 | Imec | Tunnel effect transistors based on silicon nanowires |
| CN1953206A (en) * | 2006-10-27 | 2007-04-25 | 安徽大学 | Homojunction combined gate field effect transistor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714412A (en) * | 1996-12-02 | 1998-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-level, split-gate, flash memory cell and method of manufacture thereof |
| CN1655340A (en) * | 2004-02-10 | 2005-08-17 | 株式会社瑞萨科技 | Semiconductor memory and making method thereof |
| CN101740619A (en) * | 2008-11-13 | 2010-06-16 | 北京大学 | Nano-wire field effect transistor |
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