CN102569081A - Method for manufacturing strain semiconductor device structure - Google Patents
Method for manufacturing strain semiconductor device structure Download PDFInfo
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- CN102569081A CN102569081A CN2010106006041A CN201010600604A CN102569081A CN 102569081 A CN102569081 A CN 102569081A CN 2010106006041 A CN2010106006041 A CN 2010106006041A CN 201010600604 A CN201010600604 A CN 201010600604A CN 102569081 A CN102569081 A CN 102569081A
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Abstract
The invention provides a method for manufacturing a strain semiconductor device structure. The method comprises the following steps of: providing a front end device structure, which comprises a semiconductor substrate and a grid structure positioned on the semiconductor substrate; forming a partially-ashable interval wall structure which is positioned on both sides of the grid structure and clings to the grid structure on the semiconductor substrate, wherein the partially-ashable interval wall structure comprises a first interval wall layer and a second interval wall layer in sequence from inside to outside; forming protective oxide layers on the surface of the semiconductor substrate, the surface of the partially-ashable interval wall structure and the surface of the grid structure; performing ion injection to form a source/drain region in the semiconductor substrate; removing the protective oxide layers and the second interval wall layer till the surface of the first interval wall layer is exposed; and forming strain introducing liner layers on the surface of the semiconductor substrate, the surface of the first interval wall layer and the surface of the grid structure. According to the method, adverse influences of SPT (Shortest Processing Time) processing on saturated current of a PMOS (P-channel Metal Oxide Semiconductor) transistor can be effectively suppressed, and damages to a siliconization region are avoided.
Description
Technical field
The present invention relates to semiconductor fabrication process, and in particular to a kind of method that is used to make the strained semiconductor device structure.
Background technology
At present, the principal element that influences field-effect transistor performance is the mobility of charge carrier rate, and wherein the mobility of charge carrier rate can influence the size of electric current in the raceway groove.The decline of carrier mobility not only can reduce transistorized switch speed in the field-effect transistor, but also the resistance difference when holding and closing is dwindled.Therefore, in the development of complementary metal oxide semiconductor field effect transistor (CMOS), effectively improve carrier mobility and always be one of transistor arrangement emphasis of design.
Conventionally; In the cmos device manufacturing technology with P-type mos field-effect transistor (PMOS) and N type metal oxide semiconductor field-effect transistor (NMOS) separate processes; For example, in the manufacturing approach of PMOS device, adopt the compression material, and in nmos device, adopt tensile stress material; Applying suitable stress to channel region, thereby improve the mobility of charge carrier rate.
Consider the complexity of technology, usually can on the surface of Semiconductor substrate and around the grid structure, form stress and introduce liner (liner), with to the channel region stress application.In the semiconductor fabrication process of the following technical merit of current 65nm, general pair nitride liner (the dual nitride liner) technologies that adopt realize the stress introducing.Particularly, two nitride liner process are meant and around nmos device, form the tension stress nitride liner and around the PMOS device, form the compression nitride liner.
On the other hand; Introduce liner more near channel region in order to make stress; So that channel region is applied suitable stress, and increase interlayer dielectric layer (ILD) gap filling window simultaneously, can after formation source/drain region, remove the clearance wall structure that is positioned at the grid structure both sides usually.This is called as stress near technology (claiming the SPT technology again).What routine was adopted is comprehensive SPT technology, that is, the clearance wall structure is removed fully, perhaps exposes until the sidewall that exposes grid structure to be positioned at the inboard skew clearance wall structure of clearance wall structure.Need specifying a bit, in this application, is benchmark with the center of grid structure, is the inboard near this center, is the outside away from this center.
Yet so comprehensive SPT technology can produce two adverse effects to the semiconductor device of final formation.On the one hand, remove the clearance wall structure fully, can damage the silicification area (will further describe hereinafter) that is positioned at grid structure top layer and source/surface, drain region, and cause Miller (Miller) electric capacity to increase.On the other hand; Owing to when making the PMOS device, also can form embedded germanium silicon (SiGe) stressor layers in Qi Yuan/drain region channel region is applied bigger compression; Therefore; When removing the clearance wall structure fully, also can cause certain damage, thereby cause the saturation current I of PMOS device the SiGe stressor layers that exposes
DsatReduce.
Please, wherein show of the influence of existing comprehensive SPT technology to the transistorized saturation current of strain PMOS with reference to Fig. 1.Abscissa is represented the spacing between grid structure and the contact hole; Ordinate is represented the transistorized saturation current decline of PMOS percentage; That is, adopt the attenuation of comprehensive SPT technical finesse saturation current afterwards and the ratio of the saturation current that does not adopt comprehensive SPT technical finesse.
As can be seen from Figure 1, adopt after existing comprehensive SPT technical finesse, the transistorized saturation current of PMOS obviously descends.For the less situation of the spacing between grid structure and the contact hole, this influence is then especially remarkable, almost reaches-5%.
Therefore, in view of above reason, be badly in need of a kind of method that is used to make the strained semiconductor device structure of exploitation, to address the above problem.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
For solving as stated existing problem in the prior art; The present invention provides a kind of method that is used to make the strained semiconductor device structure; Said method comprises: the front end device architecture is provided, and said front end device architecture comprises Semiconductor substrate and is positioned at the grid structure on the said Semiconductor substrate; On said Semiconductor substrate, form and be positioned at said grid structure both sides and but near the part ashing clearance wall structure of said grid structure, wherein, but said part ashing clearance wall structure comprises the first gap parietal layer and the second gap parietal layer from inside to outside successively; But on the surface and the surface of said grid structure of the surface of said Semiconductor substrate, said part ashing clearance wall structure, form the protection oxide layer; Carry out ion and inject, with formation source/drain region in said Semiconductor substrate; Remove said protection oxide layer and the said second gap parietal layer, till the surface of exposing the said first gap parietal layer; And on the surface of the surface of said Semiconductor substrate, the said first gap parietal layer and the surface of said grid structure, form stress and introduce laying.
Preferably, further comprise: on the surface of the surface of said Semiconductor substrate and said grid structure, form first material layer and second material layer successively but form said part ashing clearance wall structure; And through anisotropic dry etching said second material layer of etching and said first material layer successively, till the surface of the surface of exposing said grid structure and a part of said Semiconductor substrate.
Preferably, the constituent material of the said second gap parietal layer is a low-k materials.
Preferably, said low-k materials comprises amorphous carbon and black diamond.
Preferably, the said first gap parietal layer is L shaped, and comprises that lateral part and longitudinal component, said lateral part cover a part of said Semiconductor substrate, and said longitudinal component is positioned at said grid structure both sides and near said grid structure.
Preferably, the said first gap parietal layer comprises one deck oxide skin(coating) and/or one deck nitride layer at least at least.
Preferably, the thickness of the said first gap parietal layer is 2 ~ 10nm.
Preferably, the etching gas that adopted of said anisotropic dry etching comprises O
2, SO
2And He.
Preferably, said protection thickness of oxide layer is 20 ~ 100nm.
Preferably, the removal of the removal of said protection oxide layer and the said second gap parietal layer is carried out in same technological reaction chamber.
Preferably, the removal of the removal of said protection oxide layer and the said second gap parietal layer is carried out in the different process reaction chamber.
Preferably, the said second gap parietal layer is handled through plasma ashing and is removed.
Preferably, said plasma ashing is handled the podzolic gas that is adopted and is comprised O
2And CO
2In at least a.
Preferably; Said front end device architecture also comprises skew clearance wall structure; Said skew clearance wall structure is formed on the said Semiconductor substrate; And be positioned at said grid structure both sides and near said grid structure, but and the said part ashing clearance wall structure that forms subsequently is positioned at the said skew clearance wall structure outside and near said skew clearance wall structure.
Preferably, said strained semiconductor device structure is the nmos device structure, and said stress introducing laying is the tensile stress layer.
Preferably, said strained semiconductor device structure is the PMOS device architecture, and said stress introducing laying is a compressive stress layer.
Preferably, said front end device architecture also comprises embedded germanium silicon stressor layers, and said embedded germanium silicon stressor layers is formed on the groove that is arranged in said semiconductor substrate surface.
The method that is used to make strained semiconductor device according to the present invention has the following advantages.On the one hand; Different with prior art; The present invention comes to remove fully the clearance wall structure through dry plasma etch, but only removes the clearance wall structure through ground, plasma ashing processing section, therefore; Can avoid the embedded SiGe stressor layers that is exposed on the semiconductor substrate surface is caused damage, thereby can suppress the adverse effect that SPT handles the saturation current of pair pmos transistor effectively.On the other hand; Because the first remaining gap parietal layer covers the part that is formed with silicification area in the Semiconductor substrate; Thereby can avoid occurring as prior art when removing the clearance wall structure fully silicification area caused the situation of damage, and can prevent effectively that Miller capacitance from increasing.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.
In the accompanying drawing:
Fig. 1 shows the simulation curve figure of existing comprehensive SPT technology to the influence of the transistorized saturation current of strain PMOS;
Fig. 2 A-2F shows according to the preferred embodiment of the present invention and makes the schematic cross sectional view in the strained semiconductor device configuration process;
Fig. 3 shows another schematic cross sectional view of the front end device architecture that is adopted according to preferred embodiment of the present invention making strained semiconductor device structure; And
Fig. 4 shows the flow chart of method according to the preferred embodiment of the invention.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention makes the strained semiconductor device structure.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should give and be noted that, employed here term only is in order to describe specific embodiment, but not the intention restriction is according to exemplary embodiment of the present invention.As used herein, only if context spells out in addition, otherwise singulative also is intended to comprise plural form.In addition; It is to be further understood that; When using a technical term " comprising " and/or " comprising " in this manual; It indicates and has said characteristic, integral body, step, operation, element and/or assembly, does not exist or additional one or more other characteristics, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Now, will describe in more detail according to exemplary embodiment of the present invention with reference to accompanying drawing.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as the embodiment that is only limited to here to be set forth.Should be understood that, provide these embodiment of the present inventionly to disclose thoroughly and complete, and the design of these exemplary embodiments fully conveyed to those of ordinary skills in order to make.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and used the identical Reference numeral to represent components identical, thereby will omit description of them.
Here; Should give and be understood that; Though following description and diagram are example with independent making strain PMOS device architecture only, the present invention also is applicable to independent making strain NMOS device architecture and makes strain PMOS device architecture simultaneously and the situation of strain NMOS device architecture.
[preferred embodiment]
Below, will be example only with independent making strain PMOS device architecture, describe the method that is used to make the strained semiconductor device structure according to the preferred embodiment of the invention in detail with reference to Fig. 2 A-2F.
Please, wherein show according to the preferred embodiment of the present invention and make the schematic cross sectional view in the strained semiconductor device configuration process with reference to Fig. 2 A-2F.
At first, shown in Fig. 2 A, the front end device architecture is provided.Said front end device architecture comprises Semiconductor substrate 201 and is positioned at the grid structure 210 on the said Semiconductor substrate 201.
Wherein, the constituent material of Semiconductor substrate 201 can adopt unadulterated monocrystalline silicon, be doped with monocrystalline silicon, silicon-on-insulator (SOI) or the germanium silicon (SiGe) etc. of impurity.As an example, in the present embodiment, Semiconductor substrate 201 selects for use single crystal silicon material to constitute.
As an example, grid structure 210 can comprise the gate dielectric 202 and gate material layers 203 and grid hard masking layer 204 that stacks gradually, shown in Fig. 2 A.Gate dielectric 202 can comprise oxide, as, silicon dioxide (SiO
2) layer.Gate material layers 203 can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and the metal silicide layer.Wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; The conductive metal oxide layer can comprise titanium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.Grid hard masking layer 204 can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and the amorphous carbon.Wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD).Nitride layer can comprise silicon nitride (Si
3N
4) layer.Oxynitride layer can comprise silicon oxynitride (SiON) layer.
As another example, grid structure 210 can be semiconductor-range upon range of grid structure of oxide-nitride thing-oxide-semiconductor (SONOS).
As an example, on Semiconductor substrate 201, can also be formed with and be positioned at grid structure 210 both sides and near the skew clearance wall structure (not shown) of grid structure 210.Wherein, skew clearance wall structure can comprise one deck oxide skin(coating) and/or one deck nitride layer at least at least.Need to prove that said skew clearance wall structure is optional and nonessential, its sidewall that is mainly used in grill-protected electrode structure 210 when carrying out the injection of etching or ion is injury-free.The method of formation skew clearance wall structure and process conditions and parameter are known in those skilled in the art, repeat no more at this.
In addition, should give and be noted that front end device architecture described herein and that accompanying drawing is painted is not to be restrictive, but can also have other structures.For example, in Semiconductor substrate 201, can also be formed with isolation channel, buried regions etc.For the semiconductor device structure that adopts lightly-doped source/leakage (LDD) technology, also can comprise LDD district and halo (halo) district in the Semiconductor substrate 201.For the PMOS transistor, can also be formed with N trap (not shown) in the Semiconductor substrate 201, and before forming grid structure 210, can carry out once low dose of boron to whole N trap and inject, be used to adjust the transistorized threshold voltage V of PMOS
ThAnd; In the PMOS transistor; Because it is much little that the mobility of the mobility ratio electronics in hole is wanted; Simultaneously form embedded SiGe stressor layers so in existing technology, can combine dual liner process usually,, thereby improve the wherein mobility of holoe carrier effectively so that channel region is applied bigger compression in source/drain region.In the case, the front end device architecture also can comprise the embedded SiGe stressor layers (will describe in detail with reference to Fig. 3 after a while) in the source of being formed on/drain region.Method and the process conditions and the parameter that form embedded SiGe stressor layers in source/drain region all are known in those skilled in the art, repeat no more at this.
Then, shown in Fig. 2 B, be positioned at grid structure 210 both sides and near the part ashing clearance wall structure of grid structure 210 but on Semiconductor substrate 201, form.Here, need specifying that a bit, " from inside to outside " refers among this paper, is benchmark with the center of grid structure 210, near this center be in, away from this center be outside.Wherein, but said part ashing clearance wall structure comprises the first gap parietal layer 206 and the second gap parietal layer 207 from inside to outside successively.Wherein, the first gap parietal layer 206 can not ashing, but the second gap parietal layer 207 is ashing.Here " can not ashing " be meant to handle through plasma ashing and remove, and " but ashing " is meant to handle through plasma ashing and removes.
As an example; But said part ashing clearance wall structure can form through the following step: at first; On the surface of the surface of Semiconductor substrate 201 and grid structure 210, form first material layer and second material layer successively, wherein; Said first material layer can not ashing, but said second material layer is ashing; Then; Through said second material layer of anisotropic dry etching etching successively and said first material layer; Till the surface of exposing grid structure 210 and a part of Semiconductor substrate 201, thereby form the first gap parietal layer 206 as shown in the figure and the second gap parietal layer 207.
The first gap parietal layer 206 is formed L shaped, comprises lateral part 206a and longitudinal component 206b.Lateral part 206a covers the part of Semiconductor substrate 201, and longitudinal component 206b is positioned at grid structure 210 both sides and near grid structure 210.The first gap parietal layer 206 comprises one deck oxide skin(coating) and/or one deck nitride layer at least at least, and both gross thickness are approximately 2 ~ 10nm, for example can be 3nm, 5nm, 7nm or 9nm, and be preferably 7nm.Need be noted that, should make the first gap parietal layer 206 thin as far as possible so that the stress that forms subsequently introduce laying can as close as possible channel region so that better to its stress application.As an example, in this preferred embodiment, the first gap parietal layer 206a comprises one deck oxide skin(coating) and one deck nitride layer, and for example, the first gap parietal layer 206a can be the ON structure that is made up of from inside to outside silica and silicon nitride.Silicon nitride can use in two silicon hexachlorides, BTBAS (two (the 3rd-butylamine) silane) and the disilicone hexachloride any one to form as source gas with ammonia.Silica can use TEOS (tetraethoxysilane), SiH
4/ N
2O or BTBAS form as source gas.This first gap parietal layer 206a can adopt with the method for the conventional ON of formation clearance wall structure and process conditions and parameter and form, and repeats no more at this.
The constituent material of the second gap parietal layer 207 can be low-k (low k) material (k < 3.0).Wherein, low-k materials for example comprises amorphous carbon, black diamond (BD) etc.Particularly, the constituent material of the second gap parietal layer 207 can be Black Diamond
TMII (BDII) dielectric.This dielectric substance is the silica (being also referred to as silicon oxide carbide) that carbon mixes; Wherein carbon content is higher than 10%; It is commercially available by the holy big Ke Laola city of California, USA Applied Materials company, and it improves material and comprises through the UV sclerosis and have the BDIIx dielectric of 30% porosity and the BDIIebeam dielectric through electron-beam curing.In addition, the low-k materials of other carbon containings comprises Silk
With Cyclotene
(benzocyclobutene) dielectric material, it is commercially available by Dow Chemical company.Majority is organic or polyelectrolye in these materials, easily with oxygen or oxonium ion reaction generation gaseous state thing and be consumed.This low-k materials layer can form through being similar to the spin-coating method or the chemical vapor deposition (CVD) method that apply photoresist (PR).
As an example, the process conditions that said anisotropic dry etching is adopted can be technological reaction chamber pressure 2 ~ 50mT, top electrodes power (TCP) 100 ~ 1000W, bias voltage 100 ~ 1000V.The etching gas that is adopted can comprise O
2, SO
2And He.Wherein, O
2Flow velocity be about 10 ~ 500sccm, SO
2Flow velocity be about 10 ~ 500sccm, the flow velocity of He is about 10 ~ 200sccm.Here, sccm is under the standard state, just the flow of 1 atmospheric pressure, 25 degrees centigrade of following per minutes 1 cubic centimetre (1ml/min).
In addition; What call for attention is; If be formed with skew clearance wall structure in grid structure 210 both sides and near grid structure 210 as previously mentioned, but the said part ashing clearance wall structure that then forms in this step will be positioned at the said skew clearance wall structure outside and near said skew clearance wall structure.
Then, shown in Fig. 2 C, but on the surface of the surface of the surface of Semiconductor substrate 201, said part ashing clearance wall structure and grid structure 210, form protection oxide layer 208.The thickness of protection oxide layer 208 for example can be about 20 ~ 100nm, and it is mainly used in and when injecting formation source/drain region through ion, protects the second gap parietal layer 207.
As an example, can be through under 700 ~ 750 ℃ temperature, forming oxide layer 208 as source gas through the chemical vapor deposition (CVD) method with tetraethoxysilane (TEOS).As another example, can be with SiH under 210 ℃ temperature
4And N
2The mist of O forms oxide layer 208 as source gas through the CVD method.
The additive method of formation protection oxide layer 208 and process conditions and parameter are well-known to those skilled in the art, repeat no more at this.
Then, shown in Fig. 2 D, carry out ion and inject, with formation source/drain region 209 in Semiconductor substrate 201.Source/the drain region 209 that forms in this step is actually heavy-doped source/drain region.In existing CMOS manufacturing process, source/drain region 209 constitutes the source/drain region of semiconductor device with aforementioned LDD district and halo region.Afterwards, can carry out annealing in process, to activate the ion that injects.The process conditions of formation source/drain region and annealing in process and parameter are known in those skilled in the art, repeat no more at this.
Here; Need be noted that; After ion injects formation source/drain region, can adopt conventional silicification technics to form silicification area (indicating by dotted line among the figure) usually at the near surface in grid structure 210 top layers, source/drain region 209, the purpose of this operation is the active area formation Metal Contact at all silicon; This layer Metal Contact can make Si and subsequently the deposition electric conducting material more closely combine, thereby can reduce contact resistance.Usually, can select the metal material of titanium (Ti), and after deposition, make itself and Si react the silicide (TiSi that generates Ti as deposition
2).Certainly, the metal material that is adopted is not limited to Ti, but can also comprise Ta, W, Co, Ni, Pt, Pd and their alloy.The deposition of metal material layer for example can be used sputter, chemical vapour deposition (CVD), evaporation, chemical solution deposition, plating etc.
Then, shown in Fig. 2 E, remove the protection oxide layer 208 and the second gap parietal layer 207, till the surface of exposing the first gap parietal layer 206.
As an example, can remove protection oxide layer 208 through the plasma dry etching, wherein, process conditions for example can be technological reaction chamber pressure 2 ~ 50mT, top electrodes power (TCP) 100 ~ 1000W, bias voltage 0 ~ 500V.The etching gas that is adopted can comprise CF
4, He and O
2Wherein, CF
4Flow velocity be about 10 ~ 200sccm, the flow velocity of He is about 10 ~ 100sccm, O
2Flow velocity be about 0 ~ 50sccm.
As an example, can remove the second gap parietal layer 207 through original position (in-situ) or the processing of dystopy (ex-situ) plasma ashing.Help improving the flexibility of technology like this.What need explain is; Here mentioned original position is meant in removing the used same technological reaction chamber of protection oxide layer 208 carries out ashing treatment; Dystopy then is meant after having removed protection oxide layer 208 semiconductor wafer moved in another technological reaction chamber carries out ashing treatment, to remove the second gap parietal layer 207.
The podzolic gas that ashing treatment adopted for example can comprise O
2And CO
2In at least a, and can comprise CH
4, H
2O and N
2H
2In one or more.In this preferred embodiment, employed podzolic gas comprises O
2And N
2H
2Wherein, O
2Flow velocity be about 1000 ~ 8000sccm, be 2000sccm, 3000sccm, 5000sccm, 7000sccm for example, and be preferably 5000sccm, N
2H
2Flow velocity be about 100 ~ 1000scc, be 200sccm, 300sccm, 500sccm, 700sccm, 900sccm for example, and be preferably 500sccm.
At last, shown in Fig. 2 F, on the surface of the surface of the surface of Semiconductor substrate 201, the first gap parietal layer 206 and grid structure 210, form stress and introduce laying 211.As an example, stress introduce laying 211 can be by such as Si
3N
4Such nitride constitutes.Particularly, around nmos device, form the tension stress nitride liner, and around the PMOS device, form the compression nitride liner.Can adopt conventional two nitride liner process to form stress and introduce laying 211, its process conditions and parameter are known in those skilled in the art, repeat no more at this.
Please, wherein show another schematic cross sectional view of the front end device architecture that is adopted according to preferred embodiment of the present invention making strained semiconductor device structure with reference to Fig. 3.As shown in Figure 3, embedded SiGe stressor layers 312 is formed on the groove that is arranged in Semiconductor substrate 301 surfaces, and said groove is formed on the part that will form source/drain region in the Semiconductor substrate 301.Should give and be noted that, do not flush with the surface of Semiconductor substrate 301, also can be formed the flush of its surface and Semiconductor substrate 301 though embedded SiGe stressor layers 312 is depicted as its surface in the drawings.
Below, please with reference to Fig. 4, wherein show the flow chart of method according to the preferred embodiment of the invention, be used to schematically illustrate the flow process of entire method.
At first, in step S401, the front end device architecture is provided.Said front end device architecture comprises Semiconductor substrate and is positioned at the grid structure on this Semiconductor substrate.
Then, in step S402, be positioned at said grid structure both sides and near the part ashing clearance wall structure of said grid structure but on said Semiconductor substrate, form.Wherein, said clearance wall structure comprises the first gap parietal layer and the second gap parietal layer from inside to outside successively.
Then, in step S403, but on the surface and the surface of said grid structure of the surface of said Semiconductor substrate, said part ashing clearance wall structure, form the protection oxide layer.
Then, in step S404, carry out ion and inject, with formation source/drain region in said Semiconductor substrate.
Then, in step S405, remove said protection oxide layer and the said second gap parietal layer, till the surface of exposing the said first gap parietal layer.
At last, in step S306, on the surface of the surface of said Semiconductor substrate, the said first gap parietal layer and the surface of said grid structure, form stress and introduce laying.
The method that is used to make strained semiconductor device according to the present invention has the following advantages.On the one hand; Different with prior art; The present invention comes to remove fully the clearance wall structure through the plasma dry etching, but only removes the clearance wall structure through ground, plasma ashing processing section, therefore; Can avoid the embedded SiGe stressor layers that is exposed on the semiconductor substrate surface is caused damage, thereby can suppress the adverse effect that SPT handles the saturation current of pair pmos transistor effectively.On the other hand; Because the first remaining gap parietal layer covers the part that is formed with silicification area in the Semiconductor substrate; Thereby can avoid occurring as prior art when removing the clearance wall structure fully silicification area caused the situation of damage, and can prevent effectively that Miller capacitance from increasing.
[industrial applicibility of the present invention]
Semiconductor device according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).For example, can be memory circuitry according to IC of the present invention, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.For example, IC chip according to the present invention can be used for consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (17)
1. method that is used to make the strained semiconductor device structure, said method comprises:
The front end device architecture is provided, and said front end device architecture comprises Semiconductor substrate and is positioned at the grid structure on the said Semiconductor substrate;
On said Semiconductor substrate, form and be positioned at said grid structure both sides and near the clearance wall structure of said grid structure, wherein, said clearance wall structure comprises the first gap parietal layer and the second gap parietal layer from inside to outside successively;
On the surface and the surface of said grid structure of the surface of said Semiconductor substrate, said clearance wall structure, form the protection oxide layer;
Carry out ion and inject, with formation source/drain region in said Semiconductor substrate;
Remove said protection oxide layer and the said second gap parietal layer, till the surface of exposing the said first gap parietal layer; And
On the surface of the surface of said Semiconductor substrate, the said first gap parietal layer and the surface of said grid structure, form stress and introduce laying.
2. method according to claim 1 is characterized in that, forms said clearance wall structure and further comprises:
On the surface of the surface of said Semiconductor substrate and said grid structure, form first material layer and second material layer successively; And
Through said second material layer of anisotropic dry etching etching successively and said first material layer, till the surface of the surface of exposing said grid structure and a part of said Semiconductor substrate.
3. method according to claim 1 is characterized in that, the constituent material of the said second gap parietal layer is a low-k materials.
4. method according to claim 3 is characterized in that said low-k materials comprises amorphous carbon and black diamond.
5. method according to claim 1; It is characterized in that the said first gap parietal layer is L shaped, and comprises lateral part and longitudinal component; Said lateral part covers a part of said Semiconductor substrate, and said longitudinal component is positioned at said grid structure both sides and near said grid structure.
6. method according to claim 1 is characterized in that, the said first gap parietal layer comprises one deck oxide skin(coating) and/or one deck nitride layer at least at least.
7. method according to claim 1 is characterized in that, the thickness of the said first gap parietal layer is 2 ~ 10nm.
8. method according to claim 1 is characterized in that, the etching gas that said anisotropic dry etching is adopted comprises O
2, SO
2And He.
9. method according to claim 1 is characterized in that, said protection thickness of oxide layer is 20 ~ 100nm.
10. method according to claim 1 is characterized in that, the removal of the removal of said protection oxide layer and the said second gap parietal layer is carried out in same technological reaction chamber.
11. method according to claim 1 is characterized in that, the removal of the removal of said protection oxide layer and the said second gap parietal layer is carried out in the different process reaction chamber.
12. method according to claim 1 is characterized in that, the said second gap parietal layer is handled through plasma ashing and is removed.
13. method according to claim 12 is characterized in that, said plasma ashing is handled the podzolic gas that is adopted and is comprised O
2And CO
2In at least a.
14. method according to claim 1; It is characterized in that; Said front end device architecture also comprises skew clearance wall structure; Said skew clearance wall structure is formed on the said Semiconductor substrate, and is positioned at said grid structure both sides and near said grid structure, but and the said part ashing clearance wall structure that forms subsequently is positioned at the said skew clearance wall structure outside and near said skew clearance wall structure.
15. method according to claim 1 is characterized in that, said strained semiconductor device structure is the nmos device structure, and said stress introducing laying is the tensile stress layer.
16. method according to claim 1 is characterized in that, said strained semiconductor device structure is the PMOS device architecture, and said stress introducing laying is a compressive stress layer.
17. method according to claim 16 is characterized in that, said front end device architecture also comprises embedded germanium silicon stressor layers, and said embedded germanium silicon stressor layers is formed on the groove that is arranged in said semiconductor substrate surface.
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| CN104952797A (en) * | 2014-03-26 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing semiconductor device |
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