CN102576698A - 具有增强的接地接合可靠性的引线框封装 - Google Patents

具有增强的接地接合可靠性的引线框封装 Download PDF

Info

Publication number
CN102576698A
CN102576698A CN2010800427454A CN201080042745A CN102576698A CN 102576698 A CN102576698 A CN 102576698A CN 2010800427454 A CN2010800427454 A CN 2010800427454A CN 201080042745 A CN201080042745 A CN 201080042745A CN 102576698 A CN102576698 A CN 102576698A
Authority
CN
China
Prior art keywords
pad
die attach
attach pad
encapsulation
closing line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010800427454A
Other languages
English (en)
Inventor
邵卫·李
埃因新·吴
赤锡·刘
义金·李
李汉明@尤金·李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of CN102576698A publication Critical patent/CN102576698A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/85051Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • H01L2224/85207Thermosonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

本文描述改进将裸片线接合到接地或其它外部触点的可靠性的各种半导体封装布置及方法。在一个方面中,所述裸片上的所选择的接地垫线接合到位于引线框的系杆部分上的接合区。所述系杆连接到从所述系杆的所述接合区下移安置的暴露的裸片附接垫。在一些实施例中,所述接合区及引线处于所述裸片及裸片附接垫上方大体上同一高度。所述裸片、接合线及所述引线框的至少一部分可用塑料包封材料包封,而使所述裸片附接垫的接触表面暴露以促进将所述裸片附接垫电耦合到外部装置。

Description

具有增强的接地接合可靠性的引线框封装
技术领域
本发明大体上涉及基于引线框的半导体封装。更明确地说,本发明描述增强裸片与充当所述封装的触点的裸片附接垫之间的电连接的可靠性的布置。
背景技术
许多半导体封装利用金属引线框以提供集成电路裸片与外部组件之间的电互连。通常使用称为“接合线”的非常小的电线来将裸片上的I/O垫(经常称为“接合垫”)电连接到引线框中的对应引线/触点。通常,为了防护,将裸片、接合线及引线框的若干部分包封在塑料中,而留下引线框的若干部分暴露以促进到外部装置的电连接。
许多引线框包括裸片附接垫(DAP),在装配封装期间,裸片附接垫支撑裸片。在一些此类封装中,裸片附接垫在封装的表面(通常底部表面)上暴露。暴露的裸片附接垫可协助封装的热管理,因为裸片附接垫提供良好的热传导路径,用于耗散由裸片产生的过多热量。在一些暴露的DAP封装中,裸片附接垫也被用作封装的电触点。最常见的是,将裸片附接垫用作接地垫,虽然在少数封装中,可将裸片附接垫用作电源垫,且理论上可将裸片附接垫代替地用作信号垫。
当将裸片附接垫用作电触点时,常使用接合线来将裸片上的一个或一个以上接地I/O垫电连接到裸片附接垫(常称为“下接合法”的工艺)。更常见地是,将非常细的金线或铜线用作接合线,且引线框由铜或基于铜的合金形成。因为金不能较好地粘附到铜,因此裸片附接垫的顶部表面(及引线框的其它相关部分)通常镀有薄银膜,薄银膜比铜更好地粘附到金接合线。偶尔发生的问题是在使用装置期间,裸片有时会从裸片附接垫分层。分层可同样发生在裸片附接垫与包封裸片的模制化合物之间。当发生分层时,裸片相对于裸片附接垫的运动可有时使下接合线从裸片附接垫分离或以其它方式破坏下接合线。
相似的分层问题可同样发生在引线处。举例来说,分层有时发生在模制材料与引线指状物之间,尤其在引线框的镀银的区中。模制材料与引线之间的分层还可能损坏接合线。
适合用在具有暴露的裸片附接垫的封装中的代表性引线框在图1A及1B中概略说明。图1A是具有附接及电连接到引线框的裸片的引线框100的俯视平面图。图1B是图1A的沿着截面线A-A截取的横截面侧视图。使用接地接合线106将裸片102线接合到接地的裸片附接垫104。接地接合线106的一端附接到裸片102上的接地I/O垫110,而另一端直接附接到裸片附接垫104。在使用金接地接合线106的设计中,为了改进接合质量,接地的裸片附接垫104常常镀有银。另外,为了在集成电路设计中按需电连接裸片,接合线108将裸片102的I/O垫116连接到引线框124的相关联引线112。举例来说,接合线108可用于将裸片102连接到电源、信号线或任一其它合适的电连接。裸片附接垫104由系杆118支撑。
尽管常规的接地接合方法在许多应用中有效,但要一直不懈地努力以改进接地接合的可靠性。
发明内容
为了达到本发明的前述或其它目的,裸片上的一个或一个以上所选择的I/O垫(例如,接地I/O垫)电耦合到系杆的承载裸片附接垫的部分,或连接到此系杆的结构。接合区升高到高出裸片附接垫。因为将裸片电连接到裸片附接垫的接合线接合在与裸片附接垫不同的平面内,所以即使裸片从裸片附接垫分层,所述接合也不大可能断裂或被损坏。万一发生分层,从接合区下移安置裸片附接垫允许更多的相对运动,从而导致具有增强的电可靠性的接地接合。在一些优选实施例中,接合区比相关联系杆的其它部分宽。此布置允许多个接地I/O垫电耦合到裸片附接垫。
一些实施例可具有矩形放大接合区,而其它实施例可具有熔合引线形状。所述熔合引线形状包括从系杆朝裸片附接垫向内延伸的至少一个指状物部分。放大接合区的增大的表面积虑及系杆上的多个接地接合位置。同样,在一些设计中,引线框可具有多个系杆及放大的接合区,其可位于裸片的相对侧上或其它合适的位置处。
为了保护任一相关联装置,还可将半导体封装包封在塑料包封材料中。裸片附接垫的背表面常常暴露以促进到外部装置的电连接。
在研究下图及详细的描述后,本发明的其它设备、方法、特征及优势对于所属领域的技术人员来说将是或将变得显而易见。希望所有此些额外的系统、方法、特征及优势包含在本说明书内,在本发明的范围内,且受所附权利要求书保护。
附图说明
在以下图式中,相同参考标号有时用于指定相同结构元件。还应了解,图中的描绘是概略的且不按比例绘制的。本发明及其优势可参考结合附图进行的以下描述得到更好的理解,其中:
图1A说明现有技术集成电路封装的俯视平面图,其中裸片上的接地接合垫向下接合到接地的裸片附接垫。
图1B说明沿着截面A-A截取的图1A中所展示的封装的侧视横截面图。
图2A说明根据本发明的一个实施例的在系杆上具有放大接合区的引线框装置区域的俯视平面图。
图2B说明根据本发明的一个实施例的包括附接到图2A的引线框装置区域的裸片的集成电路封装的俯视平面图,其中裸片电耦合到系杆的放大接合区。
图2C说明根据本发明的一个实施例沿着图2B的实施例的截面B-B截取的侧视横截面图,其展示电耦合到系杆的升高的接合区的接地接合线。
图2D说明根据本发明的一个实施例沿着图2B的实施例的截面C-C截取的侧视横截面图,其展示电耦合到引线的接合线。
图3A说明根据本发明的另一个实施例的在系杆上具有放大接合区的引线框装置区域的俯视平面图。
图3B说明根据本发明的另一个实施例的集成电路封装的俯视平面图,所述集成电路封装包括附接到图3A的引线框装置区域的裸片,其中裸片电耦合到系杆的放大接地区。
图3C说明根据本发明的一个实施例沿着截面F-F截取的图3B的集成电路封装的侧视横截面图,其中接地I/O垫耦合到系杆的放大接合区。
图4A说明集成电路封装的侧视横截面图,其中接合线经由具有缝在球上的楔形的球形接合(ball bond with wedge stitched on ball,BSOB)直接耦合到裸片附接垫。
图4B说明集成电路封装的侧视横截面图,其中接合线是经由缝在球上的反向球(reverse ball stitched on ball,RBSOB)直接耦合到裸片附接垫。
图5A到5C说明根据本发明的一个实施例的含有多个装置区域514的引线框带524的俯视平面图。
具体实施方式
本发明大体上涉及用于将裸片上的所选择的I/O垫(例如,接地垫)电连接到基于引线框的集成电路封装中的裸片附接垫的经改进的设计及技术。
在以下描述中,为了提供对本发明的透彻理解而陈述许多具体细节。然而,应理解,本发明可在没有一些或全部的这些具体细节的情况下实践。在其它例子中,为了不会不必要地模糊本发明,没有详细描述众所周知的工艺操作。
如在背景部分所描述,一些基于引线框的集成电路封装经设计以使得通过将裸片直接线接合到引线框的接地裸片附接垫部分而将裸片电接地。这种工艺经常称为“下接合法”。在下接合的封装中有时出现的问题是裸片有时可从裸片附接垫分层,这可能导致裸片与裸片附接垫之间的相对运动。当此运动发生时,存在的风险是下接合的接合线可从裸片附接垫撕下或以其它方式遭损坏或断裂,这可导致较差的电可靠性。
为解决这个问题,本发明描述一种集成电路封装,其中裸片上的所选择的接地I/O垫使用接合线电耦合到系杆的线接合焊盘区。所述系杆是引线框的部分,所述系杆直接连接到裸片附接垫,且在封装期间机械支撑裸片附接垫,但一般不是本身既定用作封装的电触点。在来自现有技术的许多设计中,系杆为仅用于支撑裸片附接垫的薄金属片。本申请案进一步预期使用系杆作为集成电路封装的接地平面的部分。裸片附接垫的裸片安装表面相对于系杆的线接合焊盘区下移安置。在一些实施例中,线接合焊盘区在封装内与引线在同一高度。尽管所描述的实施例预期使用裸片附接垫作为接地触点,但应理解,裸片附接垫可用作用于其它功能的触点,例如电源或信号端子。
首先参考图2A到2D,展示本发明的第一实施例。图2A说明引线框面板224的一个装置区域214的俯视平面图,其包括引线212、系杆218及裸片附接垫204。除了这些组件之外,放大接合区220与系杆218一体形成。裸片附接垫204由系杆218承载,且因此电耦合且机械耦合到系杆218,系杆218又附接到引线框面板224中的支撑杆223。多个引线212同样机械附接到引线框224,且朝裸片附接垫204向内延伸。接合区220可经由系杆218通过电连接到接地的裸片附接垫204而接地。当引线框由铜或铜合金形成时,一般希望用银膜来电镀接合区220以增强金接合线的粘附性。
在此第一实施例中,接合区220形成为矩形区域,其实际上是系杆218的一部分。然而,将了解的是,接合区220可在系杆上其它合适的位置形成,且可采用其它合适的形状及大小。接合区220通常比其相关联系杆218的其它部分宽。出于多种原因,较大的区可为有用的,例如提供较大的表面积以接合多根线。同样地,尽管在此实施例中展示两个系杆及放大的接合区,但每一装置区域214可具有仅一个系杆及接合区,或替代地按裸片设计所要求的两个以上系杆及接合区。图2A说明将两个系杆218机械连接到裸片附接垫204的相对侧上的裸片附接垫204,但系杆218还可附接到任一(或全部)裸片附接垫隅角。
图2B描绘集成电路封装200的俯视平面图。在图2B中,裸片202机械贴附到裸片附接垫204的裸片安装表面226。裸片包括位于裸片202的作用表面上的多个I/O垫(接合垫)。第一组I/O垫216中的每一I/O垫经设计以将裸片202连接到引线框224的相关联引线212。I/O垫216可用于多种目的,包括将裸片202连接到电源、信号线、接地平面或其它合适的功能。如在图2B中所说明,I/O垫216使用接合线208电连接到引线212。尽管可使用例如铜等其它合适的材料,但是在优选实施例中,接合线208由金制成。此外,接合线优选热声波接合,从而产生I/O垫216处的金球接合及对应引线212处的针脚式接合。
第二组I/O垫210中的每一I/O垫(“接地I/O垫”)经设计以将裸片202电连接到接地平面,接地平面在此情况下是放大的接合区220。在图2A到2D的实施例中,接地I/O垫210经由接地接合线206接合到系杆218的放大的接合区220。优选的是,接地接合线由金制成,且由以超声波方式形成所述接合,从而产生I/O垫210处的金球接合及对应的放大接合区220处的针脚式接合。尽管在图2B中两个接地接合线206连接到每一接合区220,但一些实施例中将仅一个或替代地大于两个接地接合线连接到单个接合区是有用的。集成电路封装200还可包括包封材料,所述包封材料未在图2B中展示。
图2C说明沿着截面B-B截取的图2B中呈现的封装200的侧视横截面图。如在图中所展示,裸片附接垫204的裸片安装表面226优选从系杆218的放大的接合区220下移安置距离h1,将接地接合线206耦合到升高的、放大接合区220改进接地接合的电可靠性。所述连接不易受到因裸片分层而导致的损坏,因为由接地接合线形成的环路允许比现有技术设计多的相对运动,例如图1中展示的情况。裸片与裸片附接垫之间的相对运动因此不大可能导致对接地接合线206的损坏。
图2D是沿着截面C-C截取的图2B中所呈现的封装200的侧视横截面图。引线212朝裸片202向内延伸。尽管在图2D中引线212不直接上覆在裸片202上,但所属领域的技术人员将了解,引线212可不同地定位。裸片附接垫204的裸片安装表面226从引线212下移安置距离h2。距离h2可大于或小于图2C中展示的距离h1。然而,在优选实施例中,距离h1与距离h2大体上相等,以致放大的接合区220及引线212定位在裸片安装表面226上方大约同一高度处。
裸片202、裸片附接垫204、引线212、I/O垫216、接地I/O垫210、接合线208、接地接合线206及系杆218的若干部分可包封在包封材料或模制材料222内。模制化合物一般是非导电性塑料或树脂。在图2C及2D中所说明的实施例中,引线212的外面部分从包封的封装200的侧面延伸以促进与合适的衬底的电连接。
裸片附接垫204的底部表面穿过包封材料222而暴露,以促进将裸片附接垫204电耦合到电接地平面。因为裸片附接垫204电连接到系杆218的接合区220,因此这呈现一种将接地I/O垫电连接到接地的方法。
接下来参考图3A到3C,将描述根据本发明的另一个实施例。虽然本文中呈现出若干差异,但本实施例中的许多特征大体上相似于图2A到2D的特征。图3A展示在系杆318上具有放大的接合区320且具有朝裸片附接垫304向内延伸的多根引线312的引线框装置区域314。图3A的放大的接合区320的形状(熔合引线形状)包括从系杆318朝裸片附接垫304向内延伸的至少一个指状物部分330。接合区320的大表面积虑及单个系杆318上的多个接地接合位置。接合区320又通过系杆318电连接到裸片附接垫304。
图3B描绘具有附接到裸片附接垫304的裸片302的集成电路封装300的俯视图。如同图2B的实施例,接合线308将所选择的I/O垫316从裸片302电连接到引线312。I/O垫316可用于多种目的,包括将裸片302连接到电源、信号线、接地平面或其它合适的功能。在优选实施例中,接合线308由金制成。此外,接合线308优选以超声波方式接合,从而产生I/O垫316处的金球接合及对应引线312处的针脚式接合。
第二组I/O垫310经设计以将裸片302电连接到接地平面。在本实施例中,接地I/O垫310经由接地接合线306接合到系杆318的放大的接合区320。优选的是,接地接合线306由金制成,且接合是以超声波方式形成,从而产生I/O垫310处的金球接合及对应的放大接合区320处的针脚式接合。
当适度按比例缩放时,图3B中展示的实施例的沿着截面D-D及E-E截取的侧视图可大体上分别相似于图2C及2D的实施例中所描绘的侧视图。作为所述实施例之间的一个显著差别,图3C说明沿着图3B的截面F-F截取的集成电路封装300的侧视横截面图。接地接合线306将接地I/O垫310电连接到系杆318的放大的接合区320。在图3C的图中,接地接合线306以超声波方式接合到接合区320的朝裸片向内延伸的指状物部分330。
如同在图2A到2D中展示的实施例,裸片附接垫304的裸片安装表面326从放大的接合区320下移安置距离h1且从引线312下移安置距离h2。尽管这些距离不需要相等,但接合区320及引线312可处于裸片附接垫304的裸片安装表面326上方的大体上同一高度。放大的接合区320的升高的定位通过降低接地接合线306上的相关联应力而改进接地接合的可靠性。
相似于上文所描述的实施例,集成电路封装300优选装入包封材料或模制材料322内。裸片附接垫304的背表面穿过包封材料322而暴露,以连接到接地平面,如上文详细揭示。
图4A及4B呈现又一种改进集成电路封装中的接地接合可靠性的方法。在图4中说明的实施例中,裸片402上的接地I/O垫410中的一些使用具有缝在球上的楔形的球形接合(BSOB)技术直接耦合到接地的裸片附接垫404。如可在图4A中所见,引线接合凸块432最初在接地的裸片附接垫404的裸片安装表面426上形成。凸块432通过使用标准的线接合毛细管以超声波方式将球形接合沉积到接地的裸片附接垫404上而制成。不是继续挤压所述线,所述毛细管在靠近球形接合凸块432的顶部截短所述线,以使得仅一线接合“球”或“凸块”432仍在裸片附接垫404的顶上。可使用比通常用于线接合多的力来形成凸块432,这具有使凸块平坦的效果,从而增大其接合表面积并增大所得凸块的强度。
接着使用接合线406将接地I/O垫410线接合到凸块432。接合线406可由金、铜或其它合适的导电材料形成。在线接合工艺期间,第二球形接合优选形成于接地I/O垫410处,且针脚形接合434可形成于凸块432的顶部上。因此,接合线406经由位于在凸块432的顶上的针脚形接合434电耦合到接地的裸片附接垫404。在一些实施例中,凸块432近似为接地I/O垫410处的球形接合的高度的三分之一。如果裸片附接垫404镀有银,那么图4中揭示的实施例改进接地接合的可靠性。这是因为球形接合凸块432粘附到镀银的裸片附接垫404好于粘附到针脚形接合。因此,凸块432提供接合线406与裸片附接垫404的裸片安装表面426之间的界面,从而降低接合线406中的剪应力,并改进可靠性。
图4B中说明替代球上针脚技术(stitch on ball techenique)。在此实施例中,最初的凸块442形成于裸片402上的接地I/O垫410上。接着,使用接合线406将裸片附接垫404电连接到I/O垫410上的凸块442。在线接合工艺期间,第二球形接合446形成于裸片附接垫404上。再次,线接合机可利用比正常更多的接合力,这具有使凸块平坦的效果,从而增大接合强度及表面积。
接下来参考图5A到5C,将描述本发明的又一实施例。如所属领域的技术人员将熟悉,使用引线框带524来装配集成电路封装常常是有用的,引线框带524支撑装置区域514的阵列528。这种配置虑及集成电路封装的大量生产。尽管图5A到5C描绘装置区域相似于图2A到2D中所呈现的装置区域,但同样应了解,引线框可支撑图3A到3C及图4的实施例,以及任何其它合适的实施例。
图5A描绘引线框带524的具有大量装置区域514的部分。尽管多种其它布置是可能的(如一维阵列、非线性布置等),但通常装置区域514布置在面板524上的至少一个二维阵列528中。在所说明的实施例中,展示装置区域514的五个二维阵列528。然而,应了解,可提供或多或少的阵列528。尽管各种替代实施例中可使用其它合适的材料(例如铝),但引线框板524通常由铜或基于铜的合金形成。每一装置区域514可包含如在以上实施例中的任一者中所描述的集成电路封装。当将所述封装装配到引线框524上之后,按需要使引线框524单一化,以生产多个个别的集成电路封装,其准备好用在任一所要应用中。可布置所述单一化以牺牲系杆518,且可使引线512与引线框524的裸片附接垫部分504电绝缘。
本发明同样可用在任一合适的集成电路封装式样中。在图2A到2D及图3A到3C的实施例中,举例来说,集成电路封装200可用作在裸片202的相对侧上具有两行引线212的双列直插式封装(DIP)。当然,所揭示的封装同样可在多种其它封装式样中有用,例如四方平坦封装(QFP)及薄型小外形封装(TSOP)。
尽管已经详细描述本发明的仅几个实施例,但应了解,本发明可以许多其它形式实施而不脱离本发明的精神及范围。举例来说,除了耦合到电接地平面,放大的接合区可同样用于耦合到电源或信号输入。
在所说明的预期到系杆的区的线接合的实施例中,裸片附接垫相对于引线及系杆的线接合区两者下移安置。然而,在一些封装(例如,QFN或LLP封装)中,可能希望引线的底部表面充当与裸片附接垫的底部表面共面的触点。在此些实施例中,可能希望上移安置裸片附接垫的接合区,使得引线触点与裸片附接垫仍大体上共面。因此,应将本发明的实施例视为说明性而非限制性的,且本发明不限制于本文所给出的细节,而是可在所附权利要求书的范围及等效物内修改。

Claims (20)

1.一种集成电路封装,其包含:
引线框,其包括:裸片附接垫;多个引线,其与所述裸片附接垫物理隔离且电绝缘;及第一系杆,其与所述裸片附接垫一体形成,且机械耦合并电耦合到所述裸片附接垫,所述第一系杆包括第一接合区,其中所述裸片附接垫具有裸片安装表面,所述裸片安装表面相对于所述第一接合区下移安置;
裸片,其安装在所述裸片附接垫的所述裸片安装表面上,所述裸片具有大量I/O垫;
第一组接合线,其中所述第一组接合线中的每一接合线具有附接到相关联I/O垫的第一端及附接到相关联引线的第二端,从而将所述相关联I/O垫电耦合到所述相关联引线;及
第二组接合线,所述第二组接合线中有至少一个接合线,所述第二组接合线中的每一接合线具有附接到所述裸片上的相关联I/O垫的第一端及附接到所述第一系杆上的所述第一接合区的第二端,借此所述第一接合线到所述第一接合区的附接点相对于包围所述裸片安装表面的平面偏移。
2.根据权利要求1所述的集成电路封装,其中所述裸片附接垫电耦合到接地,且其中附接到所述第二组接合线中的接合线的每一I/O垫是接地I/O垫。
3.根据权利要求1或2所述的集成电路封装,其中所述第一接合区的宽度大体上大于所述第一系杆的其它部分的宽度。
4.根据前述权利要求中任一权利要求所述的集成电路封装,其进一步包含塑料包封材料,其包封所述裸片、所述接合线及所述引线框的至少一部分而使所述裸片附接垫的底部表面暴露以充当电触点。
5.一种电子装置,其包括
衬底,其具有接地垫;
根据权利要求4所述的集成电路封装,其安装在所述衬底上,其中附接到所述第二组接合线中的接合线的每一I/O垫是接地I/O垫,且所述裸片附接垫的所述底部表面电耦合且机械耦合到所述衬底接地垫,从而通过所述接合线、所述第一系杆及所述裸片附接垫将所述接地I/O垫电连接到接地。
6.根据权利要求5所述的集成电路封装,其中所述封装是在所述封装的相对侧上具有两行引线且无引线从所述封装的相对端延伸的双列直插式封装,且其中所述第一系杆朝所述封装的不具有引线的端延伸。
7.根据前述权利要求中任一权利要求所述的集成电路封装,其中所述第二组接合线包括多个接合线,其各自耦合到所述第一接合区。
8.根据前述权利要求中任一权利要求所述的集成电路封装,其进一步包含:
第二系杆,其与所述裸片附接垫一体形成,且具有第二接合区,其中至少一个额外接合线附接到所述第二放大的接合区。
9.根据权利要求8所述的集成电路封装,其中所述第一及第二接合区的顶部表面与所述引线的顶部表面大体上共面。
10.根据前述权利要求中任一权利要求所述的集成电路封装,其中所述第一接合区的形状是具有朝所述裸片向内延伸的至少一个指状物部分的熔合引线形状。
11.一种集成电路封装,其包含:
引线框,其具有裸片附接垫及多个引线;
裸片,其安装在所述裸片附接垫上,所述裸片包括多个I/O垫;
至少一个线接合凸块,其形成于所述裸片附接垫上;
大量接合线,每一接合线电连接到相关联I/O垫,其中第一组所述接合线中的每一者将相关联I/O垫电连接到相关联引线,且其中所述接合线中的至少一者是下接合线,下接合线间接紧固到所述裸片附接垫,其中每一下接合线针脚式接合到相关联的线接合凸块,以将所述下接合线电连接到所述裸片附接垫。
12.一种集成电路封装,其包含:
引线框,其包括多个引线、一裸片附接垫及至少一个系杆,所述系杆连接到所述裸片附接垫且包括线接合焊盘区,其中所述裸片附接垫及所述引线中的每一者充当所述封装的电触点,且所述系杆不充当所述封装的电触点,且其中所述裸片支撑表面相对于所述线接合焊盘区下移安置;
裸片,其安装于所述裸片附接垫上,所述裸片包括多个I/O垫,所述I/O垫包括至少一个接地I/O垫;
大量接合线,每一接合线电连接到相关联I/O垫,其中第一组所述接合线中的每一者将相关联I/O垫电连接到相关联引线,且其中所述接合线中的至少一者是接地接合线,其将相关联接地I/O垫连接到所述系杆的所述线接合焊盘区,从而间接地将所述接地接合线电连接到所述裸片附接垫,借此所述接地接合线到所述线接合焊盘区的附接点相对于包围所述裸片安装表面的平面垂直偏移;及
包封材料,其包封所述裸片、所述接合线及所述引线框的至少一部分,其中所述裸片附接垫的底部表面在所述封装的底部表面上暴露,以促进将所述裸片附接垫电耦合到电接地,从而通过所述接地接合线、所述系杆及所述裸片附接垫将所述接地I/O垫电连接到接地。
13.根据权利要求1所述的集成电路封装,其中所述第一接合区的宽度大体上大于所述第一系杆的其它部分的宽度。
14.根据权利要求1所述的集成电路封装,其进一步包含塑料包封材料,其包封所述裸片、所述接合线及所述引线框的至少一部分,而使所述裸片附接垫的底部表面暴露以充当电触点。
15.一种电装置,其包括:
衬底,其具有接地垫;
根据权利要求14所述的集成电路封装,其安装在所述衬底上,其中附接到第二组接合线中的接合线的每一I/O垫是接地I/O垫,且裸片附接垫的底部表面电耦合且机械耦合到所述衬底接地垫,从而通过所述接合线、所述第一系杆及所述裸片附接垫将所述接地I/O垫电连接到接地。
16.根据权利要求15所述的集成电路封装,其中所述封装是在所述封装的相对侧上具有两行引线且无引线从所述封装的相对端延伸的双列直插式封装,且其中所述第一系杆朝所述封装的不具有引线的端延伸。
17.根据权利要求1所述的集成电路封装,其中所述第二组接合线包括多个接合线,其各自耦合到所述第一接合区。
18.根据权利要求1所述的集成电路封装,其进一步包含:
第二系杆,其与所述裸片附接垫一体形成且具有第二接合区,其中至少一个额外接合线附接到所述第二放大的接合区。
19.根据权利要求18所述的集成电路封装,其中所述第一及第二接合区的顶部表面与所述引线的顶部表面大体上共面。
20.根据权利要求1所述的集成电路封装,其中所述第一接合区的形状是具有朝所述裸片向内延伸的至少一个指状物部分的熔合引线形状。
CN2010800427454A 2009-10-19 2010-10-08 具有增强的接地接合可靠性的引线框封装 Pending CN102576698A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/581,609 2009-10-19
US12/581,609 US8093707B2 (en) 2009-10-19 2009-10-19 Leadframe packages having enhanced ground-bond reliability
PCT/US2010/052061 WO2011049764A2 (en) 2009-10-19 2010-10-08 Leadframe packages having enhanced ground-bond reliability

Publications (1)

Publication Number Publication Date
CN102576698A true CN102576698A (zh) 2012-07-11

Family

ID=43878665

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010800427454A Pending CN102576698A (zh) 2009-10-19 2010-10-08 具有增强的接地接合可靠性的引线框封装

Country Status (5)

Country Link
US (1) US8093707B2 (zh)
JP (1) JP2013508974A (zh)
CN (1) CN102576698A (zh)
TW (1) TWI515855B (zh)
WO (1) WO2011049764A2 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110115063A1 (en) * 2009-11-18 2011-05-19 Entropic Communications, Inc. Integrated Circuit Packaging with Split Paddle
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US9337240B1 (en) * 2010-06-18 2016-05-10 Altera Corporation Integrated circuit package with a universal lead frame
TWI489607B (zh) * 2010-11-23 2015-06-21 登豐微電子股份有限公司 封裝結構
CN102800765A (zh) * 2012-03-21 2012-11-28 深圳雷曼光电科技股份有限公司 Led封装结构及其封装工艺
US9147656B1 (en) * 2014-07-11 2015-09-29 Freescale Semicondutor, Inc. Semiconductor device with improved shielding
US9922904B2 (en) 2015-05-26 2018-03-20 Infineon Technologies Ag Semiconductor device including lead frames with downset
US10249556B1 (en) * 2018-03-06 2019-04-02 Nxp B.V. Lead frame with partially-etched connecting bar
US20190287918A1 (en) * 2018-03-13 2019-09-19 Texas Instruments Incorporated Integrated circuit (ic) packages with shields and methods of producing the same
CN109192715B (zh) * 2018-09-20 2024-03-22 江苏长电科技股份有限公司 引线框结构、封装结构及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297918A (ja) * 1998-04-10 1999-10-29 Nec Corp リードフレーム及び半導体装置及び半導体装置の製造方法
US20020024122A1 (en) * 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US20030205790A1 (en) * 1996-10-25 2003-11-06 Hinkle S. Derek Multi-part lead frame with dissimilar materials
CN2831428Y (zh) * 2005-01-06 2006-10-25 威盛电子股份有限公司 引脚架封装体
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328079A (en) 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
JP3074264B2 (ja) * 1997-11-17 2000-08-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
US6398556B1 (en) * 1998-07-06 2002-06-04 Chi Fai Ho Inexpensive computer-aided learning methods and apparatus for learners
JP3062691B1 (ja) * 1999-02-26 2000-07-12 株式会社三井ハイテック 半導体装置
WO2001009953A1 (en) * 1999-07-30 2001-02-08 Amkor Technology, Inc. Lead frame with downset die pad
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package
US20020096766A1 (en) 2001-01-24 2002-07-25 Chen Wen Chuan Package structure of integrated circuits and method for packaging the same
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
AU2003218085A1 (en) 2002-03-12 2003-09-29 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
US20060012035A1 (en) 2002-12-10 2006-01-19 Infineon Technologies Ag Method of packaging integrated circuits, and integrated circuit packages produced by the method
TWI250632B (en) * 2003-05-28 2006-03-01 Siliconware Precision Industries Co Ltd Ground-enhancing semiconductor package and lead frame
KR100536898B1 (ko) 2003-09-04 2005-12-16 삼성전자주식회사 반도체 소자의 와이어 본딩 방법
US7214606B2 (en) 2004-03-11 2007-05-08 Asm Technology Singapore Pte Ltd. Method of fabricating a wire bond with multiple stitch bonds
JP4252563B2 (ja) * 2005-07-05 2009-04-08 株式会社ルネサステクノロジ 半導体装置
US8937393B2 (en) 2007-05-03 2015-01-20 Stats Chippac Ltd. Integrated circuit package system with device cavity

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205790A1 (en) * 1996-10-25 2003-11-06 Hinkle S. Derek Multi-part lead frame with dissimilar materials
JPH11297918A (ja) * 1998-04-10 1999-10-29 Nec Corp リードフレーム及び半導体装置及び半導体装置の製造方法
US20020024122A1 (en) * 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant
CN2831428Y (zh) * 2005-01-06 2006-10-25 威盛电子股份有限公司 引脚架封装体

Also Published As

Publication number Publication date
TW201125092A (en) 2011-07-16
US8093707B2 (en) 2012-01-10
WO2011049764A2 (en) 2011-04-28
TWI515855B (zh) 2016-01-01
US20110089556A1 (en) 2011-04-21
JP2013508974A (ja) 2013-03-07
WO2011049764A3 (en) 2011-11-17

Similar Documents

Publication Publication Date Title
CN102576698A (zh) 具有增强的接地接合可靠性的引线框封装
US6459148B1 (en) QFN semiconductor package
CN102201388B (zh) 方形扁平无引线半导体封装及其制作方法
KR100445073B1 (ko) 듀얼 다이 패키지
CN100416815C (zh) 包括无源器件的引线框架及其形成方法
CN102742009A (zh) 裸片附着垫接地接合增强
KR101189001B1 (ko) 프리-몰드, 클립 본딩 멀티-다이 반도체 패키지 장치
CN102194806A (zh) 堆栈式双晶片封装及其制备方法
TWI485819B (zh) 封裝結構及其製造方法
US8288858B2 (en) Semiconductor device
JP3470111B2 (ja) 樹脂封止型半導体装置の製造方法
JP6092084B2 (ja) 半導体装置および半導体装置の製造方法
US7875968B2 (en) Leadframe, semiconductor package and support lead for bonding with groundwires
US6774479B2 (en) Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for producing the electronic device
US20110210432A1 (en) Semiconductor device and method of manufacturing the same
US7750444B2 (en) Lead-on-chip semiconductor package and leadframe for the package
JP5275019B2 (ja) 半導体装置
CN107534036A (zh) 用于具有垂直堆叠的芯片和组件的电子系统的引线框架
US5223740A (en) Plastic mold type semiconductor device
KR20010059916A (ko) 멀티칩 모듈 반도체패키지
JP2007287809A (ja) 積層型半導体装置及び積層型半導体装置の製造方法
JP2005175512A (ja) 半導体装置
KR940006582B1 (ko) 세라믹 반도체 패키지 구조 및 그 제조방법
KR100222300B1 (ko) 리드 프레임 및 그를 이용한 트랜지스터 패키지
CN100477198C (zh) 芯片封装结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120711