CN102591822B

CN102591822B - Data processor

Info

Publication number: CN102591822B
Application number: CN201110381951.4A
Authority: CN
Inventors: 小山秀见; 川村正信; 池口卓弥; 松本真典; 川尻洋之
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2007-03-08
Filing date: 2008-03-10
Publication date: 2015-12-16
Anticipated expiration: 2028-03-10
Also published as: JP2008250987A; JP2015111469A; CN101261609A; CN102591822A; JP5717896B2; CN101261609B; JP5502933B2; JP2014132490A; JP4994254B2; JP2012168978A

Abstract

The invention provides and a kind ofly realize the high speed of data processing and the event response control technology of offloading the CPU.Except adopting interruptable controller (13) also to adopt event link controller (6), this event link controller (6) respond a dynamic control signal (STR) of the event signal (EVT) that produces and the output work corresponding with circuit module.Circuit module can produce event signal, and event link controller produces above-mentioned dynamic control signal according to the above-mentioned event signal defined by event control information (ECI) with corresponding between dynamic control signal.Specify event signal due to information can be stored according to event and play the associating, therefore, it is possible to control according to the order of sequence by the action of multiple circuit modules of this association defined of dynamic control signal.As the situation of interrupt processing, with based on central processing unit preservation or return process, do not need to adopt for the two priority classes of the interrupt request of competing yet.

Description

Data processor

The divisional application that the application is the applying date is on March 10th, 2008, application number is 200810083726.0, denomination of invention is the application for a patent for invention of " data processor and control system ".

Technical field

The present invention relates to the control technology responding the event produced inside and outside data processor, relate to the technology being effectively applicable to such as slice microcomputer.

Background technology

The control technology of the event responsively produced inside and outside data processor has interrupt control technique.In use disconnected when controlling, for the generation of various interruption source, interruptable controller controls it and accepts according to priority or interrupt mask level, determines the interruption main cause that receives and interrupts to central processing unit request.The central processing unit of requested interruption carries out processing to make the state of internal register before this etc. be saved in storer, thereafter, extracting the vector corresponding to interrupting main cause, transferring to the interrupt handling routine that execution is extracted.So, respond the process of its main cause from generation interruption main cause to execution before, need to carry out the arbitration of interruptable controller, the specimens preserving of central processing unit, needed to expend the regular hour before beginning interrupt processing.When frequent generation interrupt processing, the burden of central processing unit also can increase.

In known case investigation after the present invention completes, find following patent documentation.In patent documentation 1, describe following content: adopt and connect into circular interrupt request arbitration circuit, to make interrupt orders produce movement, thus can give coequally all interrupt request sources to perform the chance of interrupting.Following content is described: daisy chain (daisychain) is carried out to multiple interrupt processing device and connects in patent documentation 2, each interrupt processing device directly input from central processing unit interruption acknowledge signal and interrupt acceptor level signal, determine whether the interrupt request that have recognised oneself in advance, the judgement high speed of permitting to make interruption.

Patent documentation 1: Japanese Unexamined Patent Publication 07-105124 publication

Patent documentation 2: Japanese Laid-Open Patent Publication 64-55667 publication

Summary of the invention

But in interrupt control technique in the past, fully do not realize the high speed of data processing and fully alleviate the burden of central authorities' process, the data-handling efficiency that result leaves whole system reduces such problem.Especially, enroll in the data processor controlling purposes at equipment, along with the generation of event, temporally sequence carries out multiple interrupt processing successively to carry out desired control work, and the situation of repeatedly carrying out such a sequential control work is more.Sometimes also wish to carry out multiple control work concurrently.The present inventor finds, if consider such feature, mode is as follows useful, that is, according to the content that must process, the combination of the peripheral circuit required for regulation and the job order of peripheral circuit, control the response process for event.

The object of the present invention is to provide and a kind ofly can contribute to realizing the high speed of data processing, alleviate the event response control technology of central processing unit burden.

Another object of the present invention is to provide and can enroll at equipment the data processor that the event response control of control purposes makes the data-handling efficiency of entire system improve.

Above-mentioned and other objects of the present invention and new feature will be able to clear by the record of this instructions and accompanying drawing.

Below, representative art scheme disclosed in simple declaration the application.

That is, except adopting interruptable controller also to adopt event link controller, this event link controller responds the event signal produced, and what export the work corresponding with circuit module plays dynamic control signal.Circuit module can produce event signal, and above-mentioned event link controller produces above-mentioned dynamic control signal according to the correspondence between the above-mentioned event signal defined by event control information and dynamic control signal.Thereby, it is possible to by above-mentioned event control information specify event signal with the associating, therefore, it is possible to control in order by the work of multiple circuit modules of this association defined of dynamic control signal.This is as the situation of interrupt processing, with based on central processing unit preservation or return process, do not need to adopt for the such control of the two priority classes of the interrupt request of competing yet.

Simple declaration adopts the effect that in invention disclosed herein, representative technical scheme obtains as follows.

That is, can realize can contributing to the high speed of data processing, alleviating the event response control technology of central processing unit burden.

In addition, can enroll at equipment the event response controlling purposes to control the data-handling efficiency of entire system is improved.

Accompanying drawing explanation

Fig. 1 is the block diagram of the microcomputer illustrating the present invention's example.

Fig. 2 is the block diagram schematically illustrating that the starting of the interruption control undertaken by interruptable controller and the circuit module undertaken by event link controller controls.

Fig. 3 be represent by the key diagram of object lesson of groundwork of circuit module specified by dynamic control signal.

Fig. 4 is the key diagram of the main object lesson of the event signal that indication circuit module exports.

Fig. 5 exemplifies event signal and the key diagram of the relation linked playing dynamic control signal.

Fig. 6 is the key diagram of the control method of the event link exemplified based on event control information.

Fig. 7 is the block diagram of other structures exemplifying event link controller.

Fig. 8 is the block diagram of another concrete structure that the structure exemplifying the part be connected on A/D converter and timer controls as event link.

Fig. 9 is the structure that exemplifies the part be connected in the input/output port block diagram as another concrete structure of event link controller.

Figure 10 is the action specification figure of data input action when exemplifying the starting indicating data input action in input/output port.

Figure 11 is the action specification figure of data input action when exemplifying the starting indicating data input action in input/output port.

Figure 12 is the key diagram of the unitisation of the inputoutput data position exemplified in input/output port.

Figure 13 exemplifies CPU to perform the block diagram that the first program carries out the object lesson associated using the situation of the particular procedure of multiple circuit module to start with action as event generation.

Figure 14 is the block diagram situation adopting interrupt processing to tackle event signal respectively represented as comparative example.

Figure 15 is that contrast is based on the disposal interrupted and the sequential chart in the processing time based on the process of event link.

Figure 16 is the block diagram rotating output action for illustration of the position of being undertaken by input/output port.

Figure 17 is the sequential chart rotating output action for illustration of the position of being undertaken by input/output port.

Figure 18 is the block diagram representing the example being applicable to the action by some cycles measuring tempeature, its result being sent to bus in outside.

Figure 19 is the sequential chart of the action based on Figure 18.

Figure 20 is the control flow of measurement based on event link and communication operation.

To be control flow when the control of Figure 20 all being carried out with interrupt processing carry out as comparative example the process flow diagram that represents to Figure 21.

Figure 22 illustrates the block diagram by 3 figure places, the measured value of input voltage being carried out to Application Example when timing is lighted.

Figure 23 is the action timing diagram that the timing of Figure 23 is lighted.

Figure 24 is the control flow chart of above-mentioned measurement based on event link and display action.

To be control flow when the control of Figure 24 all being carried out with interrupt processing carry out as comparative example the process flow diagram that represents to Figure 25.

Figure 26 is the process flow diagram of the set action exemplifying event control information.

Figure 27 is the block diagram of the control device of an example as the control system employing microcomputer.

Figure 28 is the block diagram of the details of the control system exemplified centered by the microcomputer in the air conditioning control device of Figure 27.

Figure 29 is the process flow diagram exemplifying the control sequence that the indoor temperature according to the air-conditioning of event control information controls.

Figure 30 is the block diagram of the washing machine of an example as the control system employing microcomputer.

Figure 31 is the block diagram of the details of the control system exemplified centered by the microcomputer in the washing machine of Figure 30.

Figure 32 is the process flow diagram of the input control order exemplified according to the washing machine of event control information.

Figure 33 is the process flow diagram exemplified according to the Schema control of event control information and the control sequence of display excess time.

Embodiment

1. the summary of embodiment

First, embodiment representative in invention disclosed herein is briefly described.In the simple declaration for representational embodiment, be marked with bracket and only exemplify parts in the concept being included in the inscape indicating this label to the reference number in the accompanying drawing carrying out reference.

(1) digital processing unit of representational embodiment of the present invention, comprising: for exectorial central processing unit; The multiple circuit modules utilized by above-mentioned central processing unit; Interruptable controller, responds the event signal produced, carries out interrupt request to above-mentioned central processing unit; And event link controller, it responds the event signal produced, to a dynamic control signal of above-mentioned circuit module output services, wherein, foregoing circuit module can produce event signal, above-mentioned event link controller has rewritable memory circuit, and above-mentioned memory circuit stores the event control information playing dynamic control signal that will export for determining to respond above-mentioned event signal.Thereby, it is possible to by above-mentioned event store information specify event signal with associating, therefore, it is possible to control in order by the work of multiple circuit modules of this association defined between dynamic control signal.This is as the situation of interrupt processing, with based on central processing unit preservation or return process, do not need to adopt for the such control of the two priority classes of the interrupt request of competing yet.Therefore, it is possible to contribute to the high speed of data processing and alleviate the burden of central processing unit, the data-handling efficiency of entire system can be made to improve.More specifically, the high speed of the response can realize the parallelization of the process of each responding multiple event, event being produced and the burden of CPU alleviated when response events produces.

As a concrete embodiment, above-mentioned event control information can specify the corresponding of above-mentioned event signal and foregoing circuit module changeably, and above-mentioned event control information is the information can specifying selectable work in foregoing circuit module changeably.When circuit module has multiple working method, form while the stage can be had the event control information of the correspondence between the above-mentioned event signal of regulation and a dynamic control signal.

As the embodiment that another is concrete, comprise the non-volatile memory preserving above-mentioned event control information rewritably, above-mentioned memory circuit is the register from above-mentioned non-volatile memory input (load) above-mentioned event control information.Thereby, it is possible to easily carry out the initial setting of the event control information in the situations such as power-on reset.Because event control information can rewrite, therefore easily adopt the event control information corresponding to the system architecture applying data processor

As the embodiment that another is concrete, above-mentioned interruptable controller and event link controller have the event enable register preserved for determining the whether effective information of inputted event signal.Can use during identical event signal at above-mentioned interruptable controller and event link controller and easily avoid competition.

As the embodiment that another is concrete, above-mentioned interruptable controller and event link controller have the event enable register preserved for determining the whether effective information of inputted event signal.As one in above-mentioned multiple circuit module, there is the timer that can carry out counting action, comparison match action and input capture action, above-mentioned event link controller can export dynamic control signal according to above-mentioned event control information, this plays dynamic control signal and starts for making any one action in above-mentioned counting action, comparison match action and input capture action, above-mentioned timer can respond the generation of the spilling that caused by above-mentioned counting action or the generation of underflow, the generation of comparison match or input capture, and produces corresponding event signal.Special structure can not be adopted to timer, correspond to event link controller together with above-mentioned interruptable controller.

As the embodiment that another is concrete, as in foregoing circuit module, comprise and there is multiple A/D converter simulating signal being converted to the A/D ALT-CH alternate channel of digital signal, above-mentioned event link controller can according to above-mentioned event control information output any one dynamic control signal started for making in above-mentioned multiple A/D ALT-CH alternate channel, and above-mentioned A/D converter can respond completing and producing corresponding event signal of A/D conversion.Special structure can not be adopted to A/D converter, correspond to event link controller together with above-mentioned interruptable controller.

As the embodiment that another is concrete, as foregoing circuit module, comprise and have multiple D/A converter digital signal being converted to the D/A ALT-CH alternate channel of simulating signal, above-mentioned event link controller can according to above-mentioned event control information output any one dynamic control signal started for making in above-mentioned multiple D/A ALT-CH alternate channel.Special structure can not be adopted to D/A converter, correspond to event link controller together with above-mentioned interruptable controller.

" inputting from the event of outside " is as another concrete embodiment, as in foregoing circuit module, have multiple external interface end, said external interface end can respond the input state that is input to the external signal of predetermined outside terminal from the outside of data processor and produce corresponding event signal.Thus, can also from the outside incoming event signal of data processor.

" exporting to outside event ", as another concrete embodiment, above-mentioned event link controller can export for making the event signal dynamic control signal from the outside that predetermined outside terminal outputs to data processor exported from foregoing circuit module to above-mentioned external interface end according to above-mentioned event control information.Thereby, it is possible to the event signal produced in inside to be outputted to the outside of data processor.

" inputting based on the port of event synchronization " is as another concrete embodiment, as one of foregoing circuit module, have be connected to data processor outside terminal on and the external interface end of input and output action can be carried out, said external interface end has the interface register for storing input/output information, above-mentioned event link controller according to above-mentioned event control information, can export for making the information of above-mentioned interface register dynamic control signal from the outside that outside terminal outputs to data processor to above-mentioned external interface end.Thereby, it is possible to be synchronized with event signal at outside interface end just port input action.

" exporting based on the port of event synchronization " is as another concrete embodiment, above-mentioned event link controller can according to above-mentioned event control information, exports for making the information being supplied to outside terminal from the outside of data processor be input to dynamic control signal above-mentioned interface register to above-mentioned external interface end.Thereby, it is possible to be synchronized with event signal at outside interface end just port output action.

" event produce start with action associate " is as another concrete embodiment, above-mentioned event link controller accepts the first event signal from a circuit module and exports to play dynamic control signal for what make other circuit modules carry out predetermined work, and the second event signal accepted from other circuit modules above-mentioned and export and play dynamic control signal for what make other circuit module carry out predetermined work.Event easily can be made to produce according to the contents of event control information to be associated with the starting of circuit module.

As an example, above-mentioned event link controller accepts the first event signal from a circuit module and exports the first dynamic control signal for making data transfer to other circuit module to other circuit module, from other circuit module acceptance responses above-mentioned complete second event signal that data are transmitted and to other circuit module export for make above-mentioned data output to outside second dynamic control signal.

" position circulation exports " is as the object lesson of which, one in foregoing circuit module is timer, other circuit modules above-mentioned are data transfer control circuits, above-mentioned other circuit module is external interface end, above-mentioned first event signal is the time-out of response timer and the signal produced, and above-mentioned second event signal is that response data is transmitted and the signal produced.By applying this object lesson, the periodicity that can realize based on the data of position circulation exports side by side.Such as, above-mentioned event link controller carries out the output of above-mentioned the first dynamic control signal and the output of above-mentioned second dynamic control signal successively repeatedly, above-mentioned data transfer control circuit whenever the output repeating above-mentioned the first dynamic control signal just circulation switch connection object data successively, said external interface end just changes index position successively whenever the output repeating above-mentioned second dynamic control signal and outputs to outside by carrying out switching the parallel data changed.Such position circulation exports multiple scan enable signals etc. that can be applicable to key scanning.

As another example, one in foregoing circuit module is outer input interface circuit, other circuit modules above-mentioned are data transfer control circuits, above-mentioned other circuit module is outside output interface circuit, the signal that above-mentioned first event signal is completing of input action of response and produces, the signal that above-mentioned second event signal is completing of response data transmission and produces.Can produce according to this event and start associating of action, the measurement results such as the outer input interface inversion temperature that easy realization A/D converter is such, output to the association of the action of outside display device or control device from the outside output interface circuit that communication port is such by the numerical data after conversion.

(2) based on the data processor of another consideration aspect, comprising: for exectorial central processing unit; The multiple circuit modules utilized by above-mentioned central processing unit; Interruptable controller, responds the event signal produced, carries out interrupt request to above-mentioned central processing unit; And event link controller, it responds the event signal produced, play dynamic control signal to above-mentioned circuit module output services, above-mentioned event link controller produces above-mentioned dynamic control signal according to being defined as the above-mentioned event signal that can rewrite in memory circuit with corresponding between dynamic control signal.

As a concrete mode, above-mentioned memory circuit is the register that can be accessed by above-mentioned central processing unit, carries out initial setting by the power-on reset of data processor.

(3) based on the data processor of another consideration aspect, comprise for exectorial central processing unit, accept the first internal circuit of the control of above-mentioned central processing unit, second internal circuit and the 3rd internal circuit, above-mentioned first internal circuit is the interruptable controller responding the event signal that provided by above-mentioned second internal circuit or above-mentioned 3rd internal circuit and export interrupt request singal to above-mentioned central processing unit, above-mentioned second internal circuit is the event link controller responding the event signal that provided by above-mentioned first internal circuit or above-mentioned 3rd internal circuit and export for dynamic control signal above-mentioned 3rd internal circuit.Owing to having event link controller, carry out therefore, it is possible to parallel the process of each responding multiple event.For the response that event produces, event link controller is at a high speed compared with interruptable controller.This is owing to not needing the preservation of the register set carried out in central processing unit, returning the cause of process.And then, the burden of CPU when response events produces can be alleviated.

As a concrete mode, above-mentioned event link controller has to preserve rewritably and defines the memory circuit that play the event control information of dynamic control signal corresponding with above-mentioned event signal.Can programmably set the processing sequence employing event link controller.

As the mode that another is concrete, above-mentioned event link controller, when being provided event signal, exports the dynamic control signal corresponding with this event signal with reference to being stored in the event control information in memory circuit.Event link processor can control the required generation playing dynamic control signal by referring to the simple process that memory circuit is such.

(4) control system of representational embodiment of the present invention, comprise sensor, accept the output of the sensor and carry out the data processor of data processing, and based on above-mentioned data processor output and action is controlled by control circuit, above-mentioned data processor comprises for exectorial central processing unit, accept the first internal circuit of the control of above-mentioned central processing unit, second internal circuit and multiple 3rd internal circuit, above-mentioned first internal circuit is the interruptable controller responding the event signal that provided by above-mentioned second internal circuit or above-mentioned 3rd internal circuit and export interrupt request singal to above-mentioned central processing unit, above-mentioned second internal circuit responds the event signal that provided by above-mentioned first internal circuit or above-mentioned 3rd internal circuit and the event link controller of dynamic control signal exporting above-mentioned 3rd internal circuit for other, above-mentioned 3rd internal circuit comprises timer, A/D converter, RAM, data transfer control circuit, and external interface circuit, above-mentioned timer exports the first event signal and second event signal with the different time intervals respectively, above-mentioned A/D converter exports the 3rd event signal when A/D converts, above-mentioned data transfer control circuit exports the 4th event signal when the data transfer is complete, above-mentioned event link controller responds the first event signal and exports for making A/D converter carry out a dynamic control signal of A/D conversion to the output signal from the sensor, respond above-mentioned 3rd event signal to export and play dynamic control signal for what make data transfer control circuit the transformation result of A/D converter be transferred to RAM, respond the 4th event signal and play dynamic control signal to interruptable controller output for what indicate CPU the generation of the control data of the converting result data employed on RAM and this control data to the storage on RAM, and export for make data transfer control circuit externally interface circuit transmission RAM on control data and make external interface circuit to by control circuit export transmission come control data rise dynamic control signal, respond above-mentioned second event signal export for make data transfer control circuit externally interface circuit transmission RAM on control data and make external interface circuit to by control circuit export transmission come converting result data rise dynamic control signal.

By using interruptable controller and event link controller together, the detection signal of sensor can obtained, control data is generated based on this, the high speed of the response provide in the process of generated control data, realize the parallelization of the process of the multiple event of response, producing for event and alleviate the burden of CPU when response events produces.Therefore, it is possible to make the data-handling efficiency of entire system improve.

As a concrete mode, above-mentioned is above-mentioned first control data be used as the display device of display data and use the controller of above-mentioned converting result data by control circuit.

As mode more specifically, the first control data is Temperature displaying data, and converting result data is measuring tempeature data.

As mode more specifically, said temperature sensor is the temperature sensor of indoor apparatus of air conditioner and the temperature sensor of heat exchanger, Temperature displaying data are Temperature displaying data of room temperature, and above-mentioned measuring tempeature data are provided to the controller of the driving data for generating air-conditioner outdoor unit.

(5) based on the control system of another consideration aspect, comprise sensor, accept the output of the sensor and carry out the data processor of data processing, and based on above-mentioned data processor output and action is controlled by control circuit, above-mentioned data processor comprises for exectorial central processing unit, accept the first internal circuit of the control of above-mentioned central processing unit, second internal circuit and multiple 3rd internal circuit, above-mentioned first internal circuit is the interruptable controller responding the event signal that provided by above-mentioned second internal circuit or above-mentioned 3rd internal circuit and export interrupt request singal to above-mentioned central processing unit, above-mentioned second internal circuit responds the event signal that provided by above-mentioned first internal circuit or above-mentioned 3rd internal circuit and the event link controller of dynamic control signal exporting above-mentioned 3rd internal circuit for other, above-mentioned 3rd internal circuit comprises timer, A/D converter, RAM, data transfer control circuit, and external interface circuit, above-mentioned timer exports the first event signal and second event signal with the different time intervals respectively, said external interface circuit exports the 3rd event signal when the data from outside have inputted, above-mentioned data transfer control circuit exports the 4th event signal when the data transfer is complete, above-mentioned event link controller response the 3rd event signal and to event link controller export for make data transfer control circuit the data being input to external interface circuit from sensor are stored on RAM dynamic control signal, respond the 4th event signal and export the transmission being used to indicate the generation of the first control data of the data employed on RAM and this first control data externally interface circuit to interruptable controller, and be used to indicate the generation of the second control data of the count value that make use of timer and storage from this second control data to RAM play dynamic control signal, respond first event signal export for make data transfer control circuit by the second control data transmission on RAM to external interface circuit and make the second control data export to by control circuit rise dynamic control signal, response second event signal exports for making the first control data being transferred to external interface circuit output to by a dynamic control signal of control circuit.

As a concrete mode, above-mentioned is above-mentioned first control data be used as the display device of display data and above-mentioned second control data be used as the driving circuit of driving data by control circuit.

As mode more specifically, above-mentioned data are pivoting angle data of motor, and above-mentioned first control data is cumulative time data, and above-mentioned second control data is motor driving data.

(6) based on the control system of other consideration aspects, comprise key input apparatus, accept the output of above-mentioned key input apparatus and carry out the data processor of data processing, and based on above-mentioned data processor output and action is controlled by control circuit, above-mentioned data processor comprises for exectorial central processing unit, accept the first internal circuit of the control of above-mentioned central processing unit, second internal circuit and multiple 3rd internal circuit, above-mentioned first internal circuit is the interruptable controller responding the event signal that provided by above-mentioned second internal circuit or above-mentioned 3rd internal circuit and export interrupt request singal to above-mentioned central processing unit, above-mentioned second internal circuit responds the event signal that provided by above-mentioned first internal circuit or above-mentioned 3rd internal circuit and the event link controller of dynamic control signal exporting above-mentioned 3rd internal circuit for other, above-mentioned 3rd internal circuit comprises timer, A/D converter, RAM, data transfer control circuit, and external interface circuit, above-mentioned timer exports the first event signal with predetermined time interval, said external interface circuit exports second event signal when the data from outside have inputted, above-mentioned data transfer control circuit exports the 3rd event signal when the data transfer is complete, above-mentioned event link controller responds the first event signal and exports and is used for making data transfer control circuit key scanning data are transferred to external interface circuit, and make external interface circuit the key scanning data that transmission comes be outputted to a dynamic control signal of key input apparatus, response second event signal and the dynamic control signal that rises that exports for making data transfer control circuit the key input data of external interface circuit is transferred to RAM, respond the 3rd event signal and export for making CPU use the key input data of RAM to judge input data, and result of determination is outputted to by a dynamic control signal of control circuit by said external interface circuit.

Thus, by adopting interruptable controller and event link controller together, the data-handling efficiency of key input control can be made to improve.

2. the detailed content of embodiment

Describe embodiment in detail further.Below, describe in detail for implementing best mode of the present invention based on accompanying drawing.For illustration of in the whole accompanying drawing of the best mode carried out an invention, identical Reference numeral is marked to the component with identical function, omit its repeat specification.

Exemplified with the microcomputer of the present invention one example in Fig. 1.Microcomputer (MCU) 1 has for exectorial central processing unit (CPU) 2, Data Transmission Control Unit (DTC, data transfer control circuit) 3, RAM4, flash memory (FLASH) 5 and event link controller (ELC) 6.Although be not particularly limited, these circuit are connected on internal bus (IBUS) 7 jointly, and internal bus 7 is connected on peripheral bus (PBUS) 11 through bus state controller (BSC) 10.Peripheral bus 11 is connected with interruptable controller (INTC) 13, for simulating signal is converted to digital signal A/D converter (A/D) 14, for digital signal being converted to the D/A converter (D/A) 15 of simulating signal, serial communication interface circuit (SCI) 16, timer (TMR) 17, input/output port (PRT0 ~ PRT5) 18 ~ 23 and other circuit (MDL) 24.The analog input of the modulating output of A/D converter 14, D/A converter 15 can be made via input/output port 18 ~ 23 to receive the outside of microcomputer 1.System controller (SYSC) 25 inputs the mode of operation that reset signal RES or mode signal MD determines microcomputer.RAM4 has program, the data of preserving CPU2 in the perform region of CPU2, FLASH5 rewritably.

Although be not particularly limited, Data Transmission Control Unit 3, A/D converter 14, D/A converter 15, serial communication interface circuit 16, timer 17, input/output port 22 ~ 23 and other circuit 24 and correspondingly outgoing event signal EVT such as its duty or internal state etc.Event signal EVT is fed into interruptable controller 13 along a direction.In the drawings, the diagram of its feed path is eliminated.Interruptable controller 13 can judge interrupt priority level for inputted event signal EVT or interrupt mask level, sends interrupt request singal IRQ to the interrupt processing making central processing unit 2 perform response events.Event signal EVT is fed into event link controller 6 along other direction.Event link controller 6 is kept at register 30 by defining event control information ECI corresponding between event signal EVT with a dynamic control signal STR, when supplying event signal EVT, then event link controller 6 exports the dynamic control signal STR corresponding with its event signal EVT according to event control information ECI.Generation place of event signal EVT can be same circuit module with the supply target of a dynamic control signal STR, and also can be different circuit modules, its correspondence be defined by above-mentioned event control information ECI.Although be not particularly limited, interruptable controller 13 can corresponding to its duty to event link controller 6 outgoing event signal EVT.For convenience of explanation, outgoing event signal EVT or the circuit that inputted dynamic control signal STR are referred to as circuit module.

Above-mentioned flash memory 5 has the memory area 31 keeping above-mentioned event control information ECI rewritably, inputs above-mentioned event control information ECI at the register 30 of above-mentioned event link controller 6 from above-mentioned memory area 31.Such as CPU2 by event control information ECI being transferred to register 30 from memory area 31 by reset abnormality processing during power-on reset, thus carries out initial setting.Thereafter, CPU2 can rewrite event control information ECI.Because memory area 31 can rewrite, therefore, it is possible to easily set required event control information ECI according to the System's composition of using miniature computing machine 1.

The event that above-mentioned interruptable controller 13 has maintenance information ENBI plays dynamic register file 32, this information ENBI is for determining that whether inputted event signal is effective, the event that event link controller 6 has maintenance information ENBE plays dynamic register file 33, and this information ENBE is for determining that whether inputted event signal is effective.These two registers 32,33 are initialised in reset processing, but are not particularly limited, and can carry out setting thereafter change in privileged-mode etc. by CPU2.Thereby, it is possible to the starting alternatively producing the circuit module that the interruption undertaken by interruptable controller 13 controls or undertaken by event link controller 6 according to an event signal EVT controls, or, the parallel control produced both this can be carried out.Certainly, the interruption undertaken by interruptable controller 13 under same event signal can be avoided to control to control to compete with the starting of the circuit module undertaken by event link controller 6, and this is self-evident.

Fig. 2 schematically represents that the starting of the circuit module that the interruption undertaken by interruptable controller 13 controls and undertaken by event link controller 6 controls.Because producing the event signal EVT from circuit module (17,14,24), interrupt to CPU2 request from interruptable controller 13, CPU is made to perform corresponding interrupt handling routine, thus, use circuit module to realize the process of this event signal of response EVT.The CPU2 performing interrupt handling routine PGMi sets up its dynamic register file to the circuit module that will carry out work and starts this circuit module.On the other hand, because producing from the event signal EVT of circuit module, dynamic control signal STR from event link controller 6 utilizes and across-the-line starting responds the work of the circuit module of this event signal EVT, thus realize the process of this event signal of response EVT.The circuit module having accepted dynamic control signal STR is such as started by being set up it by dynamic control signal STR this and playing dynamic register file.By being carried out processing the process of starting response events and producing by event link controller 6, the high speed of the response produced for event can be realized, alleviate the burden of CPU when response events produces, and the easily parallel process responding multiple event respectively.If alleviate the burden of CPU for response events, then the allowance distribution that therefore CPU can be obtained is to other data processings, and result, can improve the data-handling efficiency of entire system.

Fig. 3 represent by the dynamic control signal object lesson of the groundwork of circuit module of specifying.The prime example of the event signal that Fig. 4 indication circuit module exports.

Timer 17 can carry out counting action, comparison match action and input capture action etc.When input corresponding play dynamic control signal time, start counting action, comparison match action and input capture action etc.The necessary starting condition of each work is initially set on the timer controller register of timer inside by CPU2.Such as, the initial setting counting added value when incremental count action will be carried out, when carrying out countdown, initial setting counts prefabricated value, the initial setting fiducial value when comparing coupling action, when carrying out input capture work, initial setting carries out the timing (rising edge timing, negative edge timing or these two timings) of the work of catching of paired pulses input.Timer exports corresponding event signal by producing spilling, underflow, comparison match and input capture.

A/D converter 14 represents the playing dynamic control signal of conversion beginning by input and starts A/D conversion, exportable event signal when A/D converts.D/A converter 15 represents the playing dynamic control signal of conversion beginning by input and starts D/A conversion.

By rising of starting of input service, dynamic control signal and starting sends with the data of outside SCI16, reception work, and export corresponding to being sent completely, finishing receiving, send that data empty, receive that data expire, the event signal of error of transmission etc.

The input/output port (ORT_OUT) 22,23 setting the action as output port utilizes externally terminal to carry out the playing dynamic control signal of signal output action and carries out the setting value externally data output action that exports of terminal or by the event of the inside externally event output action that exports of terminal.The input/output port (ORT_IN) 22,23 setting the action as input port carries out the event input action change of outside terminal inputted as event, the data input action change of outside terminal being write register.When input/output port 22,23 has been set the action as input port, response external event data action and produce event signal.

DTC3 response transmission plays dynamic control signal and data transmission from the transmitting control data of RAM reading pointer structure.When completing data transmission, export the event signal be transmitted.Transmitting control data is that CPU2 is stored in the presumptive area of RAM in advance by each data transmission channel.The start address of the storage area of the transmitting control data of each transmission channel be CPU2 in advance initial setting in the DTC controller register of DTC inside.

Interruptable controller 13 can respond the interrupt request and outgoing event signal EVT that produce CPU2.

Fig. 5 exemplifies event signal and the linking relationship playing dynamic control signal.Longitudinally enumerate the circuit module of outgoing event signal EVT, transversely enumerate the circuit module having inputted dynamic control signal (start event) STR.Watchdog timer (WDT), clock timer (RTC) is illustrated as the example of other circuit (MDL) 24 in Fig. 5.Such as, when responding the input service of input port (PORT_IN) and start the A/D conversion work of A/D converter 14, the foregone conclusion part signal EVT that input port (PORT_IN) is produced links (L1) for the dynamic control signal STR that rises starting conversion work with A/D converter.When the conversion work responding A/D converter 14 completes and makes output port (PRT_OUT) start output services, the event signal exported when the conversion work of A/D converter 14 completes is linked (L2) with indicating a dynamic control signal STR for output services to output port (PRT_OUT).As long as by the event signal EVT required for event control information ECI specifies with the linking (being also only expressed as event link) of dynamic control signal STR.As shown in Figure 5, the form of the link that can be specified by event control information ECI is arbitrary, when the data processing content that microcomputer 1 carries out changes, can replace event control information ECI and carry out reply process.Therefore, even if when the circuit module that microcomputer comprises creates change, forming the information of link by changing event control information ECI, the control of event link can be carried out by combination in any.

Fig. 6 exemplifies the control method of event control information to event link.At this, for by timer 17 be set as the input/output port 22 of input port (PRT_IN) and the situation of A/D converter 14 event link.The value " 1 " of event control information ECI represents makes the spilling event signal EVT_OF of timer 17 link with the conversion start control signal STR_AD of A/D converter, the value " 2 " of event control information ECI represents makes the comparison match event signal EVT_CM of timer 17 link with the conversion start control signal STR_AD of A/D converter, and the outside incoming event signal EVT_EI that value " 3 " expression of event control information ECI changes corresponding to the input of outside terminal Pi links with the conversion start control signal STR_AD of A/D converter.A/D converter accepts conversion start control signal STR_AD and carries out simulating signal to convert to the conversion process of digital signal.According to register 30 have 1,2,3 in which value as event control information ECI, cause selector switch 35 realizes the event link corresponding to its value.If ECI=1,3, then producing in any one situation of overflowing event signal EVT_OF or produce outside incoming event signal EVT_EI, all export the conversion start control signal STR_AD of A/D converter.Utilize the structure of above-mentioned selector switch and register etc., can corresponding to the output of the event signal of multiple circuit module, make any one circuit module event link, even if when multiple circuit module concurrent working, also can respond the event signal produced separately, and any one circuit module is started.

Fig. 7 illustrates another structure of event link controller 6.Event link controller 6 has traffic pilot (model choice circuit, link selection circuit, MPX) 36 and Action Selection circuit (OPRSL) 37.Link selection circuit 36 is incoming event signal EVT, determines the circuit with which circuit module linked by this signal.Action Selection circuit 37 be when exist multiple determine the starting reason of the circuit module of link, determine to start the circuit of reason because which is linked in, it exports one or more dynamic control signal STR.Use in the selection action of model choice circuit 36 value connecting set-up register (MDLREG) 38, use the value of operation setup register (OPRREG) 39 in the selection action of Action Selection circuit 37.CPU2 carries out the setting to register 38,39 in advance.

Fig. 8 is exemplified as the structure being connected to the part on A/D converter 14 and timer 17 of the more specifically structure of event link controller 6.

MDL0 ~ MDLi indication circuit module, EVT0 ~ EVTi presentation of events signal.The interrupt flag INT0 corresponding to an interruption source EVT0 and interruption starting mark ENBI0 is illustrated in interruptable controller 13.Interrupting starting mark ENBI0 is 1 that event plays dynamic register file 32.Also be same structure for other interruption sources.INTLOG is that the interruption carrying out response events according to interrupt priority level or interrupt mask level connects in check logical circuit.

Event link controller 6 has traffic pilot (MPX) 36a, 36b example as above-mentioned connection selection circuit 36.Traffic pilot 36a, 36b incoming event signal EVT0 ~ EVTi, selects a signal according to the value connecting set-up register (MDLREG) 38a, 38b from this incoming event signal.What the Action Selection circuit 37 of the signal selected by acceptance generated A/D change-over circuit 14 according to the value of action set-up register 39 plays dynamic control signal STRa, and generate timer 17 play dynamic control signal STRb_1, STRb_2.A dynamic control signal STRa of A/D change-over circuit 14 sets up the A/D conversion start mark ADS of dynamic register file.Thus, A/D conversion work is started.Rise dynamic control signal STRb_1, STRb_2 of timer 17 are fed into demultiplexer (DMPX) 40.In demultiplexer 40, above-mentioned signal STRb_1 is distributed to the starting instruction counting any operative in beginning, event count or event capturing by the dynamic control signal STRb_2 that rises of timer 17 according to its value.When have selected counting beginning, set up the counting beginning label CUNTS playing dynamic register file of timer.When have selected event count, produce event count commencing signal ECUNT.When have selected event capturing, produce event capturing commencing signal ICAP.TMLOG is the clock logic carrying out the timework such as counting action, comparison match and event capturing.Event plays dynamic register file 33 and utilizes its value to keep selecting to make the information ENBE that the output of traffic pilot 36a, 36b is invalid.

Fig. 9 is exemplified as the structure being linked at the part in input/output port 22 of the more specifically structure of event link controller 6.

Event link controller 6 has the example of traffic pilot 36c as above-mentioned connection selection circuit 36.Traffic pilot 36c incoming event signal EVT0 ~ EVTi, according to the value connecting set-up register 38c, selects a signal from this incoming event signal.The Action Selection circuit 37 of the signal selected by acceptance, according to the value of action set-up register 39, generates dynamic control signal STRc_1, STRc_2 of input/output port 22.Input/output control circuit (IOCONT) 41 is according to the input and output work of the value control inputs output port 22 of dynamic control signal STRc_1, STRc_2.Input/output control circuit (IOCONT) 41 is connected with input and output buffer circuit, port data register (PDR) 43, port data buffer register (PDBR) 44.Input and output buffer circuit 42 is combined with outside terminal P1 ~ P8.Determined whether input/output port 22 to be set to input service private port or to be set to output action private port or to be also used as the port of input and output or to make it invalid by the setting value of input and output control register (IOCREG) 45.CPU2 carries out the initial setting to this register.

In input/output control circuit 41, rise dynamic control signal STRc_1, STRc_2 of input/output port 22 are fed into demultiplexer (not shown).In demultiplexer, above-mentioned signal STRc_1 is distributed to the starting instruction of arbitrary action in data input, data output, external event input, the output of event outside by a dynamic control signal STRc_2 according to its value.When indicating starting data input action, as shown in Figure 10, the data of outside terminal P1 ~ P8 when being produced by the event signal of correspondence are taken into port data buffer register 44.When indicating starting data output action, as shown in figure 11, the data interconnects being stored in port data buffer register 44 in advance being transferred to port data register 43, exporting from outside terminal P1 ~ P8.This output timing is synchronous with the generation of corresponding event signal.When indicating start event input action, being designated at control register 45, by the outside terminal input signal of position, when its input state becomes predetermined state, event signal EVTm being outputted in the model choice circuit 36 representated by traffic pilot 36c.Thereby, it is possible to the event that input is outside.When indicating start event outside output action, therewith synchronously from pre-determined bit externally terminal output data.The input and output action form of data is not limited to above-mentioned, as shown in figure 12, also can be, position B1 ~ the B8 of inputoutput buffer 42 (corresponding with terminals P 1 ~ P8) is made in groups (GR1, GR2) according to the setting of control register 45, the generation of response events and with the fixed data organizing unit output logic value " 1 " or " 0 " or special pattern data, or make it trigger output.Can certainly response events generation and export the fixed signal of predetermined logic values " 1 " or " 0 " from specific single position.Also as group GR3, GR4, outside input and output action can be carried out to organize the different event signal of unit response.

Expression traffic pilot 36a, 36b are described as an example of foregoing circuit model choice circuit 36 in fig. 8, expression traffic pilot 36c is described as an example of foregoing circuit model choice circuit 36 in fig .9, but be not limited to above-mentioned, also can such as using the logic product result of multiple incoming event signal etc. as playing the formation condition of dynamic control signal or using trigger etc. the generation of multiple event order to be added on the formation condition of dynamic control signal.

Figure 13 presentation of events produces and the object lesson associated started to work.At this, the 1st program is performed to CPU2 and carries out using the situation of the particular procedure of circuit module MDL1 ~ MDL3 to be described.When CPU2 starts to perform the 1st program, first, after necessary initial setting is carried out to circuit module MDL1 ~ MDL3, circuit module MDL1 instruction is started working.When circuit module MDL1 completes predetermined work, produce event signal EVT_A.The event link controller 6 accepting this signal will play dynamic control signal STR_A according to event control information ECI and is supplied to circuit module MDL2 and this circuit module MDL2 is started working.When circuit module MDL2 completes predetermined work, produce event signal EVT_B.The event link controller 6 accepting this signal will play dynamic control signal STR_B according to event control information ECI and is supplied to circuit module MDL3 and starts working.Circuit module MDL3 produces event signal EVT_C when completing predetermined work.The interruptable controller 13 accepting this signal exports look-at-me IRQ to CPU2, and branch employs the process of another the second program of the working result of circuit module 3.

So, due to the association that can specify event signal according to event control information ECI and rise between dynamic control signal, therefore, it is possible to control the work of the multiple circuit module MDL1 ~ MDL3 specified by this association according to the order of sequence.This is as the situation of interrupt processing, with based on CPU2 preservation or return process, do not need to adopt for the such control of the two priority classes of the interrupt request of competing yet.As shown in the comparative example of Figure 14, when tackling with interrupt processing event signal EVT_A ~ EVT_C respectively, need based on CPU2 preservation or return process.Until interruptable controller 13 accepts to interrupt, must carry out the such control of the two priority classes of the interrupt request of competing, contrast with Figure 15 and learn, compared with event link (T1), need to spend the more time (T1 < < T2) to interrupt processing transfer (T2).Therefore, when using the event link of Figure 13, the high speed of data processing can be realized and alleviate the burden of CPU2, integrally can improve the data-handling efficiency of microcomputer 1.

Figure 16 represents that the position of input/output port rotates the example exported.By the control of CPU2, carry out for until send and stop instruction repeatedly carrying out the initial setting of timer operation to timer 17, and carry out rotating the transmission controlled condition of output pattern data and these data exported at RAM initial setting for position.When starting timer operation from CPU2 instruction, timer 17 is outgoing event signal EVT_A when each time-out.Event link controller 6 response events signal EVT_A provides dynamic control signal STR_A to DTC3 and has indicated it to start transmission data.Original date is transferred to input/output port 22 from RAM4 according to the data transmission conditions of RAM4 by DTC3.Event signal EVT_B is produced when being transmitted.Event link controller 6 response events signal EVT_B provide dynamic control signal STR_B to input/output port (PRT4) 22, makes this input/output port (PRT4) 22 externally these data of parallel output.Repeatedly carry out the above-mentioned work that timer 17 has carried out when having counted at every turn, within each time-count cycle, export parallel data from PRT22.In respectively repeatedly working, what periodically switch that DTC3 carries out in turn transmits to the data of PRT22 from RAM4.Such as, as shown in the sequential chart of Figure 17, when the parallel output data D1 ~ D4 of output 4, in the time-count cycle of each generation event signal EVT_A, the position, position of logical value " 1 " moves to the next bit of 1, circulates successively to most significant digit from lowest order.Be stored in port data buffer register (PDBR) 44 from the transmission data of RAM4 transmission, the generation of response events signal EVT_A, the data of port data buffer register (PDBR) 44 are transferred to the inside of port data register (PDR) 43 and export from outside terminal P1 ~ P4.Thereby, it is possible to the position obtained as Figure 17 is illustrative rotates output waveform.Position rotates the multiple scanning initiating signals etc. exporting and can be suitable for for key scanning.DTC3 is not limited to the structure can transmitting data according to the Data Transmission Controlling condition of RAM4, also can have multiple register for preserving Data Transmission Controlling condition, and can impose a condition according to it and carry out data transmission.

Figure 18 represents the Application Example being applicable to following work, namely measures peripheral (outside) temperature in each constant cycle and its result is sent to the work of peripherals.The terminal voltage of thermistor 50 is input to A/D converter, its transformation result is outputted to peripherals (EXDVC) 51 from SCI16.1st timing channel TCHN1 of work period use timer 17.The microcomputer 1 of Figure 18 and Fig. 1 is corresponding, but is a simplified bus connection etc. and is illustrated.By the control of CPU2 timer 17 set and is used for carrying out the initial setting of timing working in the schedule time, and to RAM4 initial setting necessary Data Transmission Controlling condition.When indicating from CPU2 during timing working, timer 17 uses timer passage TCHN1, the outgoing event signal EVT_A when each interrupts.Event link controller 6 response events signal EVT_A and provide dynamic control signal STR_A to A/D14, and the terminal voltage of thermistor 50 is converted to numerical data, after converting, outgoing event signal EVT_B.Event link controller 6 response events signal EVT_B and provide dynamic control signal STR_B to DTC3.The translation data of A/D14 is transferred to the data output register of SCI16 by DTC3 according to the Data Transmission Controlling condition of RAM4, after completing, and outgoing event signal EVT_C.Event link controller 6 couples of SCI16 provide and have transmitted dynamic control signal STR_C, the data peripheral device 51 of data output register are exported.After transmission, interrupt from SCI16 request, thus again set above-mentioned timer operation, repeatedly carry out above-mentioned work.As shown in figure 19, carry out this work at each timing cycle, thus, peripherals 51 can obtain at each timing cycle (CYCL) temperature measuring data that thermistor 50 records.By being stopped completing this work to the timer operation of timer passage TCHN1 by CPU2.Figure 20 represents the control flow of above-mentioned measurement based on event link and communication work.Figure 21 represents control flow when all carrying out this control with interrupt processing as comparative example.As described above, if use case link, then compared with interrupt mode, the software processing time at CPU place is shorter, also less to the burden of CPU2.During being undertaken controlling by event link controller, CPU2 can perform other software process, thus effectively can utilize hardware resource.

Figure 22 represents the Application Example be applied to by the measured value of input voltage with during the 3 dynamic bright light of figure place.TB1 ~ TB3 is the three-state buffer of 8 respectively, and DD1 ~ DD3 is the display device by 7 joint display 1 bit digital respectively.The DATA IN terminal of three-state buffer TB1 ~ TB3 jointly exports with 8 of PRT22 and links, and the control terminal of three-state buffer TB1 ~ TB3 separately links with the lead-out terminal of PRT23.In this work, by CPU2, port PRTA22, PRT23 initial setting is used for the Static output pattern of the locked data of Static output port data register PDR.To the Data Transmission Controlling condition of RAM4 initial setting necessity and the control data from PRT23 output.When starting timing working from CPU2 instruction, timer 17 is outgoing event signal EVT_A when timing channel TCHN1 becomes interruption.Event link controller 6 response events signal EVT_A and provide dynamic control signal STR_A to A/D14, and input voltage vin is converted to numerical data, after converting, outgoing event signal EVT_B.Interruptable controller 13 response events signal EVT_B exports look-at-me IRQ to CPU2.CPU2 responds its interruption source, generates and represents that 3 row of input voltage vin value show data VH, VM, VL, and these display data are stored in the regulation region of RAM4 based on A/D converting result data.The time-count cycle of timing channel TCHN1 is such as 500msec.Timer 17 is outgoing event signal EVT_C when counting channel TCHN2 becomes interruption.Event link controller 6 response events signal EVT_C and provide dynamic control signal STR_C to DTC3.DTC3 specifies the port data register of the display data transmissions in region to PRT22 according to the Data Transmission Controlling condition of RAM4 by being stored in RAM4, tri-state control data is transferred to the buffered data register of PRT23.Within the timer period of each timing channel TCHN2, repeatedly carry out this work, but each transmitted display data and tri-state control data different on each figure place showing.Such as shown in figure 23, it is low level period in the output control data of terminals P 20, the display data VH of display most significant digit number, it is low level period in the output control data of terminals P 21, the display data VM of figure place in the middle of display, be low level period in the output control data of terminals P 22, the display data VL of display lowest order digit.

Figure 24 represent based on event link above-mentioned measurement and display work control flow.Figure 25 represents control flow when all carrying out this control with interrupt processing as comparative example.As described above, if use case link, then compared with interrupt mode, the processing time is shorter, also less to the burden of CPU2.

The setting workflow of Figure 26 presentation of events control information ECI.Event control information ECI responds power-on reset and carries out initial setting by CPU2.In setting work, event link work can not be carried out.Thereafter, by the control of CPU2, event link work can be stopped, again set event control information ECI.To not carry out event link work, as long as the starting of register 33 mark ENBE is resetted, namely sets it to and forbid level.

Figure 27 represents that the control system employing microcomputer 1 is aircondition.Aircondition roughly divide into be configured at indoor 108 indoor set (INUNT) 100 and be configured at outdoor off-premises station (OUTNT) 110, indoor set 100 and off-premises station 110 are connected by refrigerant circulation pipe (CRCLPIP) 121 and serial communication cable (SCICBL) 120.

Indoor set 100 has heat interchanger 101, blowing fan 102, heat exchange temperature sensor 103, temperature sensor 104, indoor temperature display 105 and control panel 106.Control panel 106 is provided with above-mentioned microcomputer 1 and impact damper or driver and power circuit etc. for this microcomputer 1 being connected to external device (ED).

Off-premises station 110 having control panel 111, compressor 114, heat interchanger 113 and sending out the hot fan 112, being provided with on control panel 111 as the microcomputer 1A of controller and impact damper or driver and the power circuit etc. for this microcomputer being connected to external device (ED).Above-mentioned microcomputer 1 can be adopted to microcomputer 1A.

Between off-premises station 110 and indoor set 100, the refrigerant gas of heat exchange utilizes pipe 121 and circulates, and between microcomputer 1 and 1A, uses serial cable 120 to communicate.

The summary that indoor temperature controls below is described.Carry out the temperature setting operation of indoor set 100 with telepilot, its operation information is imported into microcomputer 1.Microcomputer 1 controls as follows: by being installed on temperature sensor 103,104 on indoor set 100 and the temperature of 108 and the temperature of heat interchanger 101 in measuring chamber, and be shown in the temperature indicator 105 of indoor set 100.The set temperature value set based on telepilot, Indoor Temperature angle value and heat exchange temperature value are sent to the microcomputer 1A of off-premises station 110 by microcomputer 1 through serial cable 120.The microcomputer 1A of off-premises station 110 is used for the compressor 114 of compression refrigerant gas and the fan 112 for heat extraction based on reception Data Control, thus carrys out the room temperature of in pulpit 108 through heat interchanger 113.

Figure 28, centered by microcomputer 1, represents the details of its control system.Communication port (SCI_1, SCI_2) 16_1,16_2 that the communication port that serial communication interface circuit 16 illustrates remote control respectively communicates with off-premises station.A/D14 has the A/D ALT-CH alternate channel of temperature sensor and the A/D ALT-CH alternate channel of heat exchange temperature sensor respectively, and microcomputer 1, except interruptable controller 13, also has event link controller 6.Event control information (ECI) 30_1 shown in Figure 28 defines the event signal controlled for air-conditioner temperature and the information playing relation between dynamic control signal, such as, be initially set in power-on reset process.

Figure 29 represents temperature controlled control sequence in the air conditioning chamber according to event control information 30_1.According to the initial setting of CPU2, timer 17 produces event signal EVT_1 with the interval of 500 milliseconds (msec), produces event signal EVT_2 with the interval of 3msec.

The indoor temperature of air-conditioning controls the process roughly divided into centered by the interrupt processing of CPU2 and the process centered by the event link of ELC6.

When EVT_1 is input to ELC6, A/D14 carries out A/D conversion (S1) based on initiating signal STR_1 to the output signal from the sensor 103,104, after converting, and A/D14 outgoing event signal EVT_3 (S2).When event signal EVT_3 is input to ELC6, the transformation result after A/D14 conversion is transferred to RAM4 based on initiating signal STR_3 by DTC3, after converting, and outgoing event signal EVT_4 (S3).

When EVT_4 is input to ELC6, based on the requested interruption of initiating signal STR_4, INTC13.INTC13 responds it and interrupts and provide look-at-me IRQ to CPU2, starts the interrupt processing based on corresponding reason.In interrupt processing in this case, generate Temperature displaying data etc. based on translation data, the Temperature displaying data of generation and converting result data are together stored in RAM (S4).The converting result data being stored in RAM is sent to through SCI_2 in outdoor microcomputer (S5).When this interrupt processing completes, CPU returns to the state before this interruption generation.Also can recover from interrupt processing when the process completing step S4.In this case, as long as the process of step S5 is response produces other event signal to ELC6.Namely, as long as such as follows, the most backward ELC6 outgoing event signal EVT_5 of CPU2 disconnected process wherein, utilize the initiating signal STR_5 responded therewith, converting result data transmits to SCI_2 by DTC3, be transmitted with this and synchronously event signal EVT_6 outputted to ELC6, utilize the dynamic control signal STR_6 that rises responded therewith to export converting result data from SCI_2.

On the other hand, when inputting EVT_2 to ELC6, by initiating signal STR_2, Temperature displaying data on RAM are sent to the PDBR of port (PRT1) 19 by DTC3, completing with its transmission synchronously makes event signal EVT_7 output in ELC6, by responding its a dynamic control signal STR_7, port (PRT1) 19 output temperature represents data (S6).Similarly, when inputting EVT_2 to ELC6, by initiating signal STR_8, next figure place display and control data on RAM are sent to the PDBR of port (RPT2) 20 by DTC3, completing with its transmission synchronously makes event signal EVT_9 output to ELC6, by responding its a dynamic control signal STR_9, port (RPT2) 20 carry-out bit digital display shows control data (S7).The room temperature display and control of step S6, S7 be carry out exposing with the dynamic point of Figure 22 and long number illustrated in fig. 23 with display and control.

When SCI_1 receives the data sent by remote-control data, interrupt to CPU2 request, it receives data and is stored in (S8) in RAM.

According to above-mentioned aircondition, by adopting INTC13 and ELC6 simultaneously, temperature data (converting result data) is obtained from the output of sensor 103,104, Temperature displaying data are being generated according to this temperature data, when the process of generated temperature data, Temperature displaying data is provided, the parallelization of the process responding multiple event, high speed to the response of the generation of event can be realized, and the burden of CPU2 when can realize the generation alleviating response events.Therefore, it is possible to improve the data-handling efficiency of aircondition entirety.

In fig. 30, washing machine is illustrated as the control system employing microcomputer 1.Washing machine 120 comprises selects cylinder 121, brushless direct current motor (MTR) 122, multiple level sensor 123, console panel 124, display 125, the input switch 126 with key battle array (KYMTRX), fillup valve 128, draining valve 129 and lid 130.Console panel 124 is provided with above-mentioned microcomputer 1, for connecting the impact damper of this microcomputer 1, the driver of motor 122 and power circuit etc. on sensor 123.

The summary controlled based on the washing of washing machine 120 is as follows.By switch 126 set wash conditions (wash time, with or without dehydration, with or without drying etc.).Microcomputer 1 is according to set content-control washing state.That is, when pressing washing and starting switch, start washing and control.First, open water injection valve 128, start shutoff valve 128 when washing drum arrives predetermined water level, make motor 122 start the rotary actuation rotated.Until after a predetermined time, motor 122 is utilized repeatedly to carry out the rotating forward of washing drum 121, the action of reversion.Therebetween, on display 125 display until excess time of having washed.

In Figure 31, centered by microcomputer 1, the details of its control system is shown.2 of port (PRT1) 19 and port (PRT2) 20 are used in dynamically lighting of display 125.The rotor rotation position signal (PSTD) of 3 input motor 122 of port (PRT2) 20.Port (PRT3) 21 inputs the drive singal (SPND) of motor 122.Port (PRT4) 22 carries out the input of output for the key scanning data (KYSCN) of the key battle array of input switch 126 and key input data (KYIPT).As mentioned above, microcomputer 1 also has event link controller 6 except interruptable controller 13.Event control information (ECI_1) 30_2 shown in Figure 31 be define washing machine for washing the event signal of control and playing the information of relation of dynamic control signal, such as in power-on-reset process, carry out initial setting by CPU2 etc.

In Figure 32, illustrate the input control order according to event control information 30_2.According to the initial setting of CPU2, timer 17 produces event signal EVT_11 with the interval of 5 milliseconds (mSec).

Input control is roughly divided into the process centered by the interrupt processing of CPU2 and the process centered by event link based on ELC6.

When inputting EVT_11 to EVC6, by initiating signal STR_11, key scanning data are sent to the PDBR of PRT4 by DTC3, event signal EVT_14 is synchronously made to output to ELC6 with its transmission, by rise dynamic control signal STR_14, the PRT4 that respond it, key scanning data are outputted to input media 126 (S11).In addition, response input change, event signal EVT_15 is outputted to ELC6 by PRT4, by rise dynamic control signal STR_15, the DTC3 responding it, the key input data of PRT4 is sent to (S12) in RAM4.Event signal EVT_16 is outputted to ELC6 by DTC3 after transfer is completed, responds this signal, and ELC6 has passed through dynamic control signal STR_16 to be asked to interrupt to interruptable controller 13.INTC13 responds this interruption and sends look-at-me IRQ to CPU2, starts the interrupt processing of the reason according to correspondence.In interrupt processing at this moment, set the mode of operation (S13) of washing machine according to the key input data be stored in RAM4.Washing machine is started working according to set mode of operation.

In fig. 33, the control sequence according to the Schema control of event control information 30_2 and display excess time when specifying washing machine mode of operation is illustrated.According to the initial setting of CPU2, timer 17 produces event signal EVT_12 with the interval of 10 milliseconds (mSec), produces event signal EVT_13 with the interval of 3 milliseconds (mSec).

Response is input to the change of the rotor rotation position signal (PSTD) in PRT2, event signal EVT_17 is input to ELC6 by PRT2, by rise dynamic control signal STR_17, the DTC3 that respond it, the rotor rotation position signal of PRT4 is sent to (S14) in RAM4.And then event signal EVT_18 is outputted to ELC6 by DTC3 after transfer is completed, respond this signal, ELC6 has passed through dynamic control signal STR_18 to be asked to interrupt to interruptable controller 13.INTC13 responds this interruption and sends look-at-me IRQ to CPU2, starts the interrupt processing of the essential factor according to correspondence.In interrupt processing at this moment, according to the rotor rotation position signal (PSTD) be stored in RAM4, calculate next motor drive signal (SPND), and be stored in the PDBR of PRT3.And then, according to start through time action the count value of timer 17, to calculate from washing until the excess time of having washed, data excess time be stored into (S15) in RAM4.When completing predetermined interrupt processing, the process of CPU2 turns back to the process before this interrupt processing.

When inputting EVT_12 to ELC6, by rise dynamic control signal STR_12, the PRT3_21 responding it, the motor drive signal (SPND) of PDBR is outputted to motor 122 (S16).

On the other hand, when inputting EVT_12 to ELC6, by initiating signal STR_12, data excess time on RAM are sent to the PDBR of port (PRT1) 19 by DTC3, event signal EVT_19 is synchronously made to output in ELC6 with its transmission, by responding its a dynamic control signal STR_19, port (PRT1) 19 exports data excess time (S17).When inputting EVT_13 to ELC6, by initiating signal STR_13, next figure place display and control data on RAM are sent to the PDBR of port (RPT2) 20 by DTC3, completing with its transmission synchronously makes event signal EVT_20 output to ELC6, by responding its a dynamic control signal STR_20, port (RPT2) 20 carry-out bit digital display shows control data (S18).Display and control excess time of step S17, S18 be carry out exposing with the dynamic point of Figure 22 and long number illustrated in fig. 23 with display and control.

According to above-mentioned washing machine, by adopting INTC13 and ELC6 simultaneously, obtain rotor-position detection signal, next motor driving data is generated according to this signal, there is provided generated motor driving data, excess time when showing data in process, the parallelization of the process responding multiple event, high speed to the response of the generation of event can be realized, and the burden of CPU2 when can realize the generation alleviating response events.Therefore, it is possible to improve the data-handling efficiency of washing machine entirety.By adopting INTC13 and ELC6 simultaneously, the data-handling efficiency of key input control can be improved.

Above, specifically illustrate the invention completed by the present inventor according to embodiment, but the present invention is not limited thereto, in the scope not exceeding its purport, certainly can carry out various change.

Such as, be not limited to microcomputer, also can apply microprocessor, data processor etc.

Such as, the content etc. of the kind of circuit module, the bus structure of microcomputer, the kind of the event of circuit module output, the action of response starting instruction can suitably be changed.

Claims

1. a data processor, comprising:

For exectorial central processing unit;

The multiple circuit modules utilized by above-mentioned central processing unit respectively;

Response is exported the interruptable controller of interrupt request singal to above-mentioned central processing unit by an event signal produced in above-mentioned multiple circuit module;

Be kept for the effective or invalid first information determining above-mentioned event signal, when the above-mentioned first information represents invalid, make first register invalid to the above-mentioned event signal of above-mentioned interruptable controller;

Respond above-mentioned event signal and exported the event link controller of dynamic control signal to any one of above-mentioned multiple circuit module; And

Be kept for the second effective or invalid information determining above-mentioned event signal, make second register invalid to the above-mentioned event signal of above-mentioned event link controller when above-mentioned second information represents invalid.

2. data processor according to claim 1, is characterized in that:

Above-mentioned event link controller has memory circuit, and this memory circuit can keep the event control information defined a dynamic control signal corresponding with above-mentioned event signal rewritably.

3. data processor according to claim 1, is characterized in that:

Above-mentioned event link controller, when being supplied to above-mentioned event signal, based on the above-mentioned event control information be stored in above-mentioned memory circuit, exports the dynamic control signal corresponding with above-mentioned event signal.

4. data processor according to claim 1, is characterized in that:

Above-mentioned first register and above-mentioned second register are initialised in reset processing, can carry out set information by above-mentioned central processing unit.

5. data processor according to claim 1, is characterized in that:

Above-mentioned event link controller also has:

Connect selection circuit, this connection selection circuit selects in above-mentioned multiple circuit module, to accept above-mentioned dynamic control signal foregoing circuit module; With

Action Selection circuit, above-mentioned starting reason in multiple starting reasons of the circuit module selected by the selection of this Action Selection circuit, that make above-mentioned dynamic control signal link.

6. data processor according to claim 5, is characterized in that:

Above-mentioned connection selection circuit has the logical operation of carrying out multiple event signal and the result of above-mentioned logical operation is outputted to the circuit of above-mentioned Action Selection circuit, wherein, above-mentioned multiple event signal comprises the first event signal and second event signal that input from above-mentioned multiple circuit module.

7. data processor according to claim 5, is characterized in that:

Above-mentioned connection selection circuit has trigger circuit, and these trigger circuit are transfused to multiple event signal, and the plurality of event signal comprises the first event signal and second event signal that input from above-mentioned multiple circuit module.

8. a data processor, comprising:

For exectorial central processing unit;

The multiple circuit modules utilized by above-mentioned central processing unit;

The interruptable controller of interrupt request is carried out in response to above-mentioned central processing unit by an event signal produced in above-mentioned multiple circuit module; And

Respond above-mentioned event signal and play the event link controller of dynamic control signal to above-mentioned circuit module output services, wherein, above-mentioned event link controller has rewritable memory circuit,

Above-mentioned memory circuit stores the event control information playing dynamic control signal that will export for determining to respond above-mentioned event signal,

As in foregoing circuit module, there is the timer that can carry out counting action, comparison match action and input capture action,

Above-mentioned event link controller can export dynamic control signal according to above-mentioned event control information, and this plays dynamic control signal and starts for making any one action in above-mentioned counting action, comparison match action and input capture action,

Above-mentioned timer can respond the generation of spilling or the underflow caused by above-mentioned counting action, the generation of comparison match or the generation of input capture and produce corresponding event signal.

9. a data processor, comprising:

For exectorial central processing unit;

As foregoing circuit module, have and comprise multiple D/A converter digital signal being converted to the D/A ALT-CH alternate channel of simulating signal,

Above-mentioned event link controller can according to above-mentioned event control information export for make in above-mentioned multiple D/A ALT-CH alternate channel any one start rise dynamic control signal.

10. a data processor, comprising:

For exectorial central processing unit;

To have as one of foregoing circuit module on the outside terminal being connected to data processor and the external interface end of input and output action can be carried out,

Said external interface end has the interface register for storing input/output information,

Above-mentioned event link controller according to above-mentioned event control information, can export for making the information of above-mentioned interface register dynamic control signal from the outside that outside terminal outputs to data processor to above-mentioned external interface end.

11. data processors according to claim 10, is characterized in that:

Above-mentioned event link controller can according to above-mentioned event control information, exports for making the information being supplied to outside terminal from the outside of data processor be input to dynamic control signal above-mentioned interface register to above-mentioned external interface end.

12. 1 kinds of data processors, comprising:

For exectorial central processing unit;

Above-mentioned event link controller accepts the first event signal from a circuit module and exports the dynamic control signal for making other circuit modules carry out predetermined work, and accept from other circuit modules above-mentioned second event signal and export for make other circuit module carry out predetermined work rise dynamic control signal

One in foregoing circuit module is outer input interface circuit, and other circuit modules above-mentioned are data transfer control circuits, and above-mentioned other circuit module is outside output interface circuit,

The signal that above-mentioned first event signal is completing of input action of response and produces,

The signal that above-mentioned second event signal is completing of response data transmission and produces.

13. 1 kinds of data processors, comprising:

For exectorial central processing unit;

Above-mentioned event link controller accepts the first event signal from a circuit module and exports the first dynamic control signal for making data transfer to other circuit module to other circuit modules, and complete from other circuit module acceptance responses above-mentioned second event signal that data are transmitted and export to other circuit module for make above-mentioned data output to outside second dynamic control signal.

14. data processors according to claim 13, is characterized in that:

One in foregoing circuit module is timer, and other circuit modules above-mentioned are data transfer control circuits, and above-mentioned other circuit module is external interface end,

Above-mentioned first event signal is the time-out of response timer and the signal produced,

Above-mentioned second event signal is that response data is transmitted and the signal produced.

15. data processors according to claim 14, is characterized in that:

Above-mentioned event link controller carries out the output of above-mentioned the first dynamic control signal and the output of above-mentioned second dynamic control signal successively repeatedly, above-mentioned data transfer control circuit whenever the output repeating above-mentioned the first dynamic control signal just circulation switch connection object data successively, said external interface end just changes index position successively whenever the output repeating above-mentioned second dynamic control signal and outputs to outside by carrying out switching the parallel data changed.