CN102623049B - Nonvolatile memory cell and data programming, reading and erasure method thereof - Google Patents
Nonvolatile memory cell and data programming, reading and erasure method thereof Download PDFInfo
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- CN102623049B CN102623049B CN201110030444.6A CN201110030444A CN102623049B CN 102623049 B CN102623049 B CN 102623049B CN 201110030444 A CN201110030444 A CN 201110030444A CN 102623049 B CN102623049 B CN 102623049B
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Abstract
The invention discloses a nonvolatile memory cell and a data programming, reading and erasure method thereof. The nonvolatile memory cell comprises a first transistor and a second transistor, wherein the first transistor comprises a first drain electrode, a first source electrode, a first grid electrode and a first substrate; the second transistor comprises a second drain electrode, a second source electrode, a second grid electrode and a second substrate; the first drain electrode of the first transistor is connected to a bit line; the second drain electrode of the second transistor has a reverse connection with the bit line; the first grid electrode of the first transistor and the second grid electrode of the second transistor are connected to a word line; the first source electrode of the first transistor is connected to a first source line; the second source electrode of the second transistor is connected to a second source line; and the first substrate of the first transistor and the second substrate of the second transistor are connected to a substrate line. The nonvolatile memory cell is completely compatible with the existing logical technology, especially with a deep submicron logical technology, and has a memory cell area which can be reduced with reduction of the minimum processing size of a logical technology.
Description
Technical field
The present invention relates generally to semiconductor storage unit, particularly relates to a kind of non-volatile memory cells and data programing thereof, reading, method for deleting.
Background technology
Nonvolatile memory chip is widely used in electronic product, computing machine, communication device, consumer electronics and other application needing data power down to preserve.Nonvolatile memory comprises polytype, and wherein, the types such as EPROM, flash memory (Flash Memory) all have programming and erase function.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of non-volatile memory cells and data programing thereof, reading, method for deleting, itself and existing logic process especially deep-submicron logic process are completely compatible, and the area of storage unit can reducing and reduce with technique.
According to an aspect of the present invention, provide a kind of non-volatile memory cells, comprising:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds.
According to a feature of the present invention,
First, second transistor described comprises:
First heavily doped region, the second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, the first side wall, the second side wall and silicon oxide layer; Wherein,
Described silicon oxide layer is positioned on described substrate;
Described polysilicon layer, described first side wall, described second side wall are all positioned on described silicon oxide layer;
Described first side wall, described second side wall lay respectively at the both sides of described polysilicon layer;
Described asymmetric light doping section is adjacent to described second heavily doped region and described silicon oxide layer.
According to another feature of the present invention,
Described first side wall, is positioned on first, second drain electrode described, for stored charge.
According to another feature of the present invention,
The thickness of described silicon oxide layer equals the thickness of the silicon oxide layer of the thick grid oxygen transistor under standard semiconductor logic process.
According to a further aspect in the invention, provide a kind of programmed method of non-volatile memory cells, wherein,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described programmed method comprises:
Wordline applies word line programming voltage;
Bit line applies bitline programming voltage;
The anti-program voltage of bit line is applied on bit line is anti-;
First source line applies the first source line program voltage;
Second source line applies the second source line program voltage;
Substrate lines applies substrate lines program voltage.
According to a feature of the present invention,
Preliminary setting data storage rule, to programme to described non-volatile memory cells according to data storage rule and realizes the storage of data.
According to another feature of the present invention,
Only the first transistor programming of described non-volatile memory cells is represented and store data " 1 ", only the transistor seconds programming of described non-volatile memory cells is represented and store data " 0 "; Or
Only the first transistor programming of described non-volatile memory cells is represented and store data " 0 ", only the transistor seconds programming of described non-volatile memory cells is represented and store data " 1 ".
According to another feature of the present invention,
On current between the first transistor of programming or the source-drain electrode of transistor seconds is less than initial turn-on electric current;
Initial turn-on electric current is equaled without the On current between the first transistor of programming or the source-drain electrode of transistor seconds.
According to a further aspect in the invention, provide a kind of read method of non-volatile memory cells, wherein,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described read method comprises:
Wordline applies word line read voltage;
Bit line applies bit line and reads voltage;
Bit line backward read power taking pressure is applied on bit line is anti-;
First source line applies the first source line and reads voltage;
Second source line applies the second source line and reads voltage;
Substrate lines applies substrate lines and reads voltage; Wherein,
By detect the first transistor, transistor seconds source-drain electrode between On current, determine the data stored in non-volatile memory cells.
According to a further aspect in the invention, provide a kind of method for deleting of non-volatile memory cells, wherein,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described method for deleting comprises:
Wordline applies word line erase voltage;
Bit line applies bit line erase voltage;
The anti-erasing voltage of bit line is applied on bit line is anti-;
First source line applies the first source line erasing voltage;
Second source line applies the second source line erasing voltage;
Substrate lines applies substrate lines erasing voltage; Wherein,
On current between the first transistor of erasing or the source-drain electrode of transistor seconds equals initial turn-on electric current.
Non-volatile memory cells of the present invention and data programing thereof, reading, method for deleting, completely compatible with existing logic process especially deep-submicron logic process, the area of the non-volatile memory cells in the present invention can reducing and reduce with existing logic process.Non-volatile memory cells in the present invention utilizes the side wall stored charge of the transistor of asymmetric light doping section, by control the stored charge of side wall number carry out control store unit source-drain electrode between conducting resistance, with the On current between the source-drain electrode changing the transistor in storage unit, thus can determine by the difference of the On current between the source-drain electrode that compares multiple transistors of storage unit the data that store.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the standard thick grid oxygen transistor of logic-based technique;
Fig. 2 is the structural drawing as the transistor of non-volatile memory cells in the embodiment of the present invention;
Fig. 3 is the structural drawing of non-volatile memory cells in the embodiment of the present invention;
Fig. 4 A, 4B are the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to data programing;
Fig. 5 is the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to digital independent;
Fig. 6 A, 6B are the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to data erase.
Embodiment
Specific embodiments of the invention are described in detail below in conjunction with accompanying drawing.
Fig. 1 is the structural drawing of the standard thick grid oxygen transistor of logic-based technique, and in Fig. 1, standard thick grid oxygen transistor comprises:
First heavily doped region 102, heavily doped region 101, second, polysilicon layer 103, substrate 104, first light doping section 105, second light doping section 106, first side wall 107, second side wall 108 and silicon oxide layer 109.
According to Fig. 1, standard thick grid oxygen transistor comprises the first symmetrical light doping section 106, light doping section 105, second.Wherein, the first heavily doped region, heavily doped region 101, second 102 is N-type heavily doped region, and substrate 104 is P type trap.Standard thick grid oxygen transistor in logic process for realizing imput output circuit.Under the semiconductor fabrication process of 0.13 micron, the thickness of the silicon oxide layer 109 of standard thick grid oxygen transistor is generally 6-8 nanometer.Under different semiconductor fabrication process, the thickness of the silicon oxide layer 109 of standard thick grid oxygen transistor is also different.
Fig. 2 is the structural drawing as the transistor of non-volatile memory cells in the embodiment of the present invention, and in Fig. 2, the transistor as non-volatile memory cells in the embodiment of the present invention comprises:
First heavily doped region 202, heavily doped region 201, second, polysilicon layer 203, substrate 204, light doping section 205, first side wall 206, second side wall 207 and silicon oxide layer 208.Wherein,
Silicon oxide layer 208 is positioned on substrate 204;
Polysilicon layer 203, first side wall 206, second side wall 207 is all positioned on silicon oxide layer 208;
First side wall 206, second side wall 207 lays respectively at the both sides of polysilicon layer 203;
Light doping section 205 is adjacent to the second heavily doped region 202 and silicon oxide layer 208.
The thickness of silicon oxide layer 208 equals the thickness of the silicon oxide layer of the thick grid oxide layer transistor under standard semiconductor logic process.
According to Fig. 3, in the embodiment of the present invention, only comprise light doping section 205 as the transistor of non-volatile memory cells, belong to asymmetric light doping section transistor npn npn.
Be arranged at as the storage area of the transistor of non-volatile memory cells the first side wall 206 place not having light doping section using in the embodiment of the present invention, namely the first side wall 206 stored charge is adopted, conducting resistance between the charge number stored by controlling the first side wall 206 controls as the source-drain electrode of the transistor of non-volatile memory cells, with the On current size between the source-drain electrode changing the transistor of non-volatile memory cells, thus the data that store can be determined according to the On current size between the source-drain electrode of the transistor of non-volatile memory cells.
Pass through to use asymmetric light doping section as the transistor of non-volatile memory cells in the embodiment of the present invention, not only reduce program erase voltage, and improve program erase speed.
Fig. 3 is the structural drawing of non-volatile memory cells in the embodiment of the present invention, in Fig. 3, comprises the first transistor 1 and transistor seconds 2, and wherein, the first transistor 1 comprises the first drain D 1, first source S 1, first grid G1 and the first substrate B1; Transistor seconds 2 comprises the second drain D 2, second source S 2, second grid G2 and the second substrate B2.
In embodiments of the present invention in non-volatile memory cells, first drain D 1 of the first transistor 1 and bit line (BL, Bit Line) connect, the second drain D 2 (BLB anti-with bit line of transistor seconds 2, Bit Line Bar) connect, common and the wordline (WL of the first grid G1 of the first transistor 1 and second grid G2 of transistor seconds 2, Word Line) connect, first source S 1 of the first transistor 1 is connected with the first source line SL1, second source S 2 of transistor seconds 2 is connected with the second source line SL2, common and the substrate lines (SUBL of the substrate B1 of the first transistor 1 and the second substrate B1 of transistor seconds 2, SubstrateLine) connect.
In embodiments of the present invention in non-volatile memory cells, can preliminary setting data storage rule be passed through, namely how programming be carried out to realize the storage of data " 0 " and " 1 " to the first transistor 1 or transistor seconds 2.Such as, the first transistor 1 is programmed and represents storage data " 1 ", transistor seconds 2 programming is represented and stores data " 0 "; Or the first transistor 1 is programmed and represents storage data " 0 ", transistor seconds 2 programming is represented and stores data " 1 ".
For the ease of understanding, data " 1 " are stored below to represent the first transistor 1 programming, transistor seconds 2 is programmed and represents that storage data " 0 " is as the storage rule preset, and is described in detail the data programing of non-volatile memory cells, reading and erase process in the embodiment of the present invention.
Fig. 4 A, 4B are the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to data programing, and the non-volatile memory cells in Fig. 4 A, 4B comprises transistor A and transistor B, wherein,
Wordline WL0 applies word line programming voltage V
wL0;
Bit line BL0 applies bitline programming voltage V
bL0;
The anti-BLB0 of bit line applies the anti-program voltage V of bit line
bLB0;
First source line SL0A applies the first source line program voltage V
sL0A;
Second source line SL0B applies the second source line program voltage V
sL0B;
Substrate lines SUBL applies substrate lines program voltage V
sUBL;
Such as, only the transistor A of non-volatile memory cells is programmed, bitline programming voltage V
bL0=4V, the anti-program voltage V of bit line
bLB0=0V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBL=0V, represents and stores data " 1 "; Wherein,
As bitline programming voltage V
bL0=4V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBLduring=0V, represent and apply the bitline programming voltage V that size is 4V on the bit line BL0 be connected with the drain electrode of transistor A
bL0, at bitline programming voltage V
bL0effect under, will the side wall being positioned at the side not having light doping section of transistor A drain electrodes be electronically injected to, increase the conducting resistance between transistor A source-drain electrode, thus the On current I between the source-drain electrode making transistor A
abe less than initial turn-on electric current I
o.
As the anti-program voltage V of bit line
bLB0=0V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBLduring=0V, represent that on the anti-BLB0 of bit line be connected with the drain electrode of transistor B, apply size is the anti-program voltage V of 0V bit line
bLB0, at the anti-program voltage V of bit line
bLB0effect under, the On current I between the source-drain electrode of transistor B
bsize is constant, equals initial turn-on electric current I
o.
That is, due to the On current I between the source-drain electrode of the transistor A of programming
abe less than initial turn-on electric current I
o, and without programming transistor B source-drain electrode between On current I
bfor initial turn-on electric current I
o, therefore, the On current I between the source-drain electrode of the transistor A of programming
abe less than without programming transistor B source-drain electrode between On current I
b.
Only the transistor B of non-volatile memory cells is programmed, bitline programming voltage V
bL0=0V, the anti-program voltage V of bit line
bLB0=4V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBL=0V, represents and stores data " 0 "; Wherein,
As the anti-program voltage V of bit line
bLB0=4V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBLduring=0V, represent that on the anti-BLB0 of bit line be connected with the drain electrode of transistor B, apply size is the anti-program voltage V of 4V bit line
bLB0, at the anti-program voltage V of bit line
bLB0effect under, will the side wall being positioned at the side not having light doping section of transistor B drain electrodes be electronically injected to, increase the conducting resistance between transistor B source-drain electrode, thus the On current I between the source-drain electrode making transistor B
bbe less than initial turn-on electric current I
0.
As bitline programming voltage V
bL0=0V, word line programming voltage V
wL0=4V, the first source line program voltage V
sL0A=the second source line program voltage V
sL0B=0V, substrate lines program voltage V
sUBLduring=0V, represent and apply the bitline programming voltage V that size is 0V on the bit line BL0 be connected with the drain electrode of transistor A
bL0, at bitline programming voltage V
bL0effect under, the On current I between the source-drain electrode of transistor A
asize is constant, equals initial turn-on electric current I
0.
That is, due to the On current I between the source-drain electrode of the transistor B of programming
bbe less than initial turn-on electric current I
0, and without programming transistor A source-drain electrode between On current I
aequal initial turn-on electric current I
0, therefore, the On current I between the source-drain electrode of the transistor B of programming
bbe less than without programming transistor A source-drain electrode between On current I
a.
Fig. 5 is the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to digital independent,
Wordline WL0 applies word line read voltage V '
wL0;
Bit line BL0 applies bit line and reads voltage V '
bL0;
The anti-BLB0 of bit line applies bit line backward read power taking pressure V '
bLB0;
First source line SL0A applies the first source line and reads voltage V '
sL0A;
Second source line SL0B applies the second source line and reads voltage V '
sL0B;
Substrate lines SUBL applies substrate lines and reads voltage V '
sUBL;
Such as, bit line reads voltage V '
bL0=0V, bit line backward read power taking pressure V '
bLB0=0V, word line read voltage V '
wL0=2.5V, the first source line reads voltage V '
sL0A=the second source line reads voltage V '
sL0B=2.5V, substrate lines reads voltage V '
sUBL=0V, wherein,
If the On current I between source-drain electrode transistor A being detected by sense amplifier
aon current I between the source-drain electrode being less than transistor B
b, then think that the data stored in non-volatile memory cells are " 1 ".
If the On current I between source-drain electrode transistor B being detected by sense amplifier
bon current I between the source-drain electrode being less than transistor A
a, then think that the data stored in non-volatile memory cells are " 0 ".
Fig. 6 A, 6B are the schematic diagram in the embodiment of the present invention, non-volatile memory cells being carried out to data erase, and the non-volatile memory cells in Fig. 6 A, 6B comprises transistor A and transistor B, wherein,
Wordline WL0 applies word line erase voltage V "
wL0;
Bit line BL0 applies bit line erase voltage V "
bL0;
The anti-BLB0 of bit line applies the anti-erasing voltage V of bit line "
bLB0;
First source line SL0A applies the first source line erasing voltage V "
sL0A;
Second source line SL0B applies the second source line erasing voltage V "
sL0B;
Substrate lines SUBL applies substrate lines erasing voltage V "
sUBL;
Such as, the non-volatile memory cells storing data " 1 " is wiped, makes bit line erase voltage V "
bL0=4V, the anti-erasing voltage V of bit line "
bLB0=0V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBL=0V; Wherein,
As bit line erase voltage V "
bL0=4V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBLduring=0V, represent and apply the bit line erase voltage V that size is 4V on the bit line BL0 be connected with the drain electrode of transistor A "
bL0, at bit line erasing voltage V "
bL0effect under, hole is injected into the side wall being positioned at the side not having light doping section of transistor A drain electrodes, in and in programming process in the side wall of transistor A drain electrodes injected electrons, the On current I between the source-drain electrode making transistor A
arevert to initial turn-on electric current I
0.
As the anti-erasing voltage V of bit line "
bLB0=0V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBLduring=0V, represent and apply the anti-erasing voltage V of bit line that size is 0V on the anti-BLB0 of bit line be connected with the drain electrode of transistor B "
bLB0, at the anti-erasing voltage V of bit line "
bLB0effect under, the On current I between the source-drain electrode of transistor B
bfor initial turn-on electric current I
0.
Due to transistor A source-drain electrode between On current I
aand the On current I between the source-drain electrode of transistor B
bbe initial turn-on electric current I
0, therefore, by data " 1 " erasing stored in non-volatile memory cells.
The non-volatile memory cells storing data " 0 " is wiped, makes bit line erase voltage V "
bL0=0V, the anti-erasing voltage V of bit line "
bLB0=4V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBL=0V; Wherein,
As the anti-erasing voltage V of bit line "
bLB0=4V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBLduring=0V, represent and apply the anti-erasing voltage V of bit line that size is 4V on the anti-BLB0 of bit line be connected with the drain electrode of transistor B "
bLB0, at the anti-erasing voltage V of bit line "
bLB0effect under, hole is injected into the side wall being positioned at the side not having light doping section of transistor B drain electrodes, in and in programming process in the side wall of transistor B drain electrodes injected electrons, thus the On current I between the source-drain electrode making transistor B
brevert to initial turn-on electric current I
0.
As bit line erase voltage V "
bL0=0V, word line erase voltage V "
wL0=-4V, the first source line erasing voltage V "
sL0A=the second source line erasing voltage V "
sL0B=0V, substrate lines erasing voltage V "
sUBLduring=0V, represent and apply the bit line erase voltage V that size is 0V on the bit line BL0 be connected with the drain electrode of transistor A "
bL0, at bit line erasing voltage V "
bL0effect under, the On current between the source-drain electrode of transistor A is initial turn-on electric current I
0.
Due to transistor A source-drain electrode between On current I
aand the On current I between the source-drain electrode of transistor B
bbe initial turn-on electric current I
0, therefore, by data " 0 " erasing stored in non-volatile memory cells.
In the invention described above embodiment, although take operating voltage as the logic process of 0.13 micron of 3.3V be example, each voltage in data programing, reading and erase process is arranged, but be not limited to the present invention, along with the change of logic process, each voltage above-mentioned in data programing, reading and erase process can change with the change of operating voltage.Wherein,
Each voltage in data programing process comprises: word line programming voltage V
wL0, bitline programming voltage V
bL0, the anti-program voltage V of bit line
bLB0, the first source line program voltage V
sL0A, the second source line program voltage V
sL0B, substrate lines program voltage V
sUBL.
Each voltage in data read process comprises: word line read voltage V '
wL0, bit line reads voltage V '
bL0, bit line backward read power taking pressure V '
bLB0, the first source line reads voltage V '
sL0A, the second source line reads voltage V '
sL0B, substrate lines reads voltage V '
sUBL.
Each voltage in data erasing process comprises: word line erase voltage V "
wL0, bit line erase voltage V "
bL0, the anti-erasing voltage V of bit line "
bLB0, the first source line erasing voltage V "
sL0A, the second source line erasing voltage V "
sL0B, substrate lines erasing voltage V "
sUBL.
The foregoing is only preferred embodiment of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any amendment done the embodiment of the present invention, change, combination, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a non-volatile memory cells, is characterized in that, comprising:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds.
2. non-volatile memory cells according to claim 1, is characterized in that,
First, second transistor described comprises:
First heavily doped region, the second heavily doped region, polysilicon layer, substrate, asymmetric light doping section, the first side wall, the second side wall and silicon oxide layer; Wherein,
Described silicon oxide layer is positioned on described substrate;
Described polysilicon layer, described first side wall, described second side wall are all positioned on described silicon oxide layer;
Described first side wall, described second side wall lay respectively at the both sides of described polysilicon layer;
Described asymmetric light doping section is adjacent to described second heavily doped region and described silicon oxide layer.
3. non-volatile memory cells according to claim 2, is characterized in that,
Described first side wall, is positioned on first, second drain electrode described, for stored charge.
4. non-volatile memory cells according to claim 2, is characterized in that,
The thickness of described silicon oxide layer equals the thickness of the silicon oxide layer of the thick grid oxygen transistor under standard semiconductor logic process.
5. a programmed method for non-volatile memory cells, is characterized in that,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described programmed method comprises:
Wordline applies word line programming voltage;
Bit line applies bitline programming voltage;
The anti-program voltage of bit line is applied on bit line is anti-;
First source line applies the first source line program voltage;
Second source line applies the second source line program voltage;
Substrate lines applies substrate lines program voltage.
6. programmed method according to claim 5, is characterized in that,
Preliminary setting data storage rule, to programme to described non-volatile memory cells according to data storage rule and realizes the storage of data.
7. programmed method according to claim 5, is characterized in that,
Only the first transistor programming of described non-volatile memory cells is represented and store data " 1 ", only the transistor seconds programming of described non-volatile memory cells is represented and store data " 0 "; Or
Only the first transistor programming of described non-volatile memory cells is represented and store data " 0 ", only the transistor seconds programming of described non-volatile memory cells is represented and store data " 1 ".
8. programmed method according to claim 5, is characterized in that,
On current between the first transistor of programming or the source-drain electrode of transistor seconds is less than initial turn-on electric current;
Initial turn-on electric current is equaled without the On current between the first transistor of programming or the source-drain electrode of transistor seconds.
9. a read method for non-volatile memory cells, is characterized in that,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described read method comprises:
Wordline applies word line read voltage;
Bit line applies bit line and reads voltage;
Bit line backward read power taking pressure is applied on bit line is anti-;
First source line applies the first source line and reads voltage;
Second source line applies the second source line and reads voltage;
Substrate lines applies substrate lines and reads voltage; Wherein,
By detect the first transistor, transistor seconds source-drain electrode between On current, determine the data stored in non-volatile memory cells.
10. a method for deleting for non-volatile memory cells, is characterized in that,
Described non-volatile memory cells comprises:
The first transistor and transistor seconds, wherein,
The first transistor comprises the first drain electrode, the first source electrode, first grid and the first substrate;
Transistor seconds comprises the second drain electrode, the second source electrode, second grid and the second substrate;
First drain electrode of the first transistor is connected with bit line;
Second drain electrode of transistor seconds is connected with bit line is counter;
The first grid of the first transistor is connected with wordline jointly with the second grid of transistor seconds;
First source electrode of the first transistor is connected with the first source line, and the second source electrode of transistor seconds is connected with the second source line;
First substrate of the first transistor is connected with substrate lines jointly with the second substrate of transistor seconds;
Described method for deleting comprises:
Wordline applies word line erase voltage;
Bit line applies bit line erase voltage;
The anti-erasing voltage of bit line is applied on bit line is anti-;
First source line applies the first source line erasing voltage;
Second source line applies the second source line erasing voltage;
Substrate lines applies substrate lines erasing voltage; Wherein,
On current between the first transistor of erasing or the source-drain electrode of transistor seconds equals initial turn-on electric current.
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| US6097049A (en) * | 1998-03-18 | 2000-08-01 | Siemens Aktiengesellschaft | DRAM cell arrangement |
| CN101093716A (en) * | 2006-06-23 | 2007-12-26 | 国际商业机器公司 | Memory cell access circuit |
| CN101359505A (en) * | 2008-09-02 | 2009-02-04 | 北京芯技佳易微电子科技有限公司 | Read isolation programmable memory unit and programming and reading method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6097049A (en) * | 1998-03-18 | 2000-08-01 | Siemens Aktiengesellschaft | DRAM cell arrangement |
| CN101093716A (en) * | 2006-06-23 | 2007-12-26 | 国际商业机器公司 | Memory cell access circuit |
| CN101359505A (en) * | 2008-09-02 | 2009-02-04 | 北京芯技佳易微电子科技有限公司 | Read isolation programmable memory unit and programming and reading method thereof |
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