CN102623343A - Side wall hollow layer structure for semiconductor device and preparation method for side wall hollow layer structure - Google Patents
Side wall hollow layer structure for semiconductor device and preparation method for side wall hollow layer structure Download PDFInfo
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- CN102623343A CN102623343A CN2012100665256A CN201210066525A CN102623343A CN 102623343 A CN102623343 A CN 102623343A CN 2012100665256 A CN2012100665256 A CN 2012100665256A CN 201210066525 A CN201210066525 A CN 201210066525A CN 102623343 A CN102623343 A CN 102623343A
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- amorphous carbon
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Abstract
The invention provides a side wall hollow layer structure for a semiconductor device. The structure comprises a semiconductor substrate, a grid, medium layers and contact holes, wherein the hollow layer is arranged on the outer side of the grid; an outer side wall layer is arranged on the outer side of the hollow layer; and a SiO2 layer is arranged among the hollow layer, the grid and the semiconductor substrate. The invention also provides a method for preparing the side wall hollow layer structure. The method comprises the following steps of: depositing an amorphous carbon layer on the semiconductor substrate with the grid, and performing self-aligned etching to form an amorphous carbon side wall; depositing an outer side wall layer material, and performing self-aligned etching to form the outer side wall layer which seals the amorphous carbon side wall; performing chemical mechanical grinding on the medium layer until the medium layer is exposed from the amorphous carbon side wall, performing ashing treatment to completely remove the amorphous carbon side wall, and continuing to ash the amorphous carbon side wall until the grid and the exposed silicon surface form the SiO2 layer; and quickly filling the medium layer so that the part of which the amorphous carbon side wall is removed still keeps a hole. The side wall hollow layer structure is simple; and the method is simple and feasible.
Description
Technical field
The invention belongs to field of semiconductor technology, relate to a kind of semiconductor device sidewall structure and preparation method thereof, relate in particular to a kind of semiconductor device side wall cavity layer structure and preparation method thereof.
Background technology
Short-channel effect (Short Channel Effect) is cmos device channel length common phenomena when dwindling; It can cause threshold voltage shift; Break-through, DIBL (Drain induction barrier lower are leaked in the source; Drain-induced barrier reduces) characteristics such as (higher leakage are depressed), can cause the cmos device performance failure when serious.
Its principle charge available Share Model explains that promptly when raceway groove shortens, the ratio that source lining, leakage lining PN junction are shared raceway groove depletion region electric charge and raceway groove total electrical charge will increase, thereby cause the grid-control ability drop.
But the capacitive coupling of the fringe field that traditional charge-sharing model does not leak device source through side wall influences the effect of raceway groove to be taken into account, because traditional SiO
2Perhaps the SiON dielectric layer is thinner, and this effect is also not obvious.But when adopting the thick gate dielectric layer of hafnium, this effect will become big to the device influence, can cause the device property decline when serious.
In the device of the thick gate dielectric layer of high K, how to reduce this effect, can know that from theory analysis two kinds of methods are arranged: the one, the thickness of increase side wall, the 2nd, the dielectric constant of reduction side wall.The former is unfavorable for that integration density increases, and the latter is a kind of effective way, can reduce the coupling capacitance of side wall, thereby weakens fringe field that device source leaks influences raceway groove through the capacitive coupling of side wall effect.
Along with constantly reducing of device size; Short-channel effect is more and more serious, and in order to overcome the influence of short-channel effect, grid oxide layer need adopt the thick gate dielectric layer of hafnium; At this moment, the capacitance coupling effect of the fringe field that leaks of device source through side wall can become big to the influence of raceway groove.Simultaneously, the ever-reduced while of device size, the thickness of side wall also constantly reduces, and at this moment, the effect that the capacitively coupled of contact hole through side wall influences grid potential can become big.
Therefore, those skilled in the art is devoted to develop and a kind ofly can effectively reduces the dielectric constant of spacer material, influences raceway groove and grid potential thereby weaken capacitive coupling, and can prevent the semiconductor device sidewall structure of contact hole short circuit problem.
Summary of the invention
In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is the sidewall structure that lacks the dielectric constant that effectively reduces spacer material in the existing technology.
A kind of semiconductor device side wall provided by the invention cavity layer structure; Comprise Semiconductor substrate, grid, dielectric layer and contact hole; The outside of said grid is provided with the cavity layer, and the outside of said cavity layer is provided with the external wall layer, is provided with SiO between said cavity layer and said grid and the Semiconductor substrate
2Layer.
In a preferred embodiments of the present invention, said Semiconductor substrate is a silicon substrate.
In another preferred embodiments of the present invention, the material of said external wall layer is SiO
2, Si
3N
4, one or several the combination among the SiON.
The present invention also provides the preparation method of semiconductor device side wall cavity layer structure, may further comprise the steps:
Step 4, the autoregistration etching forms the external wall layer, and said external wall layer closes the amorphous carbon side wall;
Step 5 is carried out source, drain ion injection, high annealing;
Step 9 is carried out contact hole technology.
In another preferred embodiments of the present invention, the deposition in the said step 1 adopts the chemical gas-phase method deposition.
In another preferred embodiments of the present invention, said step 1 is for being provided with growth or deposition one deck SiO on the Semiconductor substrate of grid earlier
2Layer deposits one deck amorphous carbon layer again.
Semiconductor device side wall of the present invention cavity layer architecture is simple, and method is simple, through in side wall, introducing cavity layer and external wall layer, effectively reduces the dielectric constant of spacer material, and prevented the contact hole short circuit.Especially to having thick gate dielectric layer MOSFET of high K and nonvolatile storage location, can effectively weaken fringe field that device source the leaks capacitive coupling through side wall influence the effect that the effect of raceway groove and capacitively coupled that contact hole passes through side wall influence grid potential.
Description of drawings
Fig. 1 is the structural representation of embodiments of the invention;
Fig. 2 is the structural representation of the deposition amorphous carbon layer of embodiments of the invention;
Fig. 3 is the formation amorphous carbon sidewall structure sketch map of embodiments of the invention;
Fig. 4 is the deposition external wall layer material structures sketch map of embodiments of the invention;
Fig. 5 is the formation external wall layer structural representation of embodiments of the invention;
Fig. 6 is the structural representation behind the embodiments of the invention cmp interlayer dielectric layer;
Fig. 7 is the ashing amorphous carbon sidewall structure sketch map of embodiments of the invention.
Embodiment
Below will combine accompanying drawing that the present invention is done concrete explaination.
A kind of semiconductor device side wall cavity layer structure of embodiments of the invention as shown in fig. 1 comprises Semiconductor substrate 1, grid 2, dielectric layer 3 and contact hole 4.The outside of grid 2 is provided with cavity layer 5, and the outside of said cavity layer 5 is provided with external wall layer 6, is provided with SiO between said cavity layer 5 and said grid 2 and the Semiconductor substrate 1
2 Layer 7.
Semiconductor device side wall of the present invention cavity layer architecture is simple, and method is simple, through in side wall, introducing cavity layer and external wall layer, effectively reduces the dielectric constant of spacer material, and prevented the contact hole short circuit.
In an embodiment of the present invention, said Semiconductor substrate is a silicon substrate.
In addition, in an embodiment of the present invention, the material of external wall layer is SiO
2, Si
3N
4, one or several the combination among the SiON.Owing to enough hardness is arranged and, can not cause contact hole and grid and the raceway groove short circuit problem and the device reliability problem that possibly occur to the external wall layer of dielectric layer etching high selectivity.
The preparation method of the semiconductor device side wall cavity layer structure of embodiments of the invention may further comprise the steps:
As shown in Figure 2, step 1, deposition one deck amorphous carbon layer 8 on the Semiconductor substrate that is provided with grid 21; Preferred steps 1 is for growing on the Semiconductor substrate that is provided with grid 21 earlier or deposition one deck SiO
2Layer 7 deposits one deck amorphous carbon layer 8 again.
As shown in Figure 3, step 2, the autoregistration etching forms amorphous carbon side wall 81;
As shown in Figure 4, step 3, deposition external wall layer material 61;
As shown in Figure 5, step 4, the autoregistration etching forms external wall layer 6, and said external wall layer 6 closes amorphous carbon side wall 81;
Step 5 is carried out source, drain ion injection, high annealing;
As shown in Figure 6, step 6, metallization medium layer 3 adopts cmp to top portions of gates subsequently, and exposes until amorphous carbon side wall 81;
As shown in Figure 7, step 7, it is clean with the 81 whole ashing of amorphous carbon side wall to carry out ashing treatment, and continues ashing and form one deck SiO until grid 2 and the silicon face that exposes
2 Layer 7; This thin layer SiO
2Can effectively prevent grid and raceway groove short circuit.In step 1, generated SiO
2During layer, carry out ashing treatment in the step 7 the 81 whole ashing of amorphous carbon side wall are totally got final product, need not continue ashing.
As shown in fig. 1, step 9 is carried out contact hole technology.
In an embodiment of the present invention, the deposition in the step 1 adopts the chemical gas-phase method deposition.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (7)
1. semiconductor device side wall cavity layer structure; Comprise Semiconductor substrate, grid, dielectric layer and contact hole, it is characterized in that the outside of said grid is provided with the cavity layer; The outside of said cavity layer is provided with the external wall layer, is provided with SiO between said cavity layer and said grid and the Semiconductor substrate
2Layer.
2. semiconductor device side wall as claimed in claim 1 cavity layer structure is characterized in that said Semiconductor substrate is a silicon substrate.
3. semiconductor device side wall as claimed in claim 1 cavity layer structure is characterized in that the material of said external wall layer is SiO
2, Si
3N
4, one or several the combination among the SiON.
4. the preparation method of semiconductor device side wall as claimed in claim 1 cavity layer structure is characterized in that, may further comprise the steps:
Step 1 is being provided with deposition one deck amorphous carbon layer on the Semiconductor substrate of grid;
Step 2, the autoregistration etching forms the amorphous carbon side wall;
Step 3, deposition external wall layer material;
Step 4, the autoregistration etching forms the external wall layer, and said external wall layer closes the amorphous carbon side wall;
Step 5 is carried out source, drain ion injection, high annealing;
Step 6, metallization medium layer adopts cmp to top portions of gates subsequently, and exposes until the amorphous carbon side wall;
Step 7, it is clean with the whole ashing of amorphous carbon side wall to carry out ashing treatment, and continues ashing and form one deck SiO until grid and the silicon face that exposes
2Layer;
Step 8 is filled dielectric layer fast, makes the part of having removed the amorphous carbon side wall still keep hole;
Step 9 is carried out contact hole technology.
5. method as claimed in claim 4 is characterized in that, the material of said external wall layer is SiO
2, Si
3N
4, one or several the combination among the SiON.
6. method as claimed in claim 4 is characterized in that, the deposition in the said step 1 adopts the chemical gas-phase method deposition.
7. method as claimed in claim 4 is characterized in that, said step 1 is for being provided with growth or deposition one deck SiO on the Semiconductor substrate of grid earlier
2Layer deposits one deck amorphous carbon layer again.
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|---|---|---|---|
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| CN201210066525.6A CN102623343B (en) | 2012-03-14 | 2012-03-14 | Side wall hollow layer structure for semiconductor device and preparation method for side wall hollow layer structure |
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| CN102623343B CN102623343B (en) | 2014-06-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824765A (en) * | 2013-11-26 | 2014-05-28 | 上海华力微电子有限公司 | Grid side wall imaging method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6197641B1 (en) * | 1998-08-28 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
| CN101853879A (en) * | 2006-10-12 | 2010-10-06 | 三菱电机株式会社 | Field-effect transistor and method of manufacturing the same |
-
2012
- 2012-03-14 CN CN201210066525.6A patent/CN102623343B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6197641B1 (en) * | 1998-08-28 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
| CN101853879A (en) * | 2006-10-12 | 2010-10-06 | 三菱电机株式会社 | Field-effect transistor and method of manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824765A (en) * | 2013-11-26 | 2014-05-28 | 上海华力微电子有限公司 | Grid side wall imaging method |
| CN103824765B (en) * | 2013-11-26 | 2017-05-17 | 上海华力微电子有限公司 | Grid side wall imaging method |
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| CN102623343B (en) | 2014-06-04 |
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