CN102623423B - Integrated circuit pattern and multiple patterning method - Google Patents
Integrated circuit pattern and multiple patterning method Download PDFInfo
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- CN102623423B CN102623423B CN201110028133.6A CN201110028133A CN102623423B CN 102623423 B CN102623423 B CN 102623423B CN 201110028133 A CN201110028133 A CN 201110028133A CN 102623423 B CN102623423 B CN 102623423B
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Abstract
The invention discloses an integrated circuit pattern, wherein the integrated circuit pattern includes a set of material lines having X-direction portions and Y-direction portions. The X-direction portions and the Y-direction portions have a first spacing and a second spacing respectively, wherein the second spacing is greater than the first spacing, for example the second spacing is at least three times of the first spacing. The X direction portions are parallel to each other, and the Y-direction portions are also parallel to each other. End regions of the Y-direction portions include main line portions and biasing portions. The biasing portions include biasing elements, wherein the biasing elements are spaced from the main line portions and electrically connected to the main line portions. The biasing portions define contact regions for using in subsequent pattern transfer steps. The invention also discloses a multiple patterning method used during integrated circuit processes, wherein the method provides contact regions for using in the subsequent pattern transfer steps.
Description
Technical field
The invention relates to integrated circuit patterns and manufacture thereof, what comprise multiple patterning method is used in manufacture integrated circuit, can be promoted accessing of the line of material formed thus by this technical scheme.
Background technology
Integrated circuit is generally used for making diversified electronic installation, such as storage chip.For the size reducing integrated circuit, have a kind of powerful looking forward to, so that the density of Individual elements can be increased, and therefore improve the functional of integrated circuit.(representative being often normally used as the density of this circuit two contiguous structures (minimum range between the identical point of the such as grid conductor of two vicinities) of same form measures minimum spacing on integrated circuit.
The increase of current densities is often limited to the resolution of obtainable lithographic equipment.The minimum dimension in the feature that set lithographic equipment can produce and space is about its resolution capabilities.
The minimal characteristic width utilizing a set lithographic equipment to produce and the summation of minimum space width are the producible minimum spacing of this equipment.Minimal characteristic width many times probably equals minimum space width, so utilize a set producible minimum spacing of lithographic equipment probably to equal the minimal characteristic width of its producible twice.
The method spacing of integrated circuit (IC) apparatus being contracted to below minimum spacing that photoetching produces is the use via twice or four times of patternings (sometimes representing with multigraph patterning at this).Through planting method thus, single mask is typically for building a series of parallel line of material at substrate.Then diverse ways can be used to become many parallel line of material to convert the parallel line of material of every bar.Various method typically uses a series of deposition and etch step to do like this.Diverse ways is discussed at Xie, Peng and Smith, Bruce W., " analysis that the spacing about the higher level of sub-32nm photoetching is split ", Optical Microlithography XXII, Proc.of SPIE Vol.7274,72741 Y, c 2009SPIE.Be discussed at a kind of method of following example, be use autoregistration side wall spacers, think the every web stockline built from original mask, constructing is roughly two or four parallel line of material.
Summary of the invention
Part of the present invention is based on the understanding by reducing the extremely sub-lithographic dimensioned constructed problem of spacing.Namely, when the spacing between line of material may be sub-photoetching, for access line demand (typical case be via such as vertical plug access element) and cannot with sub-lithographic dimensioned complete compatibility.Be photoetching dimensionally for defining the mask of connector, and the tolerance limit of the misalignment of mask can increase the size for accessing needed for region.
One example of integrated circuit patterns comprises one group of line of material and is positioned on a substrate, and these line of material define many lines of a pattern, and it has X-direction part and Y-direction part.The length of X-direction part is in fact long than the length of Y-direction part.X-direction part has one first spacing, and Y-direction part has one second spacing, and the second spacing is greater than the first spacing.X-direction part is parallel to each other, and Y-direction part is parallel to each other.Y-direction part comprises stub area.The stub area of Y-direction part comprises main line part and biased part.Offset part is divided and is comprised biasing element, and itself and main line part are separated, and is electrically connected to main line part.Offset part is divided and is defined contact area and use for follow-up pattern transfer steps.
In some example, biased part is positioned at stub area.In some example, the second spacing is that at least 3 times of the first spacing are large.In some example, these lines are lines that photoetching is formed, and the first spacing has sub-lithographic dimensioned, and the second spacing has lithographic dimensioned.In some example, these lines are the line that photoetching is formed, and contact is picked up region and had lithographic dimensioned.In some example, Y-direction part comprises a continuous print loop and is biased part, and it contacts main line part and is positioned at the side of main line part.In some example, a biased part divides setting along the main line part that is correlated with, and comprises the element being roughly parallel to relevant main line part and extending and be approximately perpendicular to relevant main line part extension.In some example, transverse shift region is along main line part, and at least some biased part is positioned at transverse shift region.
One example of the multiple patterning method used during integrated circuit technology provides contact area to use for follow-up pattern transfer steps, and is implemented as follows.One group of parallel line pattern is selected using as one group of parallel first line of material.Parallel first line of material of this group is formed at a types of flexure, and each first line of material defines a pattern, and it has an X-direction part and a Y-direction part.The length of the X-direction part of the first line of material is in fact long than the length of the Y-direction part of the first line of material.The selection step of parallel line pattern comprises: select one first spacing to X-direction part use, and selects one second spacing to Y-direction part use, and the second spacing is greater than the first spacing, and X-direction part is parallel to each other, parallel to each other with Y-direction part.At least two second line of material are formed and are parallel to each first line of material, with the parallel Y-direction part of the parallel X-direction part and the second line of material that build the second line of material.The Y-direction part of the second line of material comprises stub area.Second line of material forming step comprises: form Y-direction part, it has main line part and biased part.Offset part is divided and is comprised biasing element, itself and main line part, and is electrically connected to main line part.Offset part is divided and is defined contact area and use for follow-up pattern transfer steps.
In some example, offset part is divided and is formed at stub area.In some example, the forming step of Y-direction part comprises; Form a continuous print loop and be biased part, it contacts main line part and is positioned at the side of main line part.In some example, the forming step of Y-direction part comprises: form a biased part, it comprises at least one biasing element and laterally extends from major part.In some example, the forming step of Y-direction part comprises: form a biased part, and it divides to arrange and comprise along main line part and is roughly parallel to main line part and is approximately perpendicular to the element that main line part extends.In some example, the forming step of Y-direction part comprises: form transverse shift region along main line part, and at least some biased part is positioned at transverse shift region.
Technical scheme of the present invention can promote accessing of the line of material formed thus.
In order to have clearer understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Fig. 1 to Fig. 8 shows the first example of four times of patterning process in simplified form.
Fig. 1 is the plan view from above being structured in nido within substrate, ring-shaped material line from corresponding moulding mask, these line of material have parallel X-direction part and parallel Y-direction part, and the spacing between X-direction part is less than the spacing in the Y direction between part.
Fig. 2 is presented at the structure of the wall of every side of the line of material of Fig. 1, utilizes follow-up spacing to reduce thus and makes density become double.
Fig. 3 is presented at the structure of the wall of every side of the line of material of Fig. 2, utilizes follow-up spacing to reduce thus and the change of the line density of Fig. 1 is quadrupled.
Fig. 4 shows the plan view from above of the mask used together with the structure of Fig. 3.
The mask that Fig. 5 shows Fig. 4 and the aiming at of structure of Fig. 3 of part covering Y-direction part.
The part of the Y-direction part that Fig. 6 display is covered by the mask of Fig. 4 of the stub area setting up line of material remove result.
Fig. 7 is the plan view treating to be used in the structure of Fig. 6 the mask building complementary features.
Fig. 8 shows the result of mask and suitable follow-up processing step that use Fig. 7, such as exposure and etching, for building complementary features, particularly in the contact pad of the stub area of part along the Y direction and bit line or wordline.
Fig. 9-Figure 16 shows the second example of four times of patterning process of the technique being similar to Fig. 1-Fig. 8 in simplified form, but exists in the line of material of wherein nido, ring-type with the form of L shape section.
Figure 17 A-Figure 17 C figure shows three additional examples of many nidos of group, the line of material of ring-type.
Figure 18 of the present invention multiple patterning method that above-mentioned reference diagram 1-17 discusses for display utilizes and the simplified flow chart of the basic step be implemented.
Figure 19-Figure 32 shows the manufacturing process of the example using BESNOS WL tetra-times of patternings.
Figure 33 is the calcspar that summary is presented at the relation between word line regions, contact area and peripheral circuit driver area.
Figure 34-Figure 36 is presented in twice patterning process the biased part using I shape design construction Y-direction part, and offset part divides the element comprising biasing element and biasing element is connected to main line part.
Figure 37-Figure 39 display is similar to the technique of Figure 34-Figure 36 but in twice patterning process, uses the technique that dual I shape is designed.
Figure 40-Figure 42 display is similar to the technique of the technique of Figure 37-Figure 39.
Figure 43-Figure 45 display is similar to the technique of Figure 34-Figure 36 but in twice patterning process, uses the technique that E shape is designed.
Figure 46-Figure 48 display is similar to the technique of the technique of Figure 43-Figure 45.
Figure 49-Figure 51 display is similar to the technique of Figure 34-Figure 36 but in twice patterning process, uses the technique that dual F shape is designed.
Figure 52-Figure 55 display is similar to the technique of Figure 37-Figure 39 but in four times of patterning process, uses the technique that dual P designs.
[main element symbol description]
10: group
12: the first line of material
14: substrate
16:X direction part
18:Y direction part
20: the first spacing
22: the second spacing
24: length
26: length
28: width
30: width
32: the second line of material/wall
34: the second line of material
34: the three line of material/wall
36: mask
38:Y points to word/bit line portion
40:X direction part
42: stub area
44: mask
46: contact pad/contact/contact area
48: circuit interconnection line
52:L shape section
54: mask
55: position
56:Y direction part/end component
60-70: method step
76: substrate
78: ground floor
80: the second layer
82: third layer
84: the four layers
86: layer 6
90: layer 7
92: the eight layers
94: photoresist circuit
96: structure
98:SiN layer
100: side wall spacers
102: film
104: side wall spacers
106: mask
107: polysilicon segment
108: lamination
109:SiO
2part
110: mask
112: lamination
113:SiO
2part
114: polysilicon segment
116: lamination
118:SiO
2part
120: memory cell
122: be etched element
124: wordline/be etched element
128: charge storage region
130: character string selects line
132: word line regions
134: contact area
136: peripheral circuit driver area
150: section
152: section
154:Y direction part
156: main line part
158: main line part
160: biased part
162: biasing element
164: Connection Element
166: distance
168: width
170,171,172: section
174,175: transverse shift region
176: join domain
178:Y direction part
180,181: main line part
182,183: biased part
184: biasing element
186: Connection Element
188: section
190: main section
192:Y direction part
194,196: main line part
198: biased part
200: biasing element
202: Connection Element
204: section
206: main section
208,210: first and second transverse shift region
212: join domain
214:Y direction part
216,218: main line part
220: biased part
222: distance
224: width
230: main section
232,234: transverse shift region
236: join domain
238: isolated island section
240: hole
242:Y direction part
244,245,246,247: main line part
248,249,250,251: biased part
254: biasing element
256: Connection Element
258: distance
260: width
262: size
Embodiment
We understand with the processing step understood illustrated by this and structure and the complete process flow of the undeclared manufacture for integrated circuit.The present invention may in conjunction with being used in known technology traditionally, or future is implemented by the various different ic manufacturing technology that develops.
Following explanation is generally with reference to embodiment and the method for particular configuration.We it will be appreciated that the present invention is not limited to disclosed in detail embodiment and method by intention, but the present invention can be implemented by using further feature, element, method and embodiment.Illustrated preferred embodiment is for showing the present invention, but not for limiting the category that it is defined by claim.Those those of ordinary skill in the art will assert for the incident various equivalent variations illustrated.Various different embodiment represents with identical reference number usually with the similar elements in example.
Various different example discussed below, is commonly referred to as the step using photoetching and photoetching, and it relates to pattern is transferred to next object from an object, and it is generally be done during the manufacture of integrated circuit by use mask and photoresist.But the present invention is not confined to this, the such as direct substrate that is written in by pattern can be comprised on the contrary and maybe may use other technology (such as electron beam) and step on other material be fabricated in the future.Lithography step and other pattern write or transfer techniques is commonly referred to pattern transfer steps sometimes.
Fig. 1-Fig. 8 shows the first example of four times of patterning process in simplified form.
Fig. 1 is the plan view from above of ring-type first line of material 12 of the nido of a group 10, and it is structured in a substrate 14 from corresponding suitable mask.First line of material 12 has parallel X-direction part 16 and parallel Y-direction part 18.Spacing 20 between X-direction part 16 is less than the spacing 22 in the Y direction between part 18.Spacing 22 preferably at least 2 times of spacing 22 large, 3 times that are more preferably at least spacing 22 are large, 4 times of even preferably spacing 22.In fact the length 24 of X-direction part 16 be greater than the length 26 of Y-direction part 18, is usually greater than multiple order of magnitude, as at least 30 times large.But, in order to graphic object, the length 24 also not drawn on scale of X-direction part 16, but significantly reduced.In this instance, the width 28 of each X-direction part 16 can such as need about 60nm, and the width 30 of each Y-direction part 18 can be such as about 150nm.Because spacing 22 is greater than spacing 20, so this kind of additional width for Y-direction part 18 can be held.
Fig. 2 is presented on the X-direction part 16 of first line of material 12 of Fig. 1 and every side of Y-direction part 18 and builds wall 32.Wall 32 is as one group of second line of material 32.This density effectively utilizing the inevitable reduction of spacing and make line density compare the first line of material 12 becomes twice.In follow-up treatment step, X-direction part 16 and the Y-direction part 18 of the first line of material 12 are removed, and only leave wall 32 as the second line of material.
Every side that Fig. 3 is presented at second line of material 32 of Fig. 2 builds wall 34, utilize thus spacing must reduce line density is become from the line density of Fig. 1 quadruple.As part 16 and 18, the second line of material 32 is removed during follow-up treatment step, only leaves wall 34 as the 3rd line of material 34.
Fig. 4 is the plan view from above of the mask 36 used together with the structure of Fig. 3.Mask 36 is parts of the Y-direction part 38 of wall 34 for mask apertures 3; In this example, X-direction part 40 does not change by using mask 36 as shown in Figure 5.Mask 36 is used to allow the part of the Y-direction part 38 removing wall 34.This result (display in figure 6) removed along the Y direction part 38 builds stub area 42.
Fig. 7 is the plan view of the mask 44 treating to use together with the structure of Fig. 6, for building complementary features portion.In this example, complementary features portion comprises contact pad to be applied to the stub area 42 of Y-direction part 38 and circuit interconnection line (circuit interconnect lines).Fig. 8 shows the result using mask 44 and suitable treatment step afterwards (such as expose and etch step), and for building complementary features portion, part 38 is at the contact pad 46 of stub area 42 and circuit interconnection line 48 especially along the Y direction.The spacing of Y-direction part 38 is preferably to being enough by the weld pad of size photolithographic fabrication and alignment tolerance, and the spacing of X-direction part 40 is not compressed because of these problems, therefore can be sub-photoetching.
When comparing the spacing of X-direction part 40, the spacing increased between the stub area 42 of part 38 is in the Y direction very important, because its tolerable is used in the known contact pad 46 by size photolithographic fabrication or larger weld pad that alternate manner formed, for provide electrically obtain the 3rd line of material 34 by the sub-photolithographic fabrication of size with the X-direction part 40 separated.3rd line of material 34 is general as wordline or bit line, and it can make X-direction part 40 and Y-direction part 38 be generally be respectively X to point to word/bit line portion 40 and Y points to word/bit line portion 38.By providing sufficient space between the inner most X-direction part 40 of these line of material 34, circuit interconnection line 48 can be placed between inner most X-direction part as shown in Figure 8.In other example, circuit interconnection line 48 can be arranged on the outside of the X-direction part 40 of the outermost of these line of material 34.Circuit interconnection line 48 can be by the line of photolithographic fabrication or sub-photolithographic fabrication by size.
Fig. 9-Figure 16 shows the second example of four times of patterning process in simplified form, and it is similar to the first example of four times of patterning process of Fig. 1-Fig. 8.Therefore, this second example can not be described in detail.But the main distinction is as follows.This group nido of 10, the line of material 12 of ring-type exist with the form of L shape section 52.Therefore, multipair L shape section 52 builds the line of material of this nido, ring-type.The mask 54 of Figure 12 is manufactured into the part not only covering Y-direction part 38 but also the part covering X-direction part 40 by size, and see Figure 13, it can make contiguous wall 34 be not electrically connected to each other by the end component 56 shown by Figure 11.
Figure 17 A-Figure 17 C shows three additional examples of many groups nido of 10, the line of material 12 of ring-type.Contact pad will part 56 and be formed at position 55 along the Y direction.
Figure 18 is the simplified flow chart of the basic step that display is implemented with multiple patterning method of the present invention.Start 68, selection, for one group of parallel line pattern of parallel first line of material 12 of a group 10, is generally nido annular patterns.First line of material 12 has parallel X-direction part 16, and it in fact can be longer than parallel Y-direction part 18, such as 100 or 1000 double-lengths.Secondly, 62, select first and second spacing 20,22 for X-direction and Y-direction part 16,18.These spacing are selected to make the second spacing 22 to the first spacing 20 larger, and such as 4-8 is doubly large.64, parallel first line of material 12 of this group 10 is formed in above a substrate 14.Article two, the second line of material 32 is formed at 66.Second line of material 32 is parallel to the first line of material 12.68, two article of the 3rd line of material 34 is parallel to every article of second line of material 32 and is formed.Do the parallel X-direction part 40 and parallel Y-direction part 38 that can build for the 3rd line of material like this.The Y-direction part 38 of the second line of material 34 comprises stub area 42.70, build complementary features portion, such as, at amplification contact pad 46 and the circuit interconnection line 48 of stub area 42.
Figure 19-Figure 32 shows the manufacturing process of an example of the autoregistration wall patterning using BE-SONOS WL tetra-times, and BE-SONOS represents charge trapping memory cells.Figure 19 display comprises the substrate 76 of first to the 8th layer of 78-92 and the photoresist circuit 94 be formed on ground floor 78.In this instance, the first, the 3rd is made up of polysilicon (usually representing with poly) with layer 6 78,82 and 88, and second and the 4th layer 80 and 84 by SiO
2formed.Layer 6 86 is made up of WSi.8th layer 92 is Si.Layer 7 90 is the compound of five layers, and for constructing as the charge storage for BE-SONOS, it has SiO alternately
2with SiN layer, wherein SiO
2layer for calculate from above the first, the 3rd and layer 5.First, second and third layer 78,80 and 82 are considered to be sacrifice layer, are because they are removed completely in patterning process.Also the configuration of other material and material can be used.
See Figure 20, photoresist circuit 94 is for etching of first layer 78 to build structure 96, and it corresponds to first line of material 12 of Fig. 1.Figure 21 display makes SiN layer 98 be deposited on the structure result above of Figure 20.Figure 22 shows the result that anisotropic etches this layer 98, and it removes those parts of the layer 98 of the structure 96 covered except layer 80.Do like this and side wall spacers 100 can be made to stay on every side of structure 96, wherein side wall spacers corresponds to the wall 32 of Fig. 2.Figure 23 shows the result that etching structure 96 leaves side wall spacers 100.The structure of the Figure 23 after the film 102 that Figure 24 is presented at polysilicon has been deposited thereon.In fig. 25, on side wall spacers 100 and the film 102 covering these parts of the second layer 80 be removed, make polysilicon sidewall wall 104 stay on every side of SiN side wall spacers 100 thus.
In fig. 26, photoresist mask 106 is for covering multiple parts of the structure of the Figure 25 be not yet removed.Mask 106 can be considered to be the contrary of the mask 36 of Fig. 4.Figure 27 display removes and is not subject to photoresist mask 106 the polysilicon sidewall wall 104 protected and the result removing photoresist mask 106 afterwards.Figure 28 shows the result of etching SiN side wall spacers 100 and those parts of the second layer 80 do not covered by side wall spacers 104; Do like this and can make polysilicon/SiO
2lamination 108 is stayed in third layer 82.Lamination 108 comprises the polysilicon segment 107 on top and the SiO of bottom
2part 109.Two structures 96 relatively on the right-hand side of the structure of Figure 20 and the polysilicon/SiO on the right-hand side of the structure of Figure 28
2lamination 108, we can find out that the number of vertical configuration becomes 4 times from 2 and becomes 8.
Figure 29 shows the constructional photoresist mask 110 of Figure 28, and mask 110 generally corresponds to the mask 44 of Fig. 7.Figure 30 is presented at those parts of the third layer 82 not being stacked 108 coverings or mask 110 and has been etched the structure of later Figure 29.The polysilicon segment 107 on top is removed and leaves lamination 112.Lamination 112 comprises the SiO on a top
2the polysilicon segment 114 of part 113 and a bottom.In fig. 30, photoresist mask 110 is also removed.Figure 31 shows the result of oxide etching, and it removes the SiO on top
2part 113 with not by the 4th SiO that polysilicon segment 114 covers
2any part of layer 84, and build lamination 116.Lamination 116 comprises polysilicon segment 114 and SiO
2part 118.
Figure 32 shows those parts that etching is not stacked the layer 86,88 and 90 of 116 coverings, removes polysilicon segment 114 and removes SiO with local
2the result of part 118, leave the memory cell arranged 120 with the element 122,124 (being generally respectively WSi and polysilicon) that is etched, form the wordline 124 of multiple row together, wordline 124 is on charge storage region 128.In this example, memory cell 120 forms NAND character string.In this example, this kind of etch step also builds the character string extended towards the direction identical with wordline 124 and selects line 130.Because the thickness of the 4th layer 84 is generally much larger than layer 7 90, so be etched by afterwards at whole layer 7 90, the SiO of a part can be remained
2part 118.
Figure 33 is the calcspar that the X closely separated be presented in word line regions 132 points to wordline part 40 and the wider Y sensing wordline part 38 separated.In a typical memory circuit, generally will there be thousands of wordline 124.In this example, two different contact areas 134 are set up and are adjacent to word line regions 132 and are connected to word line regions 132.Contact 46 points to wordline part 38 along wider (comparatively Large space) Y separated and is arranged within contact area 134.Peripheral circuit driver area 136 to be arranged between contact area 134 and to be connected to contact area 134.The configuration of this kind of following form provides the efficient layout in the actual area of integrated circuit to high-density city: (1) wordline is in word line regions 132; (2) if the one or more contact area 134 of word line regions 132 points to wordline part 38 along Y comprise contact 46; And (3) one or more relevant peripheral circuit driver area 136 contact area 134.
The following discussion of Figure 34-Figure 55 will illustrate for the various different modification of said method from structure, for partly building contact area in the Y direction.The example of Figure 34-Figure 51 utilizes the understanding of the four times of patternings used together with the example of Figure 52-Figure 55 and uses double patterning method, or also can use larger pattern.
Figure 34 shows Y-direction part 18, and it comprises the quite short Y-direction partial sector 150 being adjacent to main Y-direction partial sector 152.Section 150 is sometimes referred to as an isolated island section 150.Figure 35 to show on either side that conductive spacer layer 34 is formed in section 152 and around section 150.Figure 36 is presented at the structure removing section 150,152 later Figure 35, and leave Y-direction part 154 thus, it comprises main line part 156,158 and biased part 160.Biased part 160 comprises biasing element 162 (with main line part 158 spaced-apart and be roughly parallel to main line part 158) and multiple Connection Element 164 (biasing element 162 is electrically connected to main line part 158).Y-direction part 154 builds a contact area 46 and uses for follow-up lithography step.Distance 166 in the Y direction between partial sector 150,152 is preferably greater than the width 168 of main line part 156,158.Distance 166 is preferably less than the width 168 of three times.The pattern of this kind of form because the I shape of isolated island section 150, and designs sometimes referred to as a kind of I shape for double patterning.
Figure 37-Figure 39 is about a kind of dual I shape design for double patterning.Y-direction part 18 comprises Y-direction partial sector 170,171, and it is set up and is adjacent to main Y-direction partial sector 172.Main Y-direction partial sector 172 has first and second transverse shift region 174,175 connected by join domain 176.Figure 38 to show on either side that conductive spacer layer 34 is formed in section 172 and around isolated island section 170,171.Figure 39 is presented at the structure removing section 170,171 and 172 later Figure 38, and leave Y-direction part 178 thus, it comprises main line part 180,181 and biased part 182,183.Biased part 182,183 eachly comprises a biasing element 184 (with main line part 180,181 spaced-apart and be roughly parallel to main line part 180,181) and multiple Connection Element 186 (biasing element 184 being electrically connected to its each main line part 180,181).Y-direction part 178 builds contact area 46 and uses for follow-up lithography step.
Figure 40-Figure 42 shows the substitute of the example of Figure 37-Figure 39, and wherein similar element represents with similar reference number.
Figure 43-Figure 45 designs about a kind of E shape for double patterning.Figure 43 shows a Y-direction part 18, its comprise three suitable short, the section 188 laterally pointed to, it laterally extends from a main section 190 and is approximately perpendicular to main section 190.Figure 44 shows conductive spacer layer 34 and is formed at section 190 either side and around section 188.Figure 45 is presented at and removes section 188,190 and remain the structure comprising Figure 44 of the Y-direction part 192 of main line part 194,196 and biased part 198.Biased part 198 comprises a biasing element 200, and it separates with main line part 196 and Connection Element 202, and is roughly parallel to main line part 196 and Connection Element 202, and wherein Connection Element 202 is electrically connected biasing element 200 to main line part 196.Y-direction part 192 builds a contact area 46 and uses for follow-up lithography step.In this instance, contact area 46 comprises the part of biased part 198 and both main line parts 194,196; In other example, contact area 46 cannot comprise a part for main line part 194.Distance 222 in the Y direction between partial sector 188 is preferably more than or equal to the width 224 of main line part 194,196.Distance 222 is preferably less than the width 224 of 4 times.These sizes typically have similar design, such as Figure 46-Figure 49 and the design shown by Figure 49-Figure 51.
Figure 46-Figure 48 shows the substitute of the example of Figure 43-Figure 45, and wherein similar element represents with similar reference number.
Figure 49-Figure 51 is about a kind of dual F shape design for double patterning.Figure 49 display comprises a Y-direction part 18 of a main section 206, and main section 206 has first and second transverse shift region 208,210 connected by a join domain 212.Part 18 also comprises two from main section 206 horizontal expansion and the quite short transverse direction being approximately perpendicular to main section 206 points to section 204.Figure 50 to show on either side that conductive spacer layer 34 is formed in section 206 and around section 204.Figure 51 is presented at the structure removing section 204,206 later Figure 47, and leave a Y-direction part 214 thus, it comprises main line part 216,218 and the biased part 220 from main line part 216,218 horizontal expansion.Biased part 220 is electrically connected to main line part 216,218.Y-direction part 214 build towards 216,218 to each relevant contact area 46 of main line part, use for follow-up lithography step.
Figure 52-Figure 55 is about a kind of dual P shape design for four times of patternings.Figure 52 display comprises a Y-direction part 18 of a main section 230, and main section 230 has first and second transverse shift region 232,234 connected by a join domain 236.Part 18 also comprise two with the quite short isolated island section 238 of main section 230 spaced-apart.Hole 240 is formed in join domain 236.The edge that Figure 53 is presented at wall 32 part 18 along the Y direction forms the structure of later Figure 52.Figure 54 is presented at and removes the formation of the later conductive spacer layer of Y-direction part 18 34 along the edge of wall 32.Figure 55 is presented at the structure removing the later Figure 54 of wall 32, leaves a Y-direction part 242 thus, its biased part 248,249,250,251 comprising main line part 244,245,246,247 and extend from their relative primary parts transversely.Each biased part 248-25 1 comprises a biasing element 254, and it is electrically connected to its relevant main line part by Connection Element 256.Y-direction part 242 builds one group of four contact area 46 and uses for follow-up lithography step.Is a conducting element within each offset part is divided, and it does not need to be electrically connected to other structure any but really helps to provide mechanical stability to produced contact area 46.Distance 258 between isolated island section 238 and the region 232 of main section 230, is preferably more than or equal to the width 260 of twice main line part 244-247, and is preferably less than or equals the width 260 of main line part 244-247 of five times.Size 262 is preferably more than or equal to the width 260 of main line part 244-247, and is preferably less than or equals the width 260 of main line part 244-247 of three times.
The present invention that above-mentioned reference diagram 34-Figure 55 discusses can be used in general semiconductor device (comprising storage and logic element), for building the various different features (such as grid) except above-mentioned discussed metallization pattern.The present invention is also applicable to various different IC process technology, comprise shallow trench isolation from.
Openly list in the lump as reference data with reference to above-mentioned any and all patents, patent application and printing.
In sum, although the present invention with preferred embodiment openly as above, so it is not intended to limit the present invention.Persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various trickle change and correction.Therefore, protection scope of the present invention is when being as the criterion depending on the claim person of defining.
Claims (28)
1. an integrated circuit patterns, is characterized in that, comprises:
One group of line of material, is positioned at a types of flexure, and these line of material define many lines of a pattern, and it has multiple X-direction part and multiple Y-direction part, and the length of these X-direction parts is longer than the length of these Y-direction parts;
These X-direction parts have one first spacing, and these Y-direction parts have one second spacing, and this second spacing is greater than this first spacing;
These X-direction parts are parallel to each other, and these Y-direction parts are parallel to each other;
These Y-direction parts comprise multiple stub area; And
These stub areas of these Y-direction parts comprise multiple main line part and multiple biased part, these offset part are divided and are comprised multiple biasing element, itself and these main line part is separated, and be electrically connected to these main line parts, these offset part are divided and are defined multiple contact area, use, wherein for follow-up pattern transfer steps, biasing element is parallel to main line part and is electrically connected to main line part by multiple Connection Element, and the distance between Y-direction partial sector is greater than the width of main line part.
2. integrated circuit patterns according to claim 1, is characterized in that, these biased parts are positioned at these stub areas.
3. integrated circuit patterns according to claim 1, is characterized in that, these length of these X-direction parts are minimum is 30 times of these length of these Y-direction parts.
4. integrated circuit patterns according to claim 1, is characterized in that, this second spacing is at least 2 times of this first spacing greatly.
5. integrated circuit patterns according to claim 1, is characterized in that, this second spacing is at least 4 times of this first spacing greatly.
6. integrated circuit patterns according to claim 1, is characterized in that, these X-direction sections transverse are in these Y-direction parts.
7. integrated circuit patterns according to claim 1, is characterized in that, these lines comprise many wordline or multiple bit lines.
8. integrated circuit patterns according to claim 1, is characterized in that, these lines are the line that photoetching is formed, and this first spacing has sub-lithographic dimensioned, and this second spacing has lithographic dimensioned.
9. integrated circuit patterns according to claim 1, is characterized in that, these Y-direction parts and these X-direction parts define one group of nido ring-type parallel line.
10. integrated circuit patterns according to claim 1, is characterized in that, these lines are the line that photoetching is formed, and these contact areas have multiple lithographic dimensioned.
11. integrated circuit patterns according to claim 1, is characterized in that, these Y-direction parts comprise a continuous print loop and are biased part, and it contacts this main line part and is positioned at the side of this main line part.
12. integrated circuit patterns according to claim 11, is characterized in that, these offset part are divided and comprised at least one biasing element laterally extended from these main line parts.
13. integrated circuit patterns according to claim 1, is characterized in that, a biased part is divided along a relevant main line part and arranged and comprise multiple element, and these elements extend and are parallel to relevant main line part or perpendicular to the main line part of being correlated with.
14. integrated circuit patterns according to claim 1, is characterized in that, comprise the multiple transverse shift regions along these main line parts, these biased parts at least some is positioned at these transverse shift regions.
15. 1 kinds of multiple patterning methods, use, it is characterized in that during integrated circuit technology, and for providing multiple contact area to use for follow-up pattern transfer steps, the method comprises:
Be that one group of parallel first line of material selects one group of parallel line pattern;
Form parallel first line of material of this group in the top of a substrate, each first line of material defines the pattern that has an X-direction part and a Y-direction part, and the length of these X-direction parts of these the first line of material is longer than the length of these Y-direction parts of these the first line of material;
The selection step of these parallel line patterns comprises: for these X-direction parts select one first spacing, and be that these Y-direction parts select one second spacing, this second spacing is greater than this first spacing, and these X-direction parts are parallel to each other, and these Y-direction parts are parallel to each other;
Form at least two the second line of material and be parallel to each first line of material with the parallel Y-direction part of the parallel X-direction part and these the second line of material that build these the second line of material, these Y-direction parts of these the second line of material comprise multiple stub area; And
The forming step of these the second line of material comprises: form these Y-direction parts with multiple main line part and multiple biased part, these offset part are divided and are comprised multiple biasing element, itself and these main line part is separated and is electrically connected to these main line parts, these offset part are divided and are defined multiple contact area, use for follow-up pattern transfer steps, wherein, biasing element is parallel to main line part and is electrically connected to main line part by multiple Connection Element, and the distance between Y-direction partial sector is greater than the width of main line part.
16. methods according to claim 15, is characterized in that, these offset part are divided and are formed at these stub areas.
17. methods according to claim 15, is characterized in that, the forming step of these Y-direction parts comprises: form a continuous print loop and be biased part, and it contacts this main line part and is positioned at the side of this main line part.
18. methods according to claim 15, is characterized in that, the forming step of these Y-direction parts comprises: form a biased part, it comprises at least one biasing element laterally extended from this main line part.
19. methods according to claim 15, it is characterized in that, the forming step of these Y-direction parts comprises: form a biased part, and it divides along this main line part and arranges and comprise multiple element, and the extension of these elements is roughly parallel to this main line part or is approximately perpendicular to this main line part.
20. methods according to claim 15, is characterized in that, the forming step of these Y-direction parts comprises: divide along these main line parts and form multiple transverse shift region, and at least some of these biased parts is positioned at these transverse shift regions.
21. methods according to claim 15, is characterized in that, these second line of material comprise many wordline or bit line.
22. methods according to claim 15, is characterized in that, the forming step of these at least two the second line of material also comprises:
Form two additional materials lines, it is parallel to respectively this first line of material; And
Form two the second line of material, it is parallel to respectively this additional materials line.
23. methods according to claim 15, is characterized in that, the selection step of these parallel line patterns comprises: be that one group of parallel first line of material of nido ring-type selects one group of nido ring-type parallel line pattern.
24. methods according to claim 15, is characterized in that, also comprise: remove these at least part of Y-direction parts to build these stub areas.
25. methods according to claim 15, is characterized in that, these the first line of material wherein one define following one of at least: a continuous print rectangular shape; One rectangular shape, it has one along the gap of the wherein one of these Y-direction parts; One rectangular shape, it has one along the gap of these Y-direction parts; And a rectangular shape, it only has a Y-direction part.
26. methods according to claim 15, is characterized in that, these length of these X-direction parts are at least 30 times of these length of these Y-direction parts.
27. methods according to claim 15, is characterized in that, this second spacing is at least 2 times of this first spacing.
28. methods according to claim 15, is characterized in that, this second spacing is at least 4 times of this first spacing.
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| CN101567372A (en) * | 2008-04-22 | 2009-10-28 | 旺宏电子股份有限公司 | Integrated circuit |
| US7651951B2 (en) * | 2005-03-15 | 2010-01-26 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
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| US7351666B2 (en) * | 2006-03-17 | 2008-04-01 | International Business Machines Corporation | Layout and process to contact sub-lithographic structures |
| US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
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| US7651951B2 (en) * | 2005-03-15 | 2010-01-26 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
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