CN102683206A - Preparation method for strain silicon nanowire P-channel metal oxide semiconductor field effect transistor (PMOSFET) - Google Patents

Preparation method for strain silicon nanowire P-channel metal oxide semiconductor field effect transistor (PMOSFET) Download PDF

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CN102683206A
CN102683206A CN2012101360039A CN201210136003A CN102683206A CN 102683206 A CN102683206 A CN 102683206A CN 2012101360039 A CN2012101360039 A CN 2012101360039A CN 201210136003 A CN201210136003 A CN 201210136003A CN 102683206 A CN102683206 A CN 102683206A
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silicon
layer
preparation
etching
source
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黄晓橹
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

The invention provides a preparation method for a strain silicon nanowire P-channel metal oxide semiconductor field effect transistor (PMOSFET). The method comprises the following steps of: providing a silicon on insulator (SOI) silicon chip, wherein the SOI silicon chip comprises a silicon substrate, a buried oxide layer on the silicon substrate and a top silicon layer on the buried oxide layer; forming a silicon nanowire field effect transistor area, forming a cavity layer between the top silicon layer and the buried oxide layer, and preparing a silicon nanowire on the top silicon layer above the cavity layer; precipitating amorphous carbon, and filling the cavity layer below the top silicon layer; performing a gate oxide process to prepare a gate oxide layer, and depositing a gate material; depositing an insulating dielectric material, filling the cavity layer below the top silicon layer, and etching a gate sidewall; etching the top silicon layer in a source area and a drain area, growing a silicon germanium layer on each of a source and a drain, and performing source and drain area in-situ doping; and performing a metal silicon alloy process and a contact hole process, and leading out the source, the drain and the gate. The compressive stress of the silicon nanowire in a source direction and a drain direction in a P-channel silicon nanowire FET (P-SiNWFET) is strengthened, so that the current driving capability of the P-SiNWFET is effectively improved.

Description

The preparation method of strained silicon nano wire PMOSFET
Technical field
The invention belongs to semiconductor applications, relate to the preparation method of a kind of silicon nanowires PMOSFET, relate in particular to the preparation method of a kind of strained silicon nano wire PMOSFET.
Background technology
Current, it is very general in advanced person's semiconductor device is made, to introduce strain engineering.In passing through the semiconductor device of strain engineering manufacturing; For channel direction is the MOSFET of < 110 >; When channel direction has tensile stress; The current driving ability of NMOSFET can be effectively increased, and when channel direction has compression, the current driving ability of PMOSFET can be effectively increased.
As a same reason; For state-of-the-art semiconductor nanowires field-effect transistor (Nanowire Field Effect Transistor; NWFET), if introduce strain engineering, also will increase the current driving ability of NWFET greatly in its nanowire length direction (being channel direction).As after introducing stress engineering among < 110>NW nFET, (adopting stress memory technique; SMT); Current driving ability has increased 58% (Masumi Saitoh; " Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement ", IEDM, 2010).
United States Patent (USP) (publication number: US 2011/0104860 A1) discloses builds stressed semiconductor nano wire preparation method in a kind of; It is based on the Semiconductor substrate with oxygen buried layer (like the SOI substrate); After the semiconductor nanowires preparation is accomplished; Deposition one deck tensile strain thin layer is like the strain silicon nitride layer.After follow-up strain film etching, because the tension force effect of the strain film of both sides source and drain areas makes the semiconductor nanowires of area of grid (being channel region) have compression with area of grid.After grid technology was accomplished, the compression of this semiconductor nanowires length direction (being the NWFET channel direction) just was fixed in the semiconductor nanowires, after follow-up tensile strain thin layer is removed this compression was disappeared.
This method has following two shortcomings:
The semiconductor nanowires of this structure is to link to each other with two relative liners of semiconductor; And two liners of semiconductor link to each other with dielectric base; There is a step to be in its prepared process; Be wrapped in that tensile strain film on the semiconductor nanowires is etched away and only keep and be wrapped in the tensile strain film on two liners of semiconductor, at this moment, receive both sides tensile stress effect; The suffered power of semiconductor nanowires is not in the horizontal direction in fact, but the reverse compression of the certain angle that makes progress again in the horizontal direction.When semiconductor nanowires was enough thin, this not in the horizontal direction reverse compression may cause the semiconductor nanowires middle part to misplace, even ruptures.
And; The strain film layer needs to remove after the grid preparation finishes, and this is a kind of stress memory technique (SMT, Stress Memorized Technology) in fact; The semiconductor nanowires channel stress of its generation can only arrive 0.3GPa, can't make the bigger increase of Ion of P-NWFET.
Summary of the invention
In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is the preparation method who lacks stabilizing effective strained silicon nano wire PMOSFET in the existing technology.
The preparation method of a kind of strained silicon nano wire PMOSFET provided by the invention may further comprise the steps:
Step 1 provides soi wafer, comprises oxygen buried layer and the top layer silicon on the oxygen buried layer on silicon substrate, the silicon substrate;
Step 2, definition silicon nanowires field-effect transistor zone, and between top layer silicon and oxygen buried layer, form the cavity layer, on the top layer silicon above the layer of cavity, prepare silicon nanowires;
Step 3, deposition amorphous carbon, and fill the cavity layer below the top layer silicon;
Step 4, the amorphous carbon of etching area of grid is until exposing oxygen buried layer;
Step 5 is carried out grid oxygen prepared grid oxide layer, and deposition of gate material;
Step 6 is removed amorphous carbon;
Step 7, deposition dielectric material, and fill the cavity layer below the top layer silicon, etching forms grid curb wall;
Step 8, etching source are leaked the top layer silicon of cushion region, and at source drain region growth germanium silicon layer, it is in-situ doped to carry out source and drain areas simultaneously;
Step 9 is carried out the metallic silicon alloy technique, and contact hole technology, and source, leakage, grid are drawn.
In a preferred embodiments of the present invention, the thickness of the oxygen buried layer in the said step 1 is 10 ~ 1000nm, and top layer silicon thickness is 10 ~ 200nm.
In another preferred embodiments of the present invention, also comprise in the said step 1 through ion and injecting or the original foreign ion that contains of said top layer silicon, as the channel doping ion of subsequent device.
In another preferred embodiments of the present invention, form silicon nanowires field-effect transistor zone through photoetching and etching in the said step 2, and until etching away the part oxygen buried layer.
In another preferred embodiments of the present invention, adopt wet etching to remove the part oxygen buried layer in the said step 2, form the cavity layer.
In another preferred embodiments of the present invention, through thermal oxidation technology and wet-etching technology, prepare the silicon nanowires on the top layer silicon above in the of empty layer in the said step 2.
In another preferred embodiments of the present invention, the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertically track shape.
In another preferred embodiments of the present invention, through photoetching or selective etch the area of grid etching is come out in the said step 4, and until oxygen buried layer.
In another preferred embodiments of the present invention, the grid material in the said step 5 is a metal gate material.
In another preferred embodiments of the present invention, leak the top layer silicon of cushion region in the said step 8 through autoregistration selective etch source, and keep the part top layer silicon of bottom, as the inculating crystal layer of growth germanium silicon layer.
The present invention has adopted the e-SiGe technology to be applied among the P-SiNWFET, has increased the compression of silicon nanowires source leakage direction among the P-SiNWFET, thereby effectively increases the current driving ability of P-SiNWFET.
Description of drawings
Fig. 1 is the structural representation of the soi wafer of embodiments of the invention;
Fig. 2 a is the structure vertical view that embodiments of the invention define silicon nanowires field-effect transistor zone;
Fig. 2 b is the structural representation that embodiments of the invention define silicon nanowires field-effect transistor zone;
Fig. 3 is the structural representation that embodiments of the invention form the cavity layer;
Fig. 4 a is the structure vertical view that embodiments of the invention form silicon nanowires;
Fig. 4 b is the structural representation that embodiments of the invention form silicon nanowires;
Fig. 5 is the structural representation that embodiments of the invention form grid layer;
Fig. 6 is the structural representation that embodiments of the invention form grid curb wall;
Fig. 7 is the structural representation after the embodiments of the invention etched portions top layer silicon;
Fig. 8 is the structural representation behind the embodiments of the invention growth germanium silicon layer.
Embodiment
Below will combine accompanying drawing that the present invention is done concrete explaination.
The preparation method of the strained silicon nano wire PMOSFET of embodiments of the invention may further comprise the steps:
Step 1 provides soi wafer as shown in Figure 1, comprises oxygen buried layer 2 and the top layer silicon 3 on the oxygen buried layer 2 on silicon substrate 1, the silicon substrate 1; Preferably, oxygen buried layer 2 thickness are 10 ~ 1000nm, and top layer silicon 3 thickness are 10 ~ 200nm.And preferably inject or the original foreign ion that comprises of top silicon layer through ion, as the channel doping ion of follow-up NWFET.
Step 2, definition silicon nanowires field-effect transistor zone, wherein; Can adopt photoresistance mask (PR mask) through photoetching, etching, also can adopt hard mask (Hard mask) to define silicon nanowires field-effect transistor (Si Nanowire FET; SiNWFET) zone, shown in Fig. 2 a and 2b, middle 4 is the silicon nanowires zone that defines; Both sides 5 are that liner (Pad) is leaked in the source of NWFET, etch into oxygen buried layer 2 always, and etch away part oxygen buried layer 2 downwards.
And as shown in Figure 3, adopt wet etching removal part oxygen buried layer 2, between top layer silicon 3 and oxygen buried layer 2, form cavity layer 6, and guarantee that the source leakage pad position of top layer silicon links to each other with following oxygen buried layer;
Shown in Fig. 4 a and the 4b, remove the oxide layer on top layer silicon 3 surfaces for another example, prepare silicon nanowires 7 through thermal oxidation technology and wet method.Different according to silicon nanowires zone etching width and thickness, the cross sectional shape of silicon nanowires is also different, and circle, laterally three kinds of track shape and vertical track shape are arranged.
, step 3, deposition amorphous carbon, and fill the cavity layer below the top layer silicon; Employing has the amorphous carbon of high etching selection ratio and high absorptive as the separator in the grid technique of back, is beneficial to gate trench figure (profile) control; And agraphitic carbon ashing easily after the back grid technique is accomplished is beneficial to figure control.
Step 4, photoetching, selective etch come out the area of grid etching of NWFET, etch away the amorphous carbon of area of grid, and etch into till the oxygen buried layer always.
Step 5 is carried out grid oxygen technology, can prepare SiO through depositing operation 2Perhaps SiON or Si 3N 4The perhaps grid oxide layer of hafnium or its combination, wherein, hafnium can be HfO 2, ZrO 2, La 2O 3, Al 2O 3, TiO 2, SrTiO 3, LaAlO 3, Y 2O 3, HfOxNy, ZrOxNy, La 2OxNy, Al 2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y 2A kind of or combination among the OxNy, and deposition of gate material, the preferable alloy grid material.And cmp is removed unnecessary grid material.
Step 6 as shown in Figure 5, is removed amorphous carbon (AC) layer through cineration technics (Ashing), and is kept grid material 8.Because AC can totally and not can have influence on other part with its ashing as the separator that adopts in the grid technique of back.
Step 7, as shown in Figure 6, deposition dielectric material 9 is preferably SiO 2And the cavity layer 6 of filling top layer silicon below, the preparation of autoregistration etching forms grid curb wall 81; And carry out the source and leak injection technology.
Step 8, as shown in Figure 7, the silicon layer of cushion region 10 is leaked in autoregistration selective etch source, up to the thin layer that stays the bottom top layer silicon, as the inculating crystal layer of follow-up epitaxy Si Ge.Owing to adopt metal material as grid layer, when selective etch, can keep the grid pattern well; As shown in Figure 8, leak cushion region selective epitaxial growth (SEG, Selective Epitaxial Growth) SiGe layer 11 in the source that etches, wherein the chemical mol ratio of Ge is 1% ~ 100%, is preferably 10% ~ 50%.Simultaneously, it is in-situ doped to carry out the source leakage, preferably, and doping B+.Owing to adopt metal material as grid layer, the epitaxial growth of grid top when having avoided the source to leak cushion region selective epitaxial growth SiGe;
Step 9 is carried out the metallic silicon alloy technique, and contact hole technology, and source, leakage, grid are drawn.
The present invention has adopted the e-SiGe technology to be applied among the P-SiNWFET, has increased the compression of silicon nanowires source leakage direction among the P-SiNWFET, thereby effectively increases the current driving ability of P-SiNWFET.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims (10)

1. the preparation method of a strained silicon nano wire PMOSFET is characterized in that, may further comprise the steps:
Step 1 provides soi wafer, comprises oxygen buried layer and the top layer silicon on the oxygen buried layer on silicon substrate, the silicon substrate;
Step 2, definition silicon nanowires field-effect transistor zone, and between top layer silicon and oxygen buried layer, form the cavity layer, on the top layer silicon above the layer of cavity, prepare silicon nanowires;
Step 3, deposition amorphous carbon, and fill the cavity layer below the top layer silicon;
Step 4, the amorphous carbon of etching area of grid is until exposing oxygen buried layer;
Step 5 is carried out grid oxygen prepared grid oxide layer, and deposition of gate material;
Step 6 is removed amorphous carbon;
Step 7, deposition dielectric material, and fill the cavity layer below the top layer silicon, etching forms grid curb wall;
Step 8, etching source are leaked the top layer silicon of cushion region, and at source drain region growth germanium silicon layer, it is in-situ doped to carry out source and drain areas simultaneously;
Step 9 is carried out the metallic silicon alloy technique, and contact hole technology, and source, leakage, grid are drawn.
2. preparation method as claimed in claim 1 is characterized in that, the thickness of the oxygen buried layer in the said step 1 is 10 ~ 1000nm, and top layer silicon thickness is 10 ~ 200nm.
3. preparation method as claimed in claim 1 is characterized in that, also comprises in the said step 1 through ion injecting or the original foreign ion that contains of said top layer silicon, as the channel doping ion of subsequent device.
4. preparation method as claimed in claim 1 is characterized in that, forms silicon nanowires field-effect transistor zone through photoetching or etching in the said step 2, and until etching away the part oxygen buried layer.
5. preparation method as claimed in claim 1 is characterized in that, adopts wet etching to remove the part oxygen buried layer in the said step 2, forms the cavity layer.
6. preparation method as claimed in claim 1 is characterized in that, through thermal oxidation technology and wet-etching technology, prepares the silicon nanowires on the top layer silicon above in the of empty layer in the said step 2.
7. preparation method as claimed in claim 6 is characterized in that, the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertically track shape.
8. preparation method as claimed in claim 1 is characterized in that, through photoetching or selective etch the area of grid etching come out in the said step 4, and until oxygen buried layer.
9. preparation method as claimed in claim 1 is characterized in that, the grid material in the said step 5 is a metal gate material.
10. preparation method as claimed in claim 1 is characterized in that, leaks the top layer silicon of cushion region in the said step 8 through autoregistration selective etch source, and keeps the part top layer silicon of bottom, as the inculating crystal layer of growth germanium silicon layer.
CN2012101360039A 2012-05-04 2012-05-04 Preparation method for strain silicon nanowire P-channel metal oxide semiconductor field effect transistor (PMOSFET) Pending CN102683206A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577734A (en) * 2003-07-28 2005-02-09 英特尔公司 Method of fabricating an ultra-narrow channel semiconductor device
US20090146194A1 (en) * 2007-12-05 2009-06-11 Ecole Polytechnique Federale De Lausanne (Epfl) Semiconductor device and method of manufacturing a semiconductor device
US7989233B2 (en) * 2009-04-03 2011-08-02 International Business Machines Corporation Semiconductor nanowire with built-in stress

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577734A (en) * 2003-07-28 2005-02-09 英特尔公司 Method of fabricating an ultra-narrow channel semiconductor device
US20090146194A1 (en) * 2007-12-05 2009-06-11 Ecole Polytechnique Federale De Lausanne (Epfl) Semiconductor device and method of manufacturing a semiconductor device
US7989233B2 (en) * 2009-04-03 2011-08-02 International Business Machines Corporation Semiconductor nanowire with built-in stress

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Application publication date: 20120919