CN102694122A - 两端可重写非易失性离子传输rram器件 - Google Patents

两端可重写非易失性离子传输rram器件 Download PDF

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CN102694122A
CN102694122A CN2012101934211A CN201210193421A CN102694122A CN 102694122 A CN102694122 A CN 102694122A CN 2012101934211 A CN2012101934211 A CN 2012101934211A CN 201210193421 A CN201210193421 A CN 201210193421A CN 102694122 A CN102694122 A CN 102694122A
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ion
tunnel barrier
storage device
voltage
ion storage
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D.赖纳森
C.J.谢瓦利耶
W.金尼
R.兰伯特森
S.W.龙科尔
J.E.小桑切斯
L.施洛斯
P.F.S.斯沃布
E.R.沃德
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Unity Semiconductor Corp
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Abstract

本发明涉及两端可重写非易失性离子传输RRAM器件。该器件包括：可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：具有第一电导率的隧道势垒和离子贮存器，所述离子贮存器包括可移动离子并且具有高于所述第一电导率的第二电导率，所述离子贮存器和所述隧道势垒彼此电相连。

Description

两端可重写非易失性离子传输RRAM器件
本申请是申请号为200580038024.5、申请日为2005年9月1日、发明名称为“使用混合价导电氧化物的存储器”的发明专利申请的分案申请。
技术领域
本发明涉及计算机存储器，并且更具体地涉及非易失性存储器。
背景技术
存储器可分为易失性或者非易失性。易失性存储器是关掉电源时丢失其内容的存储器。相反，非易失性存储器不需要连续的电源以保留信息。大多数非易失性存储器使用固态存储器件作为存储元件。
20世纪60年代以来，出现了描述带有薄绝缘体的金属-绝缘体-金属结构中的开关效应和存储效应的大量文献。具有开创性的作品之一是“薄绝缘膜中新的导电现象及可逆存储现象”(“New Conduction and Reversible Memory Phenomena in Thin Insulating Films”，J.G. Simmons and R.R. Verderber，301 Proc. Roy. Soc. 77-102 (1967))。虽然Simmons和Verderber所描述的机制后来已经受到怀疑，但是他们对该领域的贡献是重大的。
然而，还没有人在商用固态存储器件中成功实施金属-绝缘体-金属结构。在“氧化物及氧化膜”(“Oxides and Oxide Films”，volume 6，edited by A. K. Vijh (Marcel Drekker 1981) 251-325，chapter 4，written by David P. Oxley)正文中完整地专门论述了“氧化膜中的存储效应”(“Memory Effects in Oxide Films”)。Oxley在文中说：“或许令人悲哀的是不得不记录：尽管经过10年的努力，这些氧化物开关的应用数量仍如此有限。”他然后描述：“展望任何应用之前需要谨慎。只有在理解了开关动作的物理性质时才运用这种谨慎；反过来，这必须等待对所展望的用于商业用途的任何开关中运行的传输机制的充分认识。”
在2002年，在写该章后过了二十年，Oxley在“电铸金属-绝缘体-金属结构：综合模型”(“The Electroformed metal-insulator-metal structure: A comprehensive model”，R.E. Thurstans and D. P. Oxley 35 J. Phys. D. Appl. Phys. 802-809)中重新论述了这个主题。在该文中，作者描述了一种模型，该模型将传导过程等同于“在成形过程中所产生的金属岛之间的受陷阱控制并且是热激发的隧穿”。“成形”(或者“电铸”)描述为“电场引起的金属阳极材料通过电介质的局部丝状运动。此处，重要的是注意蒸发电介质可能含有空位并偏离了化学计量。当结果的穿过电介质的细丝载有足够的电流时，它们裂开并留下金属岛结构嵌在电介质中。通过激发隧穿，通过这种结构形成电子传导是可能的。”
然而，作者警告，“成形过程复杂，并且本质上是可变的。当暴露在水蒸汽、有机物类和氧等中时，隧穿势垒(tunneling barrier)还易受到其特性变化的影响。因此，不可期望所制造的器件特性始终如一，或者在没有钝化、有效的封装以及对成形过程的动力学的更好理解的情况下而能够长时间稳定。”
在表面上无关的研究中，某些导电金属氧化物(CMO)已经确定为在暴露于电子脉冲之后呈现存储效应。2001年3月20颁予Liu等人的美国专利6204139描述一些呈现存储特性的钙钛矿材料。相同的研究员在2000年3月8日的Applied Physics Letters, Vol. 76, No. 19的“磁阻薄膜中电脉冲感应的可逆电阻变化效应”(“Electric-pulse-induced reversible resistance change effect in magnetoresistive films”，Applied Physics Letters，Vol. 76，No. 19，8 May 2000)中，以及在2001年的非易失性存储技术会(2001 Non-Volatile Memory Technology Symposium)的材料中的“非易失性存储器的新概念：大磁阻薄膜中电脉冲感应的电阻变化效应”(“A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films”)中，也描述了钙钛矿材料。
在Hsu等人的名为“电可编程电阻交叉点存储器”(“Electrically programmable resistance cross point memory”)美国专利6531371中，公开了电阻交叉点存储器件及其制造和使用方法。存储器件包括置于上电极和下电极之间的钙钛矿材料活性层。
类似地，IBM苏黎世研究中心(IBM Zurich Research Center)也已出版了三篇论述将金属氧化物材料用于存储应用的技术论文：“用于存储应用的薄氧化膜中的具有重现性的开关效应”(“Reproducible switching effect in thin oxide films for memory applications”，Applied Physics Letters，Vol. 77，No. 1，3 July 2000)，“铬掺杂的SrTiO3单晶中电流驱动的绝缘体-导体转变以及非易失性存储”(“Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals”，Applied Physics Letters，Vol. 78，No. 23，4 June 2001)，以及“双稳态开关期间穿过金属-绝缘体-金属结构的电流分布”( “Electric current distribution across a metal-insulator-metal structure during bistable switching”，Journal of Applied Physics，Vol. 90，No. 6，15 September 2001)。
持续努力以将固态存储器件结合到商用非易失性RAM中。
发明内容
本发明提供一种存储器件，包括：可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：具有第一电导率的隧道势垒和离子贮存器，所述离子贮存器包括可移动离子并且具有高于所述第一电导率的第二电导率，所述离子贮存器和所述隧道势垒彼此电相连。
本发明还提供一种存储器件，包括：可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：具有第一电导率的隧道势垒和离子贮存器，所述隧道势垒具有隧道势垒宽度、隧道势垒高度或二者，所述离子贮存器包括可移动离子并且具有高于所述第一电导率的第二电导率，所述离子贮存器和所述隧道势垒彼此电相连，所述离子贮存器包括与所述隧道势垒相邻并且对施加于所述ME的所述两个端子两端的写入电压响应的低电导率区，以及所述低电导率区可操作用于形成大于所述隧道势垒的所述隧道势垒宽度的有效隧道势垒宽度。
本发明又提供一种两端电器件，包括：可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：隧道势垒和离子贮存器，所述离子贮存器包括可移动离子，所述离子贮存器和所述隧道势垒彼此电相连，所述隧道势垒由是所述可移动离子的电解质的材料制成，并且仅当将写入电压施加于所述ME的所述两个端子两端时，所述隧道势垒才是所述可移动离子的至少一部分可渗透的，以及所述ME在施加于所述两个端子两端的读取电压下具有第一电导率，并且在将写入电压施加于所述两个端子两端之后在所述读取电压下具有第二电导率。
本发明还提供一种正好具有两个端子的电器件，包括：具有少于大约50埃的厚度的隧道势垒，所述厚度配置用于在读取操作和写入操作期间的电子隧穿；和包括可移动离子的离子贮存器，所述离子贮存器与所述隧道势垒电相连，所述隧道势垒由是所述可移动离子的电解质的材料制成，并且仅在所述写入操作期间，所述隧道势垒才是所述可移动离子可渗透的，以及其中，与所述隧道势垒电相连的所述离子贮存器在读取电压下具有第一电导率，而在施加写入电压之后在所述读取电压下具有第二电导率。
附图说明
结合附图，参照以下描述可以最好地理解本发明，其中：
图1A示出示范性采用单层存储器的交叉点存储器阵列的透视图；
图1B示出示范性采用四层存储器的叠式交叉点存储器阵列的透视图；
图2A示出在图1A中所示的交叉点阵列中选择存储单元的俯视图；
图2B示出图2A中所示的所选存储单元的边界的透视图；
图3示出可用于晶体管存储器阵列的存储单元的通用横截面表示；
图4A示出示范性1MB存储器的典型实施的方框图；
图4B示出包括能够读取多位的读出电路的示范性存储器的方框图；
图5A示出表示存储元件的一个实施例的基本组件的方框图；
图5B示出两端存储单元中图5A的存储元件的方框图；
图5C示出三端存储单元中图5A的存储元件的方框图；
图6A示出图5B的存储单元的方框图，在该存储单元中，氧运动产生了低电导率氧化物；
图6B示出图5B的存储单元的方框图，在该存储单元中，低电导率氧化物是自限性的；
图7示出使用另一存储元件实施例的两端存储单元的方框图；
图8A示出图7的存储单元的方框图，在该存储单元中，在混合价氧化物中形成了低电导率区；以及
图8B示出包括氧储存器的图8A的存储单元的方框图。
将理解，附图中，相似的参考数字指示相似的结构元件。同样，应理解，图中的描绘不必按照比例绘制。
具体实施方式
以下描述中，阐述了许多特定细节以提供对本发明的透彻理解。然而，对于本领域技术人员将很显然，在没有一些或者所有这些特定细节的情况下，本发明也可实施。在其它例子中，为了避免不必要地使本发明难于理解，并未详细描述已熟知的工艺步骤。
存储器阵列
常规的非易失性存储器需要三端的基于MOSFET的器件。这种器件的布局并不理想，每个存储单元通常需要至少8f2的面积，其中f是最小特征尺寸。然而，并不是所有的存储元件都需要三个端子。例如，如果存储元件能够响应电压脉冲而改变它的电性质(例如，电阻率)，则只需要两个端子。在只有两个端子的情况下，可利用允许将单个单元制造为4f2的大小的交叉点阵列布局。如果使用叠式交叉点阵列或者每单元多位，可以达到1f2的大小或者更小。使用每单元两位以及四层叠式交叉点阵列，可以达到0.25f2的有效面积。
图1A示出采用单层存储器的示范性交叉点存储器阵列100的透视图。底层的x方向的导电阵列线105与顶层的y方向的导电阵列线110正交。x方向的导电阵列线105作为多个位于导电阵列线105和110的交叉处的存储栓(memory plug)115的第一端子，而y方向的导电阵列线110作为第二端子。导电阵列线105和110用于将电压脉冲递送给存储栓115并运送电流通过存储栓115以确定它们的阻态。
导电阵列线层105和110通常可由任何导电材料制成，如铝、铜、钨或者某些陶瓷。取决于材料，导电阵列线通常会与64至8192条垂直的导电阵列线相交。制造技术、特征尺寸以及材料的电阻率可允许较短的或者较长的线。虽然x方向和y方向的导电阵列线可为相同长度(形成正方形的交叉点阵列)，它们还可为不同长度(形成长方形交叉点阵列)，如果它们由具有不同电阻率的不同材料制成，这可能是有用的。
图2A示出在交叉点阵列100中选择存储单元205。在单条x方向的导电阵列线210和单条y方向的导电阵列线215之间的交叉点唯一地确定单个存储单元205。图2B示出所选存储单元205的边界。存储单元是理论上可扩展为一维、二维或者甚至三维的可重复单元。在z方向(与x-y平面正交)上重复存储单元的一个方法是使用导电阵列线105和110的底面和顶面，形成叠式交叉点阵列。
图1B示出采用四个存储层155、160、165以及170的示范性叠式交叉点阵列150。存储层夹在x方向的导电阵列线175、180以及185和y方向的导电阵列线190以及195的交替层之间，以使每个存储层155、160、165以及170只与一个x方向的导电阵列线层和一个y方向的导电阵列线层相关联。虽然顶部导电阵列线层185和底部导电阵列线层175只用于为单个存储层155和170提供电压，但是其它导电阵列线层180、190以及195可用于为顶部和底部存储层155、160、165或者170提供电压。在这种构造中，会需要n+1个导电阵列线层，此处n表示存储层的数量。或者，每个存储层可具有其自己的x方向和y方向的导电阵列线的唯一集合，然而，这会增加层的总数，因为需要2n个导电阵列线层和使一个导电阵列线层与相邻的导电阵列线层电隔离的电介质。
返回参照图2B，构成交叉点阵列100的可重复单元可认为是存储栓255加上存储栓周围空间的1/2加上x方向的导电阵列线210的1/2以及y方向的导电阵列线215的1/2。当然，导电阵列线的1/2仅仅是理论上的结构，因为导电阵列线通常会制造为相同的宽度，而不管是使用了导电阵列线的一个表面还是两个表面。因此，最顶和最底的导电阵列线层(只使用一个表面)通常会制造成与所有其它导电阵列线层同样的大小。
交叉点阵列的一个益处是驱动交叉点阵列100或者150的有源电路可置于交叉点阵列的下方，因而减少半导体衬底上所需的覆盖面积。然而，交叉点阵列不是可供两端存储元件使用的唯一的存储器阵列类型。例如，二维晶体管存储器阵列可包含两端存储元件。虽然这种阵列中的存储元件会是两端器件，但是整个存储单元会是三端器件。
图3是可用在晶体管存储器阵列中的存储单元300的通用图形表示。每个存储单元300包括晶体管305和存储栓310。晶体管305用于当将适当的电压施加于选择线320时允许来自数据线315的电流进入存储栓310，选择线320也是晶体管的栅极。如果将相邻的单元布局为彼此的镜像，参考线325可能跨过两个单元。
存储器芯片构造
图4A是示范性1MB存储器400A的典型实施的方框图。物理布局可能不同，但是每个存储位块405可在半导体衬底的分立部分上形成。进入存储器400A的输入信号可包括地址总线430、控制总线440、一些电源450(通常Vcc以及接地—总线450的其它信号可由1MB存储器400A内部产生)以及数据总线460。控制总线440通常包括用于执行以下操作的信号：选择芯片、通知是应执行读取还是写入操作以及当芯片处于读取模式时启用输出缓冲器。地址总线430规定访问存储器阵列中的哪个位置—一些地址到X块470(通常包括预解码器和X解码器)以从水平阵列线中选择一条线。另一些地址到Y块480(通常包括预解码器和Y解码器)以将适当的电压施加于特定的垂直线。每个存储位块405对存储芯片的数据总线460的一条线进行操作。
从存储器阵列420读取数据相对简单：使x线通电，并且由读出电路410在通电的y线上读出电流并将其转换为信息位。图4B是包括能够读取多位的读出电路415的示范性存储器400B的方框图。同时读取多位涉及同时读出来自多条y线的电流。
在写入操作期间，将来自数据总线460的数据施加于所选垂直线或者位线的输入缓冲器和数据驱动器490。具体地，当将二进制信息发送到存储器芯片400B时，它通常存储在电路495内的锁存电路中。在电路495内，每条y线可具有关联的驱动器电路；或者，如果组中的未选线不会使未选存储栓经历任何电阻变化，这通常通过将非选线保持在恒定电压来实现，则一组y线可共享单个驱动器电路。例如，在交叉点阵列中可能有1024条y线，并且页面寄存器可包括8个锁存器，在这种情况下，y块会解码128条y线中的一条，并将所选线连接到块495。然后，驱动器电路将1或者0写入到适当的存储栓。写入操作可用多个周期执行。在2004年5月3日提交的PCT专利申请PCT/US04/13836中描述的方案中，所有的1可在第一周期期间写入，而所有的0可在第二周期期间写入。如下所述，某些存储栓可具有多个不同的稳定阻态。使用这种多级电阻存储栓，通过改变写入电压的量值或者脉冲长度，驱动器电路可例如编程状态00、01、10或者11。
应注意，可扩展这种结构以形成存储器，其中，与如上所述具有多个阵列或者存储位块相比，一个阵列处理数据总线的所有位。例如，如果数据总线或者还被称为数据宽度的存储数据组织是16位宽，则一个交叉点阵列的y块可制造成同时对16条线解码。通过应用同时读取和2周期写入的技术，这种仅有一个阵列的存储器芯片可读取并编程16位的字。
存储栓
每个存储栓包含数层可能对于制造或者功能是理想的材料。例如，对于某个范围的电压(VNO-至VNO+)呈现极高的阻态而对于高于以及低于该范围的电压则为极低的阻态的非欧姆特性可能是理想的。在交叉点阵列中，如果两个电压的一半都在电压VNO-至VNO+的范围内，非欧姆特性可防止读取和写入期间的泄漏。如果每条导电阵列线运送1/2VW，则电流通路会是在这两条各自运送1/2VW的导电阵列线的交叉处的存储栓。另一些存储栓会因非欧姆特性而呈现如此高的电阻，以致电流不会流过半选中的栓。
非欧姆器件可能用于使存储栓呈现非线性电阻特性。示范性非欧姆器件包括三层膜的金属-绝缘体-金属(MIM)结构以及背对背的串联二极管。此外，多个背对背的隧穿电介质还可提供必需的性质。然而，分立的非欧姆器件可能不是必需的。存储栓的某些制造可使非欧姆特性给予存储单元。虽然在某些阵列中非欧姆特性可能是理想的，但在其它阵列中可能不需要它。
电极将通常是存储栓的理想组件，一对电极使存储元件夹在中间。如果电极只用于作为防止金属相互扩散的势垒，那么可以使用薄的非活性金属层，例如，TiN、TaN、Pt、Au，以及某些金属氧化物。然而，电极可提供除仅作为金属相互扩散势垒之外的优点。电极(用单层或者多层形成的)可执行各种功能，包括：防止金属、氧、氢以及水的扩散；作为种子层以与其它层形成好的晶格匹配；作为粘附层；降低因不均匀的热膨胀系数所导致的应力；以及提供其它益处。此外，电极层的选择可能影响存储栓的存储效应性质并且成为存储元件的部分。
“存储元件电极”是存储元件夹在其间的电极(或者，在某些环境下，导电阵列线的一部分)。如本文所使用的，存储元件电极是允许其它组件电连接到存储元件的电极。应注意，不管存储单元有多少个端子，交叉点阵列和晶体管存储器阵列都正好具有两个存储元件电极，这是因为存储栓正好具有两个端子。如前所述，存储单元是可包括附加选择器件(例如，一个或者多个晶体管)的可重复单元。因此，交叉点阵列中的存储单元可包括(a)一个或者多个在正常运行状态期间对单元的电导变化有相当贡献的存储元件，(b)正好两个可能可与其它元件分开识别或者可能不可与其它元件分开识别的存储元件电极，(c)非欧姆器件，以及(d)正好两个导电线路的部分。一个晶体管存储器阵列中的存储单元可包括(a)一个或者多个存储元件，(b)正好两个存储元件电极，以及(c)具有源极、漏极和栅极的晶体管以及关联的导电线路。本领域技术人员将理解，在一个晶体管存储器阵列的情况下，一个或者多个存储元件连同正好两个存储元件电极可耦合到晶体管的源极、漏极或者栅极。
存储效应
存储效应是在施加电压时呈现阻态变化同时允许非破坏性读取的滞后。非破坏性读取意指读取操作对存储元件的阻态没有影响。测量存储单元的电阻通常通过在将存储单元保持在已知电压之后检测电流来完成，或者在已知电流流过存储单元之后检测电压来完成。因此，在施加-VW时位于高阻态R0以及在施加+VW时位于低阻态R1的存储单元应不受在-VR或者+VR执行的读取操作的影响。在这种材料中，写入操作不必在读取操作之后。应理解，|-VR|的量值不一定等于|+VR|的量值。
此外，可能的是，具有可在相同极性的电压下在阻态之间转换的存储单元。例如，在论文“电铸金属-绝缘体-金属结构：综合模型”中，Thurstans和Oxley描述了一种在到达某一VP之前一直维持低阻态的存储器。在到达VP之后，阻态可随着电压而增加。在编程之后，然后在到达VT之前一直维持高阻态。VT对从存储单元除去编程电压的速度敏感。在这种系统中，编程R1会使用电压脉冲VP来实现，编程R0会使用大于VP的电压脉冲来实现，并且在电压低于VT时会进行读取。中间阻态(对于多级存储单元)也是可能的。
存储栓的R1态可能具有的最好的值是10kΩ至100kΩ。如果R1态的电阻远低于10kΩ，电流消耗将增加，因为单元的电流高，并且寄生电阻的影响将较大。如果R1态的值远大于100kΩ，RC延迟将增加存取时间。然而，通过适当的结构改进，可使用的单态电阻值还可以使用从5kΩ至lMΩ以及更大的电阻来获得。通常，单态存储器会具有以因数10隔开的工作电阻R0和R1。
由于存储栓可置于几个不同的阻态中，多位电阻存储单元是可能的。大于因数10的存储栓的电阻性质变化在多位电阻存储单元中可能是理想的。例如，存储栓可能具有高阻态R00、中高阻态R01、中低阻态R10以及低阻态R11。由于多位存储器的存取时间通常长于单位存储器，使用大于10倍的从R11至R00的电阻变化因数是一种使多位存储器和单位存储器一样快的方法。例如，能够存储两位的存储单元可能使低阻态与高阻态以因数100隔开。能够存储三位或者四位信息的存储单元可能需要低阻态与高阻态以因数1000隔开。
使用隧穿形成存储效应
隧穿是在存在电场的情况下电子穿过势垒的过程。隧穿按指数规律取决于势垒的宽度和其高度的平方根。势垒高度通常定义为第一导电材料的费米能量与第二绝缘材料的能带边缘之间的电势差。费米能量是指在该能量，电子态的占据概率为50%。势垒宽度是绝缘材料的物理厚度。
如果将载流子或者离子引入到第二材料中，形成附加电场，则可能修改势垒高度。如果势垒物理上改变形状，或者生长或者收缩，则可以改变势垒的宽度。在存在高电场的情况下，两种机制都可能引起电导率的变化。
虽然以下论述主要集中在有目的地修改势垒宽度，但是本领域技术人员应理解，可以存在其它机制，包括但不局限于：势垒高度修改、载流子电荷陷获空间电荷限制电流、热离子发射限制传导和/或电热Poole-Frenkel发射。
图5A是表示存储元件500的一个实施例的基本组件的方框图，图5B是二端存储单元中的存储元件500的方框图，而图5C是三端存储单元中的图5A的存储元件实施例的方框图。
图5A示出电解隧道势垒(electrolytic tunnel barrier)505以及离子贮存器(ion reservoir)510，它们是存储元件500的两个基本组件。图5B示出顶部存储器电极515和底部存储器电极520之间的存储元件500。存储元件的取向(即，电解隧道势垒505是靠近顶部存储器电极515还是底部存储器电极520)对加工考虑可能是重要的，包括种子层的必要性以及淀积期间隧道势垒如何与离子贮存器510起反应。图5C示出三端晶体管器件中取向为电解隧道势垒505在底部上的存储元件500，该三端晶体管器件具有源存储元件电极525，栅存储元件电极530以及漏存储元件电极535。在这种取向中，电解隧道势垒505还可起栅氧化物的作用。
往回参照图5A，电解隧道势垒505将通常是介于10和低于50埃之间。如果电解隧道势垒505远大于50埃，那么对于大多数电子器件，形成经隧穿使电子运动穿过存储元件500所必需的电场所需的电压变得太高。取决于电解隧道势垒505的材料，对于小尺寸器件(大约几百纳米)中要求快速存取时间(大约几十纳秒，通常小于100ns)的电路，优选的电解隧道势垒505的宽度可能介于15和40埃之间。
基本上，电解隧道势垒505是电子绝缘体，并且是离子电解质。如本文所使用的，电解质是任何在正电极和负电极之间提供离子传输机制的介质。适合一些实施例的材料包括各种金属氧化物，如Al2O3、Ta2O5、HfO2以及ZrO2。一些如氧化锆的氧化物可能用另一些如CaO、MgO或者Y2O3的氧化物部分或者完全稳定，或者掺杂有如钪的材料。在一些实施例中，电解隧道势垒505可能允许离子从离子贮存器行进一直到达电解隧道势垒505的另一侧。在其它实施例中，离子可能只行进仅一段短距离，进入电解隧道势垒505，在正常工作期间从不到达另一侧。
电解隧道势垒505将通常具有极高的质量，尽可能地均匀以允许对获得通过存储元件500的电流所需的电压的可预计性。虽然原子层淀积和等离子体氧化是可用于形成极高质量的隧道势垒的方法的例子，但是特殊系统的参数将规定其制造选项。虽然如2004年5月3日提交的PCT专利申请PCT/US04/13836所述，通过允许活性金属仅仅与离子贮存器510接触就可获得隧道势垒，但是这种势垒可能缺乏均匀性，这在一些实施例中可能是重要的。因此，在本发明的优选实施例中，隧道势垒在制造期间不与离子贮存器510起显著反应。
使用标准设计，在电解隧道势垒505的电场通常高得足以促使在介于10和50埃之间的厚度的隧穿。由于电解隧道势垒505的相对高的串联电阻，电场通常高于存储元件500中的其它点。电解隧道势垒505的高电场还穿入离子贮存器510至少一个德拜长度。德拜长度可定义为局部电场影响自由电荷载流子分布的距离。在适当的极性，离子贮存器510内的电场使离子(可以带正电或者带负电)从离子贮存器510运动穿过电解隧道势垒505，电解隧道势垒505是离子电解质。
离子贮存器510是有足够的导电性以允许电流流过并具有可移动离子的材料。例如，离子贮存器510可以是具有可移动氧离子的氧贮存器。氧离子是电负性的(阴离子)，并且将逆着电流的方向流动。
图6A是氧贮存器635与互补贮存器(complementary reservoir)615之间的氧化还原反应产生低电导率氧化物640的方框图。在离子贮存器510由负氧离子组成的情况下，适当的互补贮存器615会是带正电的离子。此外，图6A中所示实施例的互补贮存器615在其非氧化态下应是导电的，并且在其氧化态下呈现低电导率。因此，许多导电材料(包括碱金属、碱土金属、过渡金属以及其它金属)可作为互补贮存器615。为便于制造，互补贮存器615可为与用于电解隧道势垒505的同样材料的非氧化形式。
当在电解隧道势垒505两端施加电场时，电场会穿入氧贮存器635至少一个德拜长度。带负电的氧离子(阴离子)迁移穿过电解隧道势垒505以在互补贮存器615中与带正电的金属离子(阳离子)结合，形成低电导率氧化物640。此低电导率氧化物640利用电解隧道势垒505来累积，强制电子隧穿一段更长的距离到达导电的互补贮存器615。由于势垒宽度对隧穿的指数效应，低电导率氧化物640可仅为几埃宽，而对存储元件的有效电阻仍具有很明显的影响。
本领域技术人员应理解，氧化还原反应可发生在电解隧道势垒505的顶面或者底面。如果互补离子穿过电解隧道势垒505的迁移率大于氧离子的迁移率，则低电导率氧化物640将在电解隧道势垒505的顶部形成。相反，如果氧离子穿过电解隧道势垒505的迁移率大于互补离子的迁移率，那么低电导率氧化物640将在电解隧道势垒505的底部形成。
金属氧化物的稳定性将取决于它的活化能。对于许多金属氧化物，如Hf和Al，使氧化还原反应逆向进行需要大量的能量，从而使具有如此高活化能的单元便于用作一次性可编程存储器。具有低活化能的氧化物，如RuOx和CuOx，通常对于可重编程存储器是理想的。
一种优化会是使用在读取期间对读取扰动不太敏感的极性。对于一次写入存储器，这可能与写入极性互补。或者，可使用交变的读取极性。对于某些实施例，另一种优化可为限制互补贮存器615的大小。
图6B是制造成自限性的互补贮存器615的方框图。由于只淀积了少量的互补贮存器615，可用于与自由氧离子结合的正离子量是有限的。一旦消耗了互补贮存器615中的所有自由离子，就可能不再形成低电导率氧化物640。在这种实施例中，底部存储元件电极520，或者另一层，可作为氧势垒以防止过量氧漏入系统的其余部分。
在大多数情况下，隧穿势垒的有效宽度只受限于贮存器615和635中离子的可用性(availability)。由于可以形成许多不同的势垒宽度，使用不同的阻态可以容易地实施每单元多位。
往回参照图5A，某些离子贮存器510具有在缺氧状态下具有较弱导电性的物理性质。具有可移动氧离子并且在缺氧状态下具有较弱导电性的材料的一些例子包括某些钙钛矿(钙钛矿通常为ABX3结构的形式，其中，对于X为氧或者为氟的情况，A的原子大小为1.0-1.4Å，而B的原子大小为0.45-0.75Å)，如SrRuO3(SRO)、Pr0.7Ca0.3MnO3、Pr0.5Ca0.5MnO3以及其它PCMO。这些离子贮存器510中许多都可能是混合价氧化物。例如，PCMO中Pr与Ca的比率将规定Mn3+态的锰离子与Mn4+态的锰离子的比率。当在电场下在PCMO中产生氧空穴时，Mn3+与Mn4+的比率将增加。在某些化学计量中，Mn3+的浓度增加会导致材料的导电性较弱。
利用氧耗尽形成存储效应
图7是表示两端存储单元中存储元件700的另一实施例的方框图，其中，在其它导电材料中的氧耗尽低电导率区715形成存储效应的主要部分。图7示出混合价氧化物710以及电解隧道势垒705，它们是在顶部存储器电极515和底部存储器电极520之间的存储元件700的两个基本组件。如和图5A的实施例一样的，存储元件的取向对于加工考虑可能是重要的。应理解，与图5C中所示的相似，存储元件还可用在三端存储单元中。
在这些实施例中，离子短缺(在图7的实施例中是氧)将导致其它导电材料的导电性变弱。混合价氧化物710将通常是晶体，要么是单晶结构，要么是多晶结构。在一个特定实施例中，晶体结构维持其在两种价态下的基本结晶性(有某种程度的变形)。通过维持其结晶性，既可降低存储元件上的物理应力，也可更容易实现过程的可逆性。
在图8A中，电解隧道势垒705还作为氧储存器，暂时保存氧直到相反极性的电压脉冲将氧推回到混合价氧化物710中。在图8B中，单独的氧储存器720层用于保存氧。氧储存器720可能与前面所描述的互补贮存器615一样，或者甚至与某些类型的氧贮存器635一样，如IrOx。如果氧化还原反应在氧储存器720中形成氧化物，则使氧从氧化物中分离出来所需的活化能将影响存储器是用作一次性可编程存储器还是可重写存储器。
本领域技术人员应理解，混合价氧化物710的氧耗尽低电导率区或者某些类型的互补贮存器的低电导率氧化物可能独立地足以形成可接受的存储效应，或者，如果传导机制不相同(例如，小极化子跳跃穿过氧耗尽低电导率区715，而隧穿穿过低电导率氧化物)，一种机制甚者可能在穿过存储元件500的总传导中占主要地位。因此，可设计存储单元以利用仅一种现象或者另一种现象或者两种现象。
在一个与图8A所示的倒转实施例相似的特定实施例中，底部电极520可能为500埃的铂层，通过以下工艺形成：在450℃、在4毫托的氩中，通过对铂靶施加180瓦进行直流磁控管溅射，然后在4毫托的氩的溅射周围气体环境中原位冷却至少10分钟。
混合价氧化物710可能为500埃的PCMO钙钛矿层，通过以下工艺形成：在550℃、在10毫托的氩中，通过对Pr0.7Ca0.3MnO3靶(用热等压压制或者HIP制成)施加120瓦进行射频磁控管溅射，然后，在10毫托的氩的溅射周围气体环境中原位冷却10分钟，然后在600托的氧的加载互锁真空室(load lock chamber)中另外冷却10分钟。
电解隧道势垒705可能为20或者30埃的某种类型的AlOx，通过以下工艺形成：在300℃、在4毫托的含有1%的氧的氩中，通过对Al2O3靶(也用HIP制成)施加150瓦进行射频磁控管溅射，然后，在4毫托的含有1%的O2的氩的溅射周围气体环境中，在250℃退火30分钟。
如果需要与图8B相似的实施例，200埃的铝金属的氧储存器720可能是通过在25℃、在4毫托的氩中对铝靶施加250瓦进行直流磁控管溅射形成的。
顶部电极515可能为500埃的铂，通过以下工艺形成：在25℃、在4毫托的氩中，通过对铂靶施加180瓦进行直流磁控管溅射。
最后评论
虽然已经以本发明目前预期的最佳模式对其进行了描述，但是很明显，在本领域技术人员的能力和技能范围内，并且无需对其实施更进一步的创造性活动，很容易就可以实现许多修改、工作模式和实施例。例如，虽然将离子贮存器描述为与氧贮存器有关的电负性，但是只要满足特定实施例的其它物理要求，带正电的离子贮存器可能具有相同的功能。此外，虽然上述理论是一种关于各种材料如何相互作用的可能的解释，发明者并不希望受限于任何理论解释。此外，希望受专利证书保护的在权利要求书中提出，并且包括在权利要求书的精神和范围内的所有变化和修改。

Claims (47)

1. 一种存储器件，包括：
可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：
具有第一电导率的隧道势垒，
离子贮存器，所述离子贮存器包括可移动离子并且具有高于所述第一电导率的第二电导率，所述离子贮存器和所述隧道势垒彼此电相连。
2. 如权利要求1所述的存储器件，其中，所述离子贮存器包括基本晶体结构。
3. 如权利要求2所述的存储器件，其中，当将写入电压或读取电压施加于所述ME的所述两个端子两端时，所述离子贮存器保持所述基本晶体结构。
4. 如权利要求1所述的存储器件，其中，所述离子贮存器和所述隧道势垒彼此接触。
5. 如权利要求1所述的存储器件，其中，所述可移动离子包括氧离子。
6. 如权利要求5所述的存储器件，其中，所述离子贮存器包括基本晶体结构并且当所述离子贮存器处于缺氧状态时保持所述基本晶体结构。
7. 如权利要求1所述的存储器件，其中，所述可移动离子包括氧离子，并且通过对所述ME的写入操作使得并非所述离子贮存器的全部处于缺氧状态。
8. 如权利要求1所述的存储器件，其中，所述可移动离子包括氧离子，并且在对所述ME进行写入操作之后，所述离子贮存器的靠近所述隧道势垒的层处于比所述离子贮存器中远离所述隧道势垒的层更缺氧的状态。
9. 如权利要求1所述的存储器件，其中，在对所述ME进行写入操作之后，所述离子贮存器的靠近所述隧道势垒的层呈现比所述离子贮存器中远离所述隧道势垒的层更大的价态变化。
10. 如权利要求1所述的存储器件，其中，所述ME的电导率指示阻态，并且通过将读取电压施加于所述ME的所述两个端子两端而非破坏性地确定所述阻态。
11. 如权利要求1所述的存储器件，其中，所述ME的电导率指示阻态，并且通过将写入电压施加于所述ME的所述两个端子两端，所述阻态可逆地可重写到不同的值。
12. 如权利要求1所述的存储器件，其中，所述可移动离子包括氧离子，并且在所述ME的所述两个端子两端施加写入电压可操作用于在所述离子贮存器和所述隧道势垒之间传输所述氧离子的至少一部分。
13. 如权利要求1所述的存储器件，其中，所述ME配置成存储非易失性数据的至少一位，并且当缺少电源时保留所述数据。
14. 如权利要求1所述的存储器件，其中，所述离子贮存器包括单晶结构。
15. 如权利要求1所述的存储器件，其中，所述隧道势垒具有少于大约50埃的厚度。
16. 如权利要求1所述的存储器件，其中，所述隧道势垒由是所述可移动离子的电解质的材料制成。
17. 如权利要求16所述的存储器件，其中，所述可移动离子包括氧离子。
18. 如权利要求1所述的存储器件，其中，仅当将写入电压施加于所述ME的所述两个端子两端时，所述隧道势垒才是所述可移动离子可渗透的，并且仅当施加所述写入电压时，将所述可移动离子的一部分传输到所述隧道势垒中或传输到所述隧道势垒外才进行。
19. 如权利要求18所述的存储器件，其中，所述可移动离子包括氧离子。
20. 如权利要求1所述的存储器件，其中，成形对所述ME的总电导率的贡献并不显著，其中，成形包括阳极材料在所述离子贮存器内部的局部丝状运动。
21. 如权利要求1所述的存储器件，其中，所述离子贮存器和所述隧道势垒配置成将非欧姆特性给予所述ME，所述非欧姆特性对于施加在所述两个端子两端的第一范围的电压呈现极高的阻态而对于对于施加在所述两个端子两端的高于以及低于所述第一范围的电压的电压则呈现极低的阻态。
22. 一种存储器件，包括：
可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：
具有第一电导率的隧道势垒，所述隧道势垒具有隧道势垒宽度、隧道势垒高度或二者，
离子贮存器，所述离子贮存器包括可移动离子并且具有高于所述第一电导率的第二电导率，
所述离子贮存器和所述隧道势垒彼此电相连，
所述离子贮存器包括与所述隧道势垒相邻并且对施加于所述ME的所述两个端子两端的写入电压响应的低电导率区，以及
所述低电导率区可操作用于形成大于所述隧道势垒的所述隧道势垒宽度的有效隧道势垒宽度。
23. 如权利要求22所述的存储器件，其中，所述ME的电导率指示阻态，并且通过将读取电压施加于所述ME的所述两个端子两端而非破坏性地确定所述阻态，并且当缺少电源时保留所述阻态。
24. 如权利要求22所述的存储器件，其中，施加于所述ME的所述两个端子两端的写入电压可操作用于在所述离子贮存器和所述隧道势垒之间传输所述可移动离子的至少一部分，并且在从所述两个端子除去所述写入电压之后，所传输的可移动离子是静止的。
25. 如权利要求22所述的存储器件，其中，施加于所述ME的所述两个端子两端的第一写入电压可操作用于将所述可移动离子的第一部分从所述离子贮存器传输到所述隧道势垒中，并且施加于所述ME的所述两个端子两端的第二写入电压可操作用于将所述可移动离子的所述第一部分从所述隧道势垒传输到所述离子贮存器中，并且，其中，所述第二写入电压具有与所述第一写入电压的极性相反的极性。
26. 如权利要求25所述的存储器件，其中，所述可移动离子包括氧离子。
27. 如权利要求22所述的存储器件，其中，所述离子贮存器包括选自以下结构的结构：基本晶体结构和单晶结构。
28. 如权利要求22所述的存储器件，其中，所述离子贮存器包括基本晶体结构，并且当将写入电压或读取电压施加于所述ME的所述两个端子两端时保持所述基本晶体结构。
29. 如权利要求22所述的存储器件，其中，成形对所述ME的总电导率的贡献并不显著，其中，成形包括阳极材料在所述离子贮存器内部的局部丝状运动。
30. 如权利要求22所述的存储器件，其中，所述可移动离子包括氧离子。
31. 如权利要求22所述的存储器件，其中，所述离子贮存器和所述隧道势垒配置成将非欧姆特性给予所述ME，所述非欧姆特性对于施加在所述两个端子两端的第一范围的电压呈现极高的阻态而对于对于施加在所述两个端子两端的高于以及低于所述第一范围的电压的电压则呈现极低的阻态。
32. 一种两端电器件，包括：
可重写非易失性存储元件（ME），所述ME正好具有两个端子并且包括与所述两个端子电相连的：
隧道势垒，
离子贮存器，所述离子贮存器包括可移动离子，所述离子贮存器和所述隧道势垒彼此电相连，
所述隧道势垒由是所述可移动离子的电解质的材料制成，并且仅当将写入电压施加于所述ME的所述两个端子两端时，所述隧道势垒才是所述可移动离子的至少一部分可渗透的，以及
所述ME在施加于所述两个端子两端的读取电压下具有第一电导率，并且在将写入电压施加于所述两个端子两端之后在所述读取电压下具有第二电导率。
33. 如权利要求32所述的两端电器件，其中，所述ME的电导率指示阻态，并且通过将所述读取电压施加于所述ME的所述两个端子两端而非破坏性地确定所述阻态，并且当缺少电源时保留所述阻态。
34. 如权利要求32所述的两端电器件，其中，所述写入电压的施加导致所述离子贮存器和所述隧道势垒之间的可移动离子传输。
35. 如权利要求32所述的两端电器件，其中，所述离子贮存器包括选自以下结构的结构：基本晶体结构和单晶结构。
36. 如权利要求32所述的两端电器件，其中，所述离子贮存器包括基本晶体结构，并且当将所述写入电压或所述读取电压施加于所述ME的所述两个端子两端时保持所述基本晶体结构。
37. 如权利要求32所述的两端电器件，其中，成形对所述ME的总电导率的贡献并不显著，其中，成形包括阳极材料在所述离子贮存器内部的局部丝状运动。
38. 如权利要求32所述的两端电器件，其中，所述可移动离子包括氧离子。
39. 如权利要求32所述的两端电器件，其中，所述离子贮存器和所述隧道势垒彼此接触。
40. 一种正好具有两个端子的电器件，包括：
具有少于大约50埃的厚度的隧道势垒，所述厚度配置用于在读取操作和写入操作期间的电子隧穿；和
包括可移动离子的离子贮存器，所述离子贮存器与所述隧道势垒电相连，所述隧道势垒由是所述可移动离子的电解质的材料制成，并且仅在所述写入操作期间，所述隧道势垒才是所述可移动离子可渗透的，以及
其中，与所述隧道势垒电相连的所述离子贮存器在读取电压下具有第一电导率，而在施加写入电压之后在所述读取电压下具有第二电导率。
41. 如权利要求40所述的电器件，其中，与所述隧道势垒电相连的所述离子贮存器的电导率指示阻态，并且在所述读取操作期间非破坏性地确定所述阻态，并且当缺少电源时保留所述阻态。
42. 如权利要求40所述的电器件，其中，所述写入操作导致所述离子贮存器和所述隧道势垒之间的可移动离子传输。
43. 如权利要求40所述的两端电器件，其中，所述离子贮存器包括选自以下结构的结构：基本晶体结构和单晶结构。
44. 如权利要求40所述的两端电器件，其中，所述离子贮存器包括基本晶体结构，并且在所述读取操作和所述写入操作期间保持所述基本晶体结构。
45. 如权利要求40所述的两端电器件，其中，成形对与所述隧道势垒电相连的所述离子贮存器的总电导率的贡献并不显著，其中，成形包括阳极材料在所述离子贮存器内部的局部丝状运动。
46. 如权利要求40所述的两端电器件，其中，所述可移动离子包括氧离子。
47. 如权利要求40所述的两端电器件，其中，与所述隧道势垒电相连的所述离子贮存器给予非欧姆特性，所述非欧姆特性对于施加在所述两个端子两端的第一范围的电压呈现极高的阻态而对于对于施加在所述两个端子两端的高于以及低于所述第一范围的电压的电压则呈现极低的阻态。
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