CN102760712A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN102760712A
CN102760712A CN2012101209335A CN201210120933A CN102760712A CN 102760712 A CN102760712 A CN 102760712A CN 2012101209335 A CN2012101209335 A CN 2012101209335A CN 201210120933 A CN201210120933 A CN 201210120933A CN 102760712 A CN102760712 A CN 102760712A
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China
Prior art keywords
conductive projection
projection
semiconductor packages
semiconductor
semiconductor chip
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Pending
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CN2012101209335A
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English (en)
Inventor
林子闳
许文松
陈泰宇
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MediaTek Inc
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MediaTek Inc
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Publication of CN102760712A publication Critical patent/CN102760712A/zh
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Abstract

本发明提供一种半导体封装。上述半导体封装包括半导体芯片；第一导电凸块和第二导电凸块，分别设置于上述半导体芯片上，其中上述第一导电凸块和上述第二导电凸块的上视面积比值大于1且小于或等于3。本发明提出的半导体封装因导电凸块的面积不同而提高热传导率并降低电阻性，从而改善半导体封装的热电特性。

Description

半导体封装
技术领域
本发明是有关于一种半导体封装，特别是有关于一种半导体封装的导电凸块设计。
背景技术
对传统的半导体封装设计而言，为了多功能芯片而需要增加输入/输出(I/O)连接的数量。上述需求冲击对印刷电路板(PCB)业者造成压力，促使印刷电路板(PCB)业者缩小线宽和间距，或发展出芯片直接黏着(Direct Chip Attach，DCA)的半导体。然而，上述多功能芯片封装因增加了输入/输出(I/O)连接数量会导致热电特性问题，举例来说，散热问题、串扰(crosstalk)、信号传输延迟(Propagation Delay)或射频(RF)电路的电磁干扰等问题。上述热电特性问题会影响产品的可靠度和质量。
因此，在此技术领域中，有需要一种具较佳热电特性的半导体封装。
发明内容
为了要解决多功能芯片封装因增加了输入/输出数量而导致的热电特性问题，本发明提供一种具有更佳热电特性的半导体封装。
本发明的实施方式提供一种半导体封装，上述半导体封装包括半导体芯片；第一导电凸块和第二导电凸块，分别设置于上述半导体芯片上，其中上述第一导电凸块和上述第二导电凸块的上视面积比值大于1且小于或等于3。
本发明的半导体封装因导电凸块的面积不同而提高热传导率并降低电阻性，从而改善半导体封装的热电特性。
附图说明
图1a为本发明的实施方式的半导体封装的剖面图。
图1b为本发明的实施方式的半导体封装的导电凸块的布局。
图2a为本发明另一实施方式的半导体封装的剖面图。
图2b为本发明另一实施方式的半导体封装的导电凸块的布局。
图3a为本发明的另一实施方式的半导体封装的剖面图。
图3b为本发明的另一实施方式的半导体封装的导电凸块的布局。
图4a为本发明更又另一实施方式的半导体封装的剖面图。
图4b为本发明更又另一实施方式的半导体封装的导电凸块的布局。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来称呼特定的组件。本领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此是包含任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表第一装置可直接电气连接于第二装置，或通过其它装置或连接手段间接地电气连接到第二装置。
图1a为本发明的实施方式的半导体封装500a的剖面图。本发明的实施方式的半导体封装500a为倒装封装半导体，其使用铜柱以连接半导体芯片和基板。如图1a所示，本发明的实施方式的半导体封装500a包括半导体芯片310，其具有中间区域302和围绕中间区域302的周围区域304。金属垫202和204属于半导体芯片310的内联线结构(图未显示)的最顶层金属层(uppermost metal layer)。在本实施方式中，配置于中间区域302中的金属垫204是用于传输半导体芯片310的接地(ground)信号或电源(power)信号，而配置于周围区域304中的金属垫202传输半导体芯片310的其他信号。因此，金属垫204可视为接地垫或电源垫，而金属垫202可视为信号垫。在本发明的实施方式中，中间区域302中的金属垫204的最小间距(minimum pitch)可设计大于周围区域304中的金属垫202的最小间距。而周围区域304中的金属垫202的最小间距也可视为半导体封装500a的设计规则的金属垫的最小间距。
如图1a所示，可利用沉积工艺和图案化工艺，顺应地形成第一保护层206，覆盖金属垫202和204。在本发明的实施方式中，第一保护层206可包括氧化物、氮化物或氮氧化物。第一保护层206在金属垫202和204的位置上具有开口，使金属垫202和204的部分从开口分别暴露出来。另外，可利用涂布工艺、图案化工艺和硬化(curing)工艺，形成第二保护层208。在本发明的实施方式中，第二保护层208具有开口，且第二保护层208可包括聚酰亚胺(polyimide)，当半导体芯片310遭受不同种类的环境压力时，第二保护层208可提供可靠的绝缘。部分金属垫202和204的部分分别从第二保护层208的开口暴露出来。在本实施方式中，金属垫204配置于中间区域302中，而金属垫202配置于周围区域304中。
如图1a所示，可利用例如溅镀或电镀法的沉积方式以及后续的非等向蚀刻工艺(anisotropic etching process)，在第二保护层208上形成凸块下金属层(Under Bump Metallurgy layer，UBM layer)210a和210b。上述非等向蚀刻工艺在形成导电柱状物之后进行。同时，凸块下金属层210a和210b位于第二保护层208的开口的侧壁以及底面。在本实施方式中，凸块下金属层210a配置于中间区域302中，而凸块下金属层210b配置于周围区域304中。并且，凸块下金属层210a和210b延伸至第二保护层208的顶面上方。在本发明的实施方式中，凸块下金属层210a和210b由钛层和位于钛层上的铜层构成。在本发明的实施方式中，配置于中间区域302中的凸块下金属层210a的上视形状设计不同于配置在周围区域304中的凸块下金属层210b。举例来说，配置于中间区域302中的凸块下金属层210a的上视形状为圆形，而配置于周围区域304中的凸块下金属层210b为长方形。
如图1a所示，分别在凸块下金属层210a和210b上形成导电柱状物212a和212b，并填充第二保护层208的开口。在本实施方式中，导电柱状物212a配置在中间区域302中，而导电柱状物212b配置在周围区域304中。可利用干膜光阻或液态光阻图案(图未显示)定义导电柱状物212a和212b的形成位置。在本发明的实施方式中，导电柱状物212a和212b可用做为后续形成于其上的导电凸块的焊点(solderjoint)，而导电凸块用于传输半导体芯片310的输入/输出(I/O)信号、接地(ground)信号或电源(power)等信号。因此，导电柱状物212a和212b可帮助增加凸块结构的机械强度。在本发明的实施方式中，导电柱状物212a和212b可由铜形成，以防止在后续回焊工艺(solder re-f1owprocess)中变形。
如图1a所示，可利用电镀方式，分别在导电柱状物212a和212b上形成导电缓冲层214a和214b。在本实施方式中，导电缓冲层214a配置在中间区域302中，而导电缓冲层214b配置在周围区域304中。在本发明的实施方式中，导电缓冲层214a和214b为选择性的组件，其可做为后续形成在其上的导电凸块的种晶层(seed layer)、黏着层和阻障层。在本发明的实施方式中，导电缓冲层214a和214b可包括镍。
如图1a所示，可利用搭配图案化光阻层的电镀工艺或网版印刷工艺形成焊料，接着进行回焊工艺的方式，在导电缓冲层214a和214b上形成导电凸块216a和216b。在本实施方式中，导电凸块216a配置在中间区域302中，而导电凸块216b系配置在周围区域304中。在本发明的实施方式中，电性连接金属垫204的导电凸块216a用于传输半导体芯片310的接地(ground)信号或电源(power)信号，而电性连接金属垫202的导电凸块216b用于传输半导体芯片310的电子信号。在本发明的实施方式中，导电柱状物212a/212b、其上的导电凸块216a/216b和两者之间的导电缓冲层214a/214b(选择性组件)共同构成凸块结构。另外，半导体芯片310和上述凸块结构共同形成本发明的实施方式的半导体封装500a。
图1b为本发明的实施方式的半导体封装500a的导电凸块的布局600a。如图1a和1b所示，注意配置在中间区域302中的每一个导电凸块216a的上视面积A1设计大于配置在周围区域304中的每一个导电凸块216b的上视面积A2，以提高热传导率并降低电阻性，从而改善半导体封装500a的热电特性。在如图1a和1b所示的本发明的实施方式中，每一个导电凸块216a对每一个导电凸块216b的上视面积比值A1/A2大于1且小于或等于3。在本实施方式中，每一个导电凸块216a对每一个导电凸块216b的上视面积比值A1/A2大致上等于1.5。在本发明的实施方式中，配置于中间区域302中的导电凸块216a的上视形状设计不同于配置于周围区域304中的导电凸块216b的上视形状。举例来说，配置于中间区域302中的导电凸块216a的上视形状为圆形，而配置于周围区域304中的导电凸块216b上视形状为长方形。并且，配置于中间区域302中的导电柱状物212a的上视形状设计大致上相同于导电凸块216a。配置在周围区域304中的导电柱状物212b的上视形状设计大致上相同于导电凸块216b。因此，导电柱状物212a的上视形状为圆形，而导电柱状物212b的上视形状为长方形。此外，配置于中间区域302中的每一个导电柱状物212a的上视面积设计大致上等于每一个导电凸块216a的上视面积A1。配置在周围区域304中的每一个导电柱状物212b设计大致上等于每一个导电凸块216b的上视面积A2。因此，如图1a和1b所示的实施方式中，每一个导电柱状物212a对每一个导电柱状物212b的上视面积比值A1/A2大于1且小于或等于3。在本实施方式中，每一个导电柱状物212a对每一个导电柱状物212b的上视面积比值A1/A2大致上等于1.5。
另外，如图1a所示，可将半导体封装500a接合至基板300上，例如可为印刷电路板(PCB)。在本发明的实施方式中，底部填充材料(underfill material)224可选择性填满半导体封装500a和基板300之间的空间。阻焊层(solder resistance layer)222，设置于基板上，位于基板300和半导体芯片310之间的重叠区域之外，且底部填充材料覆盖阻焊层222。在本发明的实施方式中，基板300具有设置于其上的导线230a和230b。在本实施方式中，导线230a配置在中间区域302中，而导线230b配置于周围区域304中。在本发明的实施方式中，可由例如硅的半导体材料或例如双马来酰亚胺-三氮杂苯树脂(BT)、聚亚酰胺(polyimide)或ABF树脂薄膜(ajinomoto build-up film)的有机材料形成基板300。在本发明的实施方式中，配置在中间区域302中的导线230a设计为用于绕线的接地(ground)/电源(power)线段，而配置于周围区域304中的导线230b设计为用于绕线的信号(signal)线段。并且，导线230a和230b可用于直接固接至基板300的半导体芯片310的输入/输出(I/O)连接。因此，每一条导线230a和230b具有一部分，其可视为基板300的垫区域(pad region)。图1b也显示本发明的实施方式的半导体封装500a的导线230a/230b和导电凸块216a/216b之间的关系。中间区域302中的导线230a的末端部分会与导电凸块216a重叠，而周围区域304中的导线230b的末端部分会与导电凸块216b重叠。
在本发明另一实施方式中，金属垫202和金属垫204的位置可以互换。图2a为本发明另一实施方式的半导体封装500b的剖面图。图2b为本发明另一实施方式的半导体封装500b的导电凸块的布局600b。上述图式中的各组件如有与图1a和1b所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。半导体封装500b(布局600b)和半导体封装500a(布局600a)的不同处为半导体封装500b用于电源(power)/接地(ground)连接的金属垫204配置在周围区域304中。并且，半导体封装500b用于信号(signal)连接的金属垫202配置在中间区域302中。因此，对应金属垫204和金属垫202设置的导电凸块216a和216b的位置也会互换，在本实施方式中，具较大上视面积的导电凸块216a配置在周围区域304中，而具较小上视面积的导电凸块216b配置在中间区域302中。
在本发明又另一实施方式中，金属垫202和金属垫204可交错配置在中间区域302和周围区域304两者中。图3a为本发明又另一实施方式的半导体封装500c的剖面图。图3b为本发明又另一实施方式的半导体封装500c的导电凸块的布局600c。上述图式中的各组件如有与图1a和1b所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。如图3a和3b所示，与任一个金属垫202相邻的金属垫为金属垫204。并且，与任一个金属垫204相邻的金属垫为金属垫202。因此，具不同上视面积的导电凸块216a和216b也可同时配置在中间区域302和周围区域304两者中，以对应至金属垫204和金属垫202的位置。
在本发明更又另一实施方式中，金属垫202和金属垫204可同时配置在中间区域302和周围区域304两者中。并且，金属垫202和金属垫204可任意配置在中间区域302或周围区域304中。图4a为本发明更又另一实施方式的半导体封装500d的剖面图。图4b为本发明更又另一实施方式的半导体封装500d的导电凸块的布局600d。上述图式中的各组件如有与图1a和1b所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。如图4a和4b所示，任一个金属垫202可与金属垫202或204相邻。并且，任一个金属垫204也可与金属垫202或204相邻。因此，具不同上视面积的导电凸块216a和216b也可任意配置在中间区域302或周围区域304中，以对应至金属垫204和金属垫202的位置。
本发明实施方式提供一种半导体封装。上述半导体封装设计于同一个半导体封装中配置两种不同面积(尺寸)的导电凸块。因为半导体芯片310的电源(power)/接地(ground)连接的数量远少于信号(signal)连接的数量，所以用于电源(power)/接地(ground)连接的金属垫204的最小间距可设计大于用于信号连接的金属垫202。连接至金属垫204的每一个导电凸块216a的上视面积A1设计大于连接至金属垫202的每一个导电凸块216b的上视面积A2，以增加热传导率(thermalconductivity)且降低电阻性，因而改善半导体封装500a～500d的热电特性。如图1a和1b所示的本发明实施方式中，每一个导电凸块216a对每一个导电凸块216b的上视面积比值A1/A2大于1且小于或等于3。举例来说，每一个导电凸块216a对每一个导电凸块216b的上视面积比值A1/A2大致上等于1.5。在本发明的实施方式中，配置在中间区域302中的导电凸块216a的上视形状设计不同于配置于周围区域304中的导电凸块216b的上视形状。
本领域中技术人员应能理解，在不脱离本发明的精神和范围的情况下，可对本发明做许多更动与改变。因此，上述本发明的范围具体应以后附的权利要求界定的范围为准。

Claims (18)

1.一种半导体封装，包括：
半导体芯片；以及
第一导电凸块和第二导电凸块，分别设置于所述半导体芯片上，其中所述第一导电凸块和所述第二导电凸块的上视面积比值大于1且小于或等于3。
2.如权利要求1所述的半导体封装，其特征在于，所述半导体芯片具有中间区域和围绕所述中间区域的周围区域，且其中所述第一导电凸块设置于所述半导体芯片的所述中间区域，且所述第二导电凸块设置于所述半导体芯片的所述周围区域。
3.如权利要求1所述的半导体封装，其特征在于，所述半导体芯片具有中间区域和围绕所述中间区域的周围区域，且其中所述第一导电凸块设置于所述半导体芯片的所述周围区域，且所述第二导电凸块设置于所述半导体芯片的所述中间区域。
4.如权利要求1所述的半导体封装，其特征在于，所述第一导电凸块和所述第二导电凸块交错设置于所述半导体芯片上。
5.如权利要求1所述的半导体封装，其特征在于，所述第一导电凸块和所述第二导电凸块任意设置于所述半导体芯片上。
6.如权利要求1所述的半导体封装，其特征在于，所述第一导电凸块的上视形状为圆形。
7.如权利要求1所述的半导体封装，其特征在于，所述第二导电凸块的上视形状为矩形。
8.如权利要求1所述的半导体封装，其特征在于，所述第一导电凸块连接所述半导体芯片的电源垫或接地垫。
9.如权利要求1所述的半导体封装，其特征在于，所述第二导电凸块连接所述半导体芯片的信号垫。
10.如权利要求1所述的半导体封装，其特征在于，更包括：
第一凸块下金属层图案，设置于所述半导体芯片和所述第一导电凸块之间；以及
第二凸块下金属层图案，设置于所述半导体芯片和所述第二导电凸块之间。
11.如权利要求10所述的半导体封装，其特征在于，所述第一凸块下金属层图案的上视形状为圆形。
12.如权利要求10所述的半导体封装，其特征在于，所述第二凸块下金属层图案的上视形状为矩形。
13.如权利要求10所述的半导体封装，其特征在于，更包括：
第一导电柱状物，连接所述第一凸块下金属层图案和所述第一导电凸块，且位于所述第一凸块下金属层图案和所述第一导电凸块之间；以及
第二导电柱状物，连接所述第二凸块下金属层图案和所述第二导电凸块，且位于所述第二凸块下金属层图案和所述第二导电凸块之间。
14.如权利要求13所述的半导体封装，其特征在于，所述第一导电柱状物的上视形状为圆形。
15.如权利要求13所述的半导体封装，其特征在于，所述第二导电柱状物的上视形状为矩形。
16.如权利要求13所述的半导体封装，其特征在于，所述第一导电柱状物和所述第二导电柱状物的上视面积比值大于1且小于或等于3。
17.如权利要求1所述的半导体封装，其特征在于，更包括基板，其上具有多个导线，其中所述第一导电凸块和所述第二导电凸块分别接合至所述多个导线上。
18.如权利要求17所述的半导体封装，其特征在于，更包括：
阻焊层，设置于所述基板上，且位于所述基板和所述半导体芯片之间的重叠区域之外；以及
底部填充材料，填满所述基板和所述半导体芯片之间的间隙，且覆盖所述阻焊层。
CN2012101209335A 2011-04-25 2012-04-23 半导体封装 Pending CN102760712A (zh)

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US20120267779A1 (en) 2012-10-25

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