CN102760754A - Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof - Google Patents
Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof Download PDFInfo
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- CN102760754A CN102760754A CN201210271677XA CN201210271677A CN102760754A CN 102760754 A CN102760754 A CN 102760754A CN 201210271677X A CN201210271677X A CN 201210271677XA CN 201210271677 A CN201210271677 A CN 201210271677A CN 102760754 A CN102760754 A CN 102760754A
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Abstract
The invention discloses a depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and a manufacturing method thereof. The depletion type VDMOS comprises a first doping substrate of a first doping type, an epitaxial layer of a first doping type, at least two deep traps of a second doping type and two ion injection channel regions of a first doping type, wherein the epitaxial layer is formed on one face of the substrate; the at least two deep traps are formed in the epitaxial layer; and the ion injection channel regions are formed on both sides of each deep trap, and are separated from each other. The channel regions of the depletion type VDMOS provided by the invention are formed through ion injection by adopting a mask layer, so that higher performance can be ensured through an accurate channel region structure and a high-quality grid oxide layer.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, particularly a kind of depletion type VDMOS and manufacturing approach thereof.
Background technology
Vertical double diffusion Metal-Oxide Semiconductor transistor (vertical double-diffusion MOS; VDMOS); Because of it has the advantage of bipolar transistor and common MOS device concurrently, no matter switch application or linear applications, VDMOS is desirable power device.VDMOS is mainly used in electric machine speed regulation, inverter, uninterrupted power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc.VDMOS is divided into enhancement mode VDMOS and depletion type VDMOS.
For depletion type VDMOS; Because in the oxide layer of source-drain electrode, mixed a large amount of ions, even when grid voltage VGS=0, under the effect of the dopant ion of oxide layer; Can induce opposite majority carrier in the underlayer surface and form inversion layer with the substrate doping type; Be to have channel region between source-leakage,, just can produce drain current as long as between source-leakage, add forward voltage; When adding grid voltage VGS, can make majority carrier flow out channel region, inversion layer narrows down the change of channel region resistance greatly, and when grid voltage VGS increased to certain value, inversion layer disappeared, and channel region is by pinch off (exhausting), and depletion type VDMOS can turn-off.
VDMOS is an example with N ditch depletion type, and when grid voltage VGS=0, the channel region between the drain-source exists, so as long as between source-drain electrode, add voltage VDS, source-drain electrode electric current I D circulation is just arranged.If increase grid voltage VGS, the electric field between grid and the substrate will make the more electronics of induction in the channel region, the channel region thickening, and the electricity of channel region is led increase.If add negative voltage at grid, promptly grid voltage VGS＜0 will induce positive charge at the device surface of correspondence, and these positive charges are offset the electronics in the N channel region, thereby produces a depletion layer at substrate surface, and channel region is narrowed down, and the channel region electricity is led and reduced.When minus gate voltage increased to a certain voltage Vp, depletion region expanded to whole channel region, and channel region even at this moment VDS still exists, can not produce drain current, i.e. ID=0 fully by pinch off (exhausting) yet.VP is called pinch-off voltage or threshold voltage.Conventional art is when making depletion type VDMOS; In grid oxic horizon, mix a large amount of cations in advance; When VGS=0, the electric field energy " induction " in P type substrate that these cations produce goes out enough electronics, and perhaps the transmission grating oxide layer is injected phosphonium ion formation N type channel region.
Promptly in conventional art; The method that the channel region of depletion type VDMOS forms through the induction of the dopant ion in the grid oxic horizon; The structure of channel region, position and the degree of depth all are the ion doping situation that depends in the grid oxic horizon, and are not easy to confirm, inject the method for phosphonium ion through gate oxide; Its injection zone not merely is a channel region; Other zone also has phosphonium ion and injects, and can have a negative impact to withstand voltage, the leakage current of device etc., and the gate oxide quality also can be affected owing to ion injects simultaneously.As everyone knows, the breadth length ratio of depletion type VDMOS channel region can influence the mutual conductance of channel region, thereby can influence many important parameters such as saturation current, leakage current and pinch-off voltage of depletion type VDMOS.And the manufacturing approach of traditional depletion type VDMOS is because it controls not accurate enough to the position of channel region and the degree of depth of channel region; Ion injection to oxide layer simultaneously also can cause adverse effect to other zones (for example source region and drain region), thereby can't produce high-quality depletion type VDMOS.
Therefore structure, position and the degree of depth how accurately to control channel region have become a urgent problem in the manufacture process of depletion type VDMOS.
Summary of the invention
The present invention provides a kind of depletion type VDMOS and manufacturing approach thereof, with the purpose of the structure, position and the channel region degree of depth that are able to accurately control channel region.
For solving the problems of the technologies described above, the present invention provides a kind of depletion type VDMOS, comprising:
The doped substrate of one first doping type;
Be formed at the epitaxial loayer of first doping type on the said substrate one side;
Be formed at the deep trap of at least two second doping types in the said epitaxial loayer; And
Be formed at the implanted channel district of two first doping types of each said deep trap both sides, wherein, the length range of said channel region is 1 μ m～3 μ m, and said channel region is separated from each other.
Optional, the distance range between two adjacent said deep traps is 1 μ m～4 μ m.
Optional, the injection ion that forms said channel region exists only in the said channel region.
Optional, said depletion type VDMOS also comprises:
Be formed in the said deep trap and two source regions that are connected with said channel region;
Be formed on the part source region of said grid structure both sides with grid structure on dielectric layer;
Be formed at the source electrode on said deep trap, two source regions and the dielectric layer; And
Be formed at said substrate another side drain electrode.
Optional, said depletion type VDMOS also comprises: be formed at least one potential dividing ring on the epitaxial loayer of said source electrode both sides.
Optional, the doping type in said source region is first doping type, doping content is higher than the doping content of said channel region.
Optional, the material of said source electrode and drain electrode is a kind of of aluminium, copper, gold, silver or several kinds alloy wherein.
Accordingly, the manufacturing approach of a kind of depletion type VDMOS is provided also, comprises:
The doped substrate of one first doping type is provided;
On the one side of said substrate, form the epitaxial loayer of first doping type;
On said epitaxial loayer, form first mask layer;
With said first mask layer is that mask carries out the ion injection first time, in said epitaxial loayer, forms the deep trap of at least two second doping types;
Remove first mask layer;
Carry out the annealing first time;
On said epitaxial loayer and deep trap, form second mask layer, said second mask layer exposes the two side areas of each deep trap; And
With said second mask layer is that mask carries out the ion injection second time, forms the implanted channel district of two first doping types in each said second doping type deep trap two side areas.
Optional, the length range of said channel region is 1 μ m～3 μ m.
Optional, the distance range between two adjacent said deep traps is 1 μ m～4 μ m.
Optional,, said channel region also comprises after forming step:
Remove second mask layer;
Forming oxide layer and polysilicon layer on said each deep trap with on the extension;
Etching is removed partial oxidation layer and polysilicon layer, forms the grid structure of the channel region of the epitaxial loayer that covers fully between adjacent two deep traps and said epitaxial loayer both sides;
Formation covers the 3rd mask layer of each deep trap top, and said the 3rd mask layer exposes the subregion of each deep trap both sides;
With said the 3rd mask layer is mask, and ion injection is for the third time carried out in the subregion of said each deep trap both sides, in each deep trap, forms two source regions that are connected respectively with two channel regions of said deep trap;
Deposition forms dielectric layer on said deep trap, source region and grid structure;
Etching is removed the part dielectric layer, exposes the deep trap surface between two source regions of surface, part source region and each deep trap of each deep trap;
At the said surface, part source region that exposes and deep trap surface and dielectric layer surface formation source electrode;
Said substrate another side is carried out attenuate; And
Form drain electrode at said substrate another side.
Optional, deep trap also comprises before forming after said epitaxial loayer forms:
Form patterned mask in the neighboring area of said epitaxial loayer;
To be mask carry out the 4th secondary ion to said epitaxial loayer injects with said patterned mask, forms on the neighboring area of said epitaxial loayer and form at least one potential dividing ring.
Optional, the energy range that said ion for the third time injects is 100Kev～200Kev, implantation dosage is 1.0E15/cm
2～1.0E16/cm
2The energy range that the said second time, ion injected is 80Kev～200Kev, and implantation dosage is 1.0E12/cm
2～1.0E13/cm
2
Optional, the energy range that the said first time, ion injected is 40Kev～200Kev, implantation dosage is 1.0E13/cm
2～1.0E14/cm
2
Optional, the temperature range of the said annealing first time is 1100 ℃～1200 ℃, the time range of the said annealing first time is 60min～180min.
Optional, also comprise behind the ion implantation step accomplishing for the third time: carry out the annealing second time.
Optional, the temperature range of the said annealing second time is 800 ℃～1000 ℃, the time range of the said annealing second time is 30min～80min.
In the depletion type VDMOS structure in the present invention, its channel region injects formation through using mask layer to carry out ion, and the grid oxic horizon that passing through doping in the nontraditional technology is responded to or inject ion generation channel region through gate oxide.Inject the channel region that generates through using mask layer to carry out ion, can accurately control the position and the structure of channel region through mask layer, the condition of injecting through the adjustment ion is with parameters such as the accurate control channel region degree of depth and doping contents.And; The ion implanted region territory that forms raceway groove among the present invention exists only in channel region, and does not exist ion to inject to grid oxic horizon, so the voltage endurance capability of grid oxic horizon can significantly promote; Do not exist simultaneously the prior art intermediate ion to inject the problems such as leakage current that cause yet; Simultaneously, inject because need not carry out ion to grid oxic horizon, the quality of grid oxic horizon also is guaranteed.The structure and the high-quality grid oxic horizon of accurate channel region can both guarantee high performance depletion type VDMOS.
Description of drawings
Fig. 1-Figure 12 is a section of structure in each step of depletion type VDMOS manufacturing approach of the embodiment of the invention one;
Figure 13-Figure 15 is a section of structure in each step of depletion type VDMOS manufacturing approach of the embodiment of the invention two;
Figure 16 is the vertical view of the depletion type VDMOS structure of the embodiment of the invention two.
Embodiment
Core concept of the present invention is to utilize mask layer to carry out ion to inject the channel region of realizing depletion type VDMOS; Through using mask layer can realize accurately controlling the position and the structure of channel region, the condition of injecting through the adjustment ion is with parameters such as the accurate control channel region degree of depth and doping contents.Structure, position and the degree of depth of accurate channel region can guarantee high performance depletion type VDMOS.
In order to make the object of the invention, technical scheme and advantage are clearer, come further to elaborate below in conjunction with accompanying drawing.
Embodiment one
Shown in figure 12, the depletion type VDMOS of the embodiment of the invention one comprises: N type substrate 101; Be formed at the N type epitaxial loayer 102 on said substrate 101 one sides; Be formed at least two P type doping deep traps 105 in the said N type epitaxial loayer 102; Be formed at two N type implanted channel districts 108 of each deep trap 105 both sides; Be formed on two channel regions 108 of two adjacent deep traps 105 and cover the grid oxic horizon 111 of said two channel regions 108 fully; Be formed at the grid 112 on the said grid oxic horizon 111; Be formed in the said deep trap 105 and two source regions 115 that are connected with said channel region 108; Be formed on the part source region 115 of said grid 112 both sides with grid 112 on dielectric layer 116, be formed at the source electrode 117 on said deep trap 105, part source region 115 and the dielectric layer 116, and be formed at said substrate 101 another sides drain electrode 118.
Below in conjunction with Fig. 1 to Figure 12 each step of the manufacturing approach of the depletion type VDMOS of the embodiment of the invention one is elaborated.
As shown in Figure 1, a N type substrate 101 is provided, growth N type epitaxial loayer 102 on said substrate 101.The thickness of said epitaxial loayer 102 can influence the voltage endurance capability of device, the thicker of epitaxial loayer 102, and the voltage endurance capability of device is high more.For example, when device withstand voltage required to 600V, the thickness range of said epitaxial loayer 102 was 40 μ m～60 μ m.
Then, as shown in Figures 2 and 3, on said epitaxial loayer 102, form patterned first mask layer 103, form first ion and inject window 104; With said first mask layer 103 is that mask carries out the ion injection first time, in said epitaxial loayer 102, forms at least two P moldeed depth traps 105.Distance range between two adjacent said deep traps 105 is 1 μ m～4 μ m.In the present embodiment, the ion of ion injection for the first time is the boron ion, and the scope of injecting energy is 40Kev～200Kev, and implantation dosage is 1.0E13/cm
2～1.0E14/cm
2Then, remove first mask layer 103.
Accomplish after the ion injection for the first time, carry out the annealing first time, the temperature range of the said annealing first time is 1100 ℃～1200 ℃, and the time range of the said annealing first time is 60min～180min.
Then; As shown in Figure 4; On said epitaxial loayer 102 and deep trap 105, form patterned second mask layer 106; The both sides that expose deep trap 105 form second ion near the zone outside the deep trap and inject window 107; With said second mask layer 106 is that mask carries out the ion injection second time, is injecting the implanted channel district 108 that window 107 each said deep trap 105 two side areas form two N types doping corresponding to second ion, and the injection ion of said channel region 108 exists only in the said channel region 108.The length range of said channel region 108 is 1 μ m～3 μ m.In the present embodiment, the ion of ion injection for the second time is an arsenic ion, and the energy range of ion injection for the second time is 80Kev～200Kev, and implantation dosage is 1.0E12/cm
2～1.0E13/cm
2Then, remove second mask layer 106.
Then, as shown in Figure 5, deposition forms oxide layer 109 and polysilicon layer 110 on said deep trap 105, channel region 108 and extension 102.In the present embodiment; Oxide layer 109 is a silica; The thickness range of said oxide layer 109 is that the thickness range of
said polysilicon layer is further for
; In order to improve the conductivity of polysilicon; Can carry out ion doping to polysilicon, doping process can adopt POCL3 diffusion technology or ion implantation technology.When adopting the POCL3 diffusion technology, it draws together the square resistance scope in advance is 15 Ω/～30 Ω/.When adopting ion implantation technology, can inject phosphonium ion and inject, the injection energy range is 40Kev～150Kev, and implantation dosage is 1.0E15/cm
2～1.0E16/cm
2
Then, as shown in Figure 6, etching is removed partial oxidation layer 109 and polysilicon layer 110, forms the grid oxic horizon 111 and grid 112 of two channel regions 108 that cover two adjacent deep traps 105 fully.
Then, like Fig. 7 and shown in Figure 8, on said deep trap 105, form patterned the 3rd mask layer 113, expose part deep trap zone, forming for the third time, ion injects window 114; With the 3rd mask layer 113 is mask, carries out ion injection for the third time, in deep trap 105, forms two source regions 115 that are connected with said channel region.Then, remove the 3rd mask layer 113.In the present embodiment, the ion of ion injection for the third time is an arsenic ion, and the energy range of ion injection for the third time is 100Kev～200Kev, and implantation dosage is 1.0E15/cm
2～1.0E16/cm
2After accomplishing the injection of the 3rd ion, carry out the annealing second time, the temperature range of the said annealing second time is 800 ℃～1000 ℃, and the time range of the said annealing second time is 30min～80min.
Then, like Fig. 9 and shown in Figure 10, deposition forms dielectric layer 116 on said deep trap 105, source region 115 and grid 112, and etching is removed the part dielectric layer then, exposes the surface of deep trap 105 and the surface in part source region 115.The material of dielectric layer 116 is a boron-phosphorosilicate glass.
Then, like Figure 11 and shown in Figure 12, form source electrode 117 at the surface of said deep trap 105, the surface and dielectric layer 116 surface depositions in part source region 115.Then, said substrate 101 another sides are carried out attenuate, form drain electrode 118 at said substrate 101 another sides after the attenuate.The material of said source electrode and drain electrode adopts a kind of of conventional aluminium, copper, gold, silver or several kinds alloy wherein.So far, accomplished the manufacturing of depletion type VDMOS shown in figure 12.
Should be understood that, all dopant ions in the foregoing description or doping type are got on the contrary that can obtain another embodiment, this belongs to ordinary skill in the art means, is not giving unnecessary details at this.
Embodiment two
Shown in figure 15, the depletion type VDMOS of the embodiment of the invention two comprises: N type substrate 101; Be formed at the N type epitaxial loayer 102 on said substrate 101 one sides; Be formed at least one potential dividing ring 220 on said N type epitaxial loayer 102 neighboring areas, shown in the figure is the situation of a potential dividing ring; Be formed at the patterned mask 219 on the N type epitaxial loayer 102 of said potential dividing ring 220 both sides; Be formed at the high temperature oxide layer 221 on the potential dividing ring 220; Be formed at a plurality of P type doping deep traps 105 in the said N type epitaxial loayer 102 between the said patterned mask 219; Be formed at two N type implanted channel districts 108 of each deep trap 105 both sides; Be formed on two channel regions 108 of two adjacent deep traps 105 and cover the grid oxic horizon 111 of said two channel regions 108 fully; Be formed at the grid 112 on the said grid oxic horizon 111; Be formed in the said deep trap 105 and two source regions 115 that are connected with said channel region 108; Be formed on the part source region 115 of said grid 112 both sides with grid on dielectric layer 116, be formed at the source electrode 117 on said deep trap 105, two source regions 112 and the dielectric layer 116, and be formed at said substrate 101 another sides drain electrode 118.
Below in conjunction with Figure 13 to Figure 15 each step of the manufacturing approach of the depletion type VDMOS of the embodiment of the invention two is elaborated.
At first, shown in figure 13, a N type substrate 101 is provided, growth N type epitaxial loayer 102 on said substrate 101.Forming patterned mask 219 on the said epitaxial loayer on 102.Wherein, The material of said mask 219 is a silica, and the thickness range of said mask 219 is
Then, be that mask carries out the boron ion implantation ion to said epitaxial loayer 102 with patterned mask 219, in said epitaxial loayer 102, form at least one potential dividing ring 220.
Then, shown in figure 14, said epitaxial loayer 220 is carried out high annealing, the boron ion in the potential dividing ring 220 is evenly distributed, and on potential dividing ring 220, form high temperature oxide layer 221.
Then, in the epitaxial loayer 102 in the patterned mask 219 with epitaxial loayer 102 on the step of other parts of formation present embodiment depletion type VDMOS identical with each step of the manufacturing approach of embodiment one, do not giving unnecessary details at this.
Through above-mentioned steps, formed the structure of the depletion type VDMOS of the embodiment of the invention shown in figure 15 two.
Figure 16 is the vertical view of the depletion type VDMOS structure of the embodiment of the invention two.Shown in figure 16, with respect to embodiment one, around whole source electrode 117, increased at least one potential dividing ring 220, separate through mask 219 between said potential dividing ring 220 and the source electrode 117.The situation of a potential dividing ring 220 that only illustrates among Figure 16.The potential dividing ring 220 that increases can effectively improve the voltage endurance capability of depletion type VDMOS, and the quantity of potential dividing ring is many more, and its voltage endurance capability is high more.
Should be understood that, all dopant ions in the foregoing description or doping type are got on the contrary that can obtain another embodiment, this belongs to ordinary skill in the art means, is not giving unnecessary details at this.
In sum, in the depletion type VDMOS structure in the present invention, its channel region carries out ion through second mask layer and injects formation, and the grid oxic horizon induction that passing through in the nontraditional technology mixed generates channel region.Inject the channel region that generates through using mask layer to carry out ion, can accurately control the position and the structure of channel region through mask layer, the condition of injecting through the adjustment ion is with parameters such as the accurate control channel region degree of depth and doping contents.And; The ion implanted region territory that forms raceway groove among the present invention exists only in channel region, and does not exist ion to inject to grid oxic horizon, so the voltage endurance capability of grid oxic horizon can significantly promote; Do not exist simultaneously the prior art intermediate ion to inject the problems such as leakage current that cause yet; Simultaneously, inject because need not carry out ion to grid oxic horizon, the quality of grid oxic horizon also is guaranteed.The structure and the high-quality grid oxic horizon of accurate channel region can both guarantee high performance depletion type VDMOS.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (17)
1. a depletion type VDMOS is characterized in that, comprising:
The doped substrate of one first doping type;
Be formed at the epitaxial loayer of first doping type on the said substrate one side;
Be formed at the deep trap of at least two second doping types in the said epitaxial loayer; And
Be formed at the implanted channel district of two first doping types of each said deep trap both sides, wherein, the length range of said channel region is 1 μ m～3 μ m, and said channel region is separated from each other.
2. depletion type VDMOS as claimed in claim 1 is characterized in that, the distance range between two adjacent said deep traps is 1 μ m～4 μ m.
3. depletion type VDMOS as claimed in claim 1 is characterized in that, the injection ion that forms said channel region exists only in the said channel region.
4. depletion type VDMOS as claimed in claim 1 is characterized in that, said depletion type VDMOS also comprises:
Be formed in the said deep trap and two source regions that are connected with said channel region;
Be formed on the part source region of said grid structure both sides with grid structure on dielectric layer;
Be formed at the source electrode on said deep trap, two source regions and the dielectric layer; And
Be formed at said substrate another side drain electrode.
5. depletion type VDMOS as claimed in claim 4 is characterized in that, said depletion type VDMOS also comprises: be formed at least one potential dividing ring on the epitaxial loayer of said source electrode both sides.
6. depletion type VDMOS as claimed in claim 4 is characterized in that, the doping type in said source region is first doping type, and doping content is higher than the doping content of said channel region.
7. depletion type VDMOS as claimed in claim 4 is characterized in that, the material of said source electrode and drain electrode is a kind of of aluminium, copper, gold, silver or several kinds alloy wherein.
8. the manufacturing approach of a depletion type VDMOS is characterized in that, comprising:
The doped substrate of one first doping type is provided;
On the one side of said substrate, form the epitaxial loayer of first doping type;
On said epitaxial loayer, form first mask layer;
With said first mask layer is that mask carries out the ion injection first time, in said epitaxial loayer, forms the deep trap of at least two second doping types;
Remove first mask layer;
Carry out the annealing first time;
On said epitaxial loayer and deep trap, form second mask layer, said second mask layer exposes the two side areas of each deep trap; And
With said second mask layer is that mask carries out the ion injection second time, forms the implanted channel district of two first doping types in each said second doping type deep trap two side areas.
9. the manufacturing approach of depletion type VDMOS as claimed in claim 8 is characterized in that, the length range of said channel region is 1 μ m～3 μ m.
10. the manufacturing approach of depletion type VDMOS as claimed in claim 8 is characterized in that, the distance range between two adjacent said deep traps is 1 μ m～4 μ m.
11. the manufacturing approach of depletion type VDMOS as claimed in claim 8 is characterized in that, after said channel region forms step, also comprises:
Remove second mask layer;
Forming oxide layer and polysilicon layer on said each deep trap with on the extension;
Etching is removed partial oxidation layer and polysilicon layer, forms the grid structure of the channel region of the epitaxial loayer that covers fully between adjacent two deep traps and said epitaxial loayer both sides;
Formation covers the 3rd mask layer of each deep trap top, and said the 3rd mask layer exposes the subregion of each deep trap both sides;
With said the 3rd mask layer is mask, and ion injection is for the third time carried out in the subregion of said each deep trap both sides, in each deep trap, forms two source regions that are connected respectively with two channel regions of said deep trap;
Deposition forms dielectric layer on said deep trap, source region and grid structure;
Etching is removed the part dielectric layer, exposes the deep trap surface between two source regions of surface, part source region and each deep trap of each deep trap;
At the said surface, part source region that exposes and deep trap surface and dielectric layer surface formation source electrode;
Said substrate another side is carried out attenuate; And
Form drain electrode at said substrate another side.
12. the manufacturing approach of depletion type MOS FET as claimed in claim 11 is characterized in that, deep trap also comprises before forming after said epitaxial loayer forms:
Form patterned mask in the neighboring area of said epitaxial loayer;
To be mask carry out the 4th secondary ion to said epitaxial loayer injects with said patterned mask, forms on the neighboring area of said epitaxial loayer and form at least one potential dividing ring.
13. the manufacturing approach of depletion type VDMOS as claimed in claim 11 is characterized in that, the energy range that said ion for the third time injects is 100Kev～200Kev, and implantation dosage is 1.0E15/cm
2～1.0E16/cm
2The energy range that the said second time, ion injected is 80Kev～200Kev, and implantation dosage is 1.0E12/cm
2～1.0E13/cm
2
14. the manufacturing approach of depletion type VDMOS as claimed in claim 8 is characterized in that, the energy range that the said first time, ion injected is 40Kev～200Kev, and implantation dosage is 1.0E13/cm
2～1.0E14/cm
2
15. the manufacturing approach of depletion type VDMOS as claimed in claim 8 is characterized in that, the temperature range of the said annealing first time is 1100 ℃～1200 ℃, and the time range of the said annealing first time is 60min～180min.
16. the manufacturing approach of depletion type VDMOS as claimed in claim 11 is characterized in that, also comprises behind the ion implantation step accomplishing for the third time: carry out the annealing second time.
17. the manufacturing approach of depletion type VDMOS as claimed in claim 16 is characterized in that, the temperature range of the said annealing second time is 800 ℃～1000 ℃, and the time range of the said annealing second time is 30min～80min.
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| CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
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| CN110648921A (en) * | 2019-10-08 | 2020-01-03 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
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| CN103022138A (en) * | 2012-12-26 | 2013-04-03 | 杭州士兰微电子股份有限公司 | High-reliability depletion type power semiconductor device and manufacturing method thereof |
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| CN103094216A (en) * | 2013-01-11 | 2013-05-08 | 无锡华润上华科技有限公司 | Annealing technology of NOR flash memory device and NOR flash memory device |
| CN103208427A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Depleted metal-oxide-semiconductor (MOS) transistor and forming method thereof |
| CN103208427B (en) * | 2013-03-22 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Depletion-type mos transistor and forming method thereof |
| CN104425274A (en) * | 2013-09-03 | 2015-03-18 | 北大方正集团有限公司 | Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor |
| CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
| CN109979801A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN109980010A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of manufacturing method and integrated-semiconductor device of semiconductor devices |
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| CN110648921A (en) * | 2019-10-08 | 2020-01-03 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
| CN110648921B (en) * | 2019-10-08 | 2023-01-24 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
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