CN102760754B - Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof - Google Patents
Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof Download PDFInfo
- Publication number
- CN102760754B CN102760754B CN201210271677.XA CN201210271677A CN102760754B CN 102760754 B CN102760754 B CN 102760754B CN 201210271677 A CN201210271677 A CN 201210271677A CN 102760754 B CN102760754 B CN 102760754B
- Authority
- CN
- China
- Prior art keywords
- depletion type
- deep trap
- channel region
- epitaxial loayer
- type vdmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and a manufacturing method thereof. The depletion type VDMOS comprises a first doping substrate of a first doping type, an epitaxial layer of a first doping type, at least two deep traps of a second doping type and two ion injection channel regions of a first doping type, wherein the epitaxial layer is formed on one face of the substrate; the at least two deep traps are formed in the epitaxial layer; and the ion injection channel regions are formed on both sides of each deep trap, and are separated from each other. The channel regions of the depletion type VDMOS provided by the invention are formed through ion injection by adopting a mask layer, so that higher performance can be ensured through an accurate channel region structure and a high-quality grid oxide layer.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, particularly a kind of depletion type VDMOS and manufacture method thereof.
Background technology
Vertical double diffused metal-oxide semi conductor transistor (vertical double-diffusion MOS, VDMOS), because it has the advantage of bipolar transistor and common MOS device concurrently, no matter switch application or linear applications, VDMOS is desirable power device.VDMOS is mainly used in electric machine speed regulation, inverter, uninterrupted power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc.VDMOS is divided into enhancement mode VDMOS and depletion type VDMOS.
For depletion type VDMOS, because be mixed with a large amount of ion in the oxide layer of source-drain electrode, even if when grid voltage VGS=0, under the effect of the Doped ions of oxide layer, majority carrier contrary to substrate doping type can be induced in underlayer surface and form inversion layer, namely there is channel region between source-leakage, as long as add forward voltage between source-leakage, just can produce drain current; When adding grid voltage VGS, majority carrier can be made to flow out channel region, inversion layer narrows channel region resistance change greatly, and when grid voltage VGS increases to certain value, inversion layer disappears, and channel region is by pinch off (exhausting), and depletion type VDMOS can turn off.
For N ditch depletion type VDMOS, when grid voltage VGS=0, the channel region between drain-source exists, as long as so add voltage VDS between source-drain electrode, source-drain electrode just has electric current I D to circulate.If increase grid voltage VGS, the electric field between grid and substrate will make to respond to more electronics in channel region, and channel region is thickening, and the conductance of channel region increases.If add negative voltage at grid, i.e. grid voltage VGS < 0, will induce positive charge at the device surface of correspondence, these positive charges offset the electronics in N channel region, thus producing a depletion layer at substrate surface, channel region is narrowed, and channel region conductance reduces.When minus gate voltage increases to a certain voltage Vp, depletion region expands to whole channel region, and channel region, completely by pinch off (exhausting), even if at this moment VDS still exists, also can not produce drain current, i.e. ID=0.VP is called pinch-off voltage or threshold voltage.Conventional art is when manufacturing depletion type VDMOS, a large amount of cations is mixed in advance in grid oxic horizon, as VGS=0, the electric field energy " induction " in P type substrate that these cations produce goes out enough electronics, or transmission grating oxide layer injects phosphonium ion formation N-type channel region.
Namely in the conventional technology, the method formed is responded in the channel region of depletion type VDMOS by the Doped ions in grid oxic horizon, the structure of channel region, position and the degree of depth are all the ion doping situations depended in grid oxic horizon, and be not easy to determine, the method of phosphonium ion is injected by gate oxide, its injection zone is not merely channel region, other region also has phosphonium ion and injects, can have a negative impact to withstand voltage, the leakage current of device etc., quality of gate oxide also can be affected due to ion implantation simultaneously.As everyone knows, the breadth length ratio of depletion type VDMOS channel region can affect the mutual conductance of channel region, thus can affect saturation current, many important parameters such as leakage current and pinch-off voltage of depletion type VDMOS.And the manufacture method of traditional depletion type VDMOS because its to the position of channel region and the severity control of channel region not accurate enough, also can cause adverse effect to other regions (such as source region and drain region) to the ion implantation of oxide layer simultaneously, thus the depletion type VDMOS of high-quality cannot be produced.
Therefore how accurately to control the structure of channel region, position and the degree of depth and become a urgent problem in the manufacture process of depletion type VDMOS.
Summary of the invention
The invention provides a kind of depletion type VDMOS and manufacture method thereof, with reach accurately can control channel region structure, position and the channel region degree of depth object.
For solving the problems of the technologies described above, the invention provides a kind of depletion type VDMOS, comprising:
The doped substrate of one first doping type;
Be formed at the epitaxial loayer of the first doping type in described substrate one side;
Be formed at the deep trap of at least two the second doping types in described epitaxial loayer; And
Be formed at the implanted channel district of two the first doping types of each described deep trap both sides, wherein, the length range of described channel region is 1 μm ~ 3 μm, and described channel region is separated from each other.
Optionally, the distance range between two adjacent described deep traps is 1 μm ~ 4 μm.
Optionally, the injection ion forming described channel region exists only in described channel region.
Optionally, described depletion type VDMOS also comprises:
Be formed in described deep trap and two source regions be connected with described channel region;
Cover the grid structure of the channel region of epitaxial loayer between adjacent two deep traps and described epitaxial loayer both sides completely;
Dielectric layer on the fractional source regions being formed at described grid structure both sides and on grid structure;
Be formed at the source electrode on described deep trap, two source regions and dielectric layer; And
Be formed at the drain electrode of described substrate another side.
Optionally, described depletion type VDMOS also comprises: be formed at least one potential dividing ring on the epitaxial loayer of described source electrode both sides.
Optionally, the doping type in described source region is the first doping type, and doping content is higher than the doping content of described channel region.
Optionally, the material of described source electrode and drain electrode is a kind of or wherein several alloy of aluminium, copper, gold, silver.
Accordingly, the manufacture method of a kind of depletion type VDMOS is also provided, comprises:
The doped substrate of one first doping type is provided;
The one side of described substrate is formed the epitaxial loayer of the first doping type;
Form the first mask layer on said epitaxial layer there;
Carry out first time ion implantation with described first mask layer for mask, in described epitaxial loayer, form the deep trap of at least two the second doping types;
Remove the first mask layer;
Carry out first time annealing;
Described epitaxial loayer and deep trap are formed the second mask layer, and described second mask layer exposes the two side areas of each deep trap; And
With described second mask layer for mask carries out second time ion implantation, form the implanted channel district of two the first doping types in each described second doping type deep trap two side areas.
Optionally, the length range of described channel region is 1 μm ~ 3 μm.
Optionally, the distance range between two adjacent described deep traps is 1 μm ~ 4 μm.
Optionally, also comprise after the forming step of described channel region:
Remove the second mask layer;
Oxide layer and polysilicon layer is formed on described each deep trap He on epitaxial loayer;
Etching removes portion of oxide layer and polysilicon layer, forms the grid structure of the channel region of epitaxial loayer and the described epitaxial loayer both sides covered completely between adjacent two deep traps;
Form the 3rd mask layer covered above each deep trap, described 3rd mask layer exposes the subregion of each deep trap both sides;
With described 3rd mask layer for mask, third time ion implantation is carried out to the subregion of described each deep trap both sides, in each deep trap, form two source regions be connected respectively with two channel regions of described deep trap;
On described deep trap, source region and grid structure, deposition forms dielectric layer;
Etching removes part dielectric layer, exposes the deep trap surface between the surface, fractional source regions of each deep trap and two source regions of each deep trap;
The surface, fractional source regions exposed described and deep trap surface and dielectric layer surface formation source electrode;
Carry out thinning to described substrate another side; And
Drain electrode is formed at described substrate another side.
Optionally, after described epitaxial loayer is formed, deep trap also comprises before being formed:
Patterned mask is formed in the neighboring area of described epitaxial loayer;
Inject for mask carries out the 4th secondary ion to described epitaxial loayer with described patterned mask, the neighboring area of described epitaxial loayer is formed at least one potential dividing ring.
Optionally, described third time the energy range of ion implantation be 100Kev ~ 200Kev, implantation dosage is 1.0E15/cm
2~ 1.0E16/cm
2; The energy range of described second time ion implantation is 80Kev ~ 200Kev, and implantation dosage is 1.0E12/cm
2~ 1.0E13/cm
2.
Optionally, described first time the energy range of ion implantation be 40Kev ~ 200Kev, implantation dosage is 1.0E13/cm
2~ 1.0E14/cm
2.
Optionally, the temperature range of described first time annealing is 1100 DEG C ~ 1200 DEG C, and the time range of described first time annealing is 60min ~ 180min.
Optionally, also comprise after completing third time ion implantation step: carry out second time annealing.
Optionally, the temperature range of described second time annealing is 800 DEG C ~ 1000 DEG C, and the time range of described second time annealing is 30min ~ 80min.
In depletion type VDMOS structure in the present invention, ion implantation formation is carried out by using mask layer in its channel region, and the grid oxic horizon by doping in nontraditional technology is responded to or generated channel region by gate oxide injection ion.By the channel region using mask layer to carry out ion implantation generation, accurately can be controlled position and the structure of channel region by mask layer, by adjusting the condition of ion implantation accurately to control the parameters such as the channel region degree of depth and doping content.And, the ion implanted regions forming raceway groove in the present invention exists only in channel region, and ion implantation is not existed to grid oxic horizon, therefore the voltage endurance capability of grid oxic horizon can significantly promote, also there is not prior art intermediate ion injects the problems such as the leakage current caused simultaneously, meanwhile, because do not need to carry out ion implantation to grid oxic horizon, the quality of grid oxic horizon have also been obtained guarantee.Structure and the high-quality grid oxic horizon of accurate channel region can both ensure high performance depletion type VDMOS.
Accompanying drawing explanation
Fig. 1-Figure 12 is section of structure in each step of depletion type VDMOS manufacture method of the embodiment of the present invention one;
Figure 13-Figure 15 is section of structure in each step of depletion type VDMOS manufacture method of the embodiment of the present invention two;
Figure 16 is the vertical view of the depletion type VDMOS structure of the embodiment of the present invention two.
Embodiment
Core concept of the present invention is to utilize mask layer to carry out ion implantation to realize the channel region of depletion type VDMOS, by using mask layer can realize the position and the structure that accurately control channel region, by adjusting the condition of ion implantation accurately to control the parameters such as the channel region degree of depth and doping content.The structure of accurate channel region, position and the degree of depth can ensure high performance depletion type VDMOS.
In order to make object of the present invention, technical scheme and advantage clearly, elaborate further below in conjunction with accompanying drawing.
Embodiment one
As shown in figure 12, the depletion type VDMOS of the embodiment of the present invention one comprises: N-type substrate 101; Be formed at the N-type epitaxy layer 102 in described substrate 101 one side; Be formed at least two P type doping deep traps 105 in described N-type epitaxy layer 102; Be formed at the Liang GeNXing implanted channel district 108 of each deep trap 105 both sides; Two channel regions 108 being formed at two adjacent deep traps 105 cover the grid oxic horizon 111 of described two channel regions 108 completely; Be formed at the grid 112 on described grid oxic horizon 111; Be formed in described deep trap 105 and two source regions 115 be connected with described channel region 108; Dielectric layer 116 on the fractional source regions 115 being formed at described grid 112 both sides and on grid 112, is formed at the source electrode 117 on described deep trap 105, fractional source regions 115 and dielectric layer 116, and is formed at described substrate 101 another side drain electrode 118.
Deep trap 105 shown in Figure 12 is two, for depletion type VDMOS, even if two deep traps 105 are also the corresponding functions that can realize depletion type VDMOS, but in actual applications, usual selection hundreds and thousands of deep traps are combined, and are described in the present embodiment with the situation of two deep traps.Should be understood that, for the depletion type VDMOS comprising hundreds and thousands of deep traps, as long as on the basis of the present embodiment, carry out expansion to two deep traps can obtain, for a person skilled in the art, above-mentioned expansion belongs to prior art, is not here described in detail.
Below in conjunction with Fig. 1 to Figure 12, each step of the manufacture method of the depletion type VDMOS of the embodiment of the present invention one is described in detail.
As shown in Figure 1, provide a N-type substrate 101, described substrate 101 grows N-type epitaxy layer 102.The thickness of described epitaxial loayer 102 can affect the voltage endurance capability of device, and the thickness of epitaxial loayer 102 is thicker, and the voltage endurance capability of device is higher.Such as, when device withstand voltage requires as 600V, the thickness range of described epitaxial loayer 102 is 40 μm ~ 60 μm.
Then, as shown in Figures 2 and 3, described epitaxial loayer 102 is formed patterned first mask layer 103, forms the first ion implantation window 104; With described first mask layer 103 for mask carries out first time ion implantation, in described epitaxial loayer 102, form at least two P moldeed depth traps 105.Distance range between adjacent two described deep traps 105 is 1 μm ~ 4 μm.In the present embodiment, the ion of ion implantation is boron ion for the first time, and the scope of Implantation Energy is 40Kev ~ 200Kev, and implantation dosage is 1.0E13/cm
2~ 1.0E14/cm
2.Then, the first mask layer 103 is removed.
After completing first time ion implantation, carry out first time annealing, the temperature range of described first time annealing is 1100 DEG C ~ 1200 DEG C, and the time range of described first time annealing is 60min ~ 180min.
Then, as shown in Figure 4, described epitaxial loayer 102 and deep trap 105 are formed patterned second mask layer 106, the region of both sides outside deep trap exposing deep trap 105 forms the second ion implantation window 107, with described second mask layer 106 for mask carries out second time ion implantation, forming the implanted channel district 108 of two N-types doping corresponding to each described deep trap 105 two side areas of the second ion implantation window 107, the injection ion of described channel region 108 exists only in described channel region 108.The length range of described channel region 108 is 1 μm ~ 3 μm.In the present embodiment, the ion of second time ion implantation is arsenic ion, and the energy range of second time ion implantation is 80Kev ~ 200Kev, and implantation dosage is 1.0E12/cm
2~ 1.0E13/cm
2.Then, the second mask layer 106 is removed.
Then, as shown in Figure 5, in described deep trap 105, channel region 108 and extension 102, deposition forms oxide layer 109 and polysilicon layer 110.In the present embodiment, oxide layer 109 is silica, and the thickness range of described oxide layer 109 is
the thickness range of described polysilicon layer is
further, in order to improve the conductivity of polysilicon, can carry out ion doping to polysilicon, doping process can adopt POCL3 diffusion technology or ion implantation technology.When adopting POCL3 diffusion technology, it draws together square resistance scope is in advance 15 Ω/ ~ 30 Ω/.When adopting ion implantation technology, can inject phosphonium ion and inject, Implantation Energy scope is 40Kev ~ 150Kev, and implantation dosage is 1.0E15/cm
2~ 1.0E16/cm
2.
Then, as shown in Figure 6, etching removes portion of oxide layer 109 and polysilicon layer 110, forms the grid oxic horizon 111 and the grid 112 that cover two channel regions 108 of two adjacent deep traps 105 completely.
Then, as shown in Figure 7 and Figure 8, described deep trap 105 is formed patterned 3rd mask layer 113, exposes part deep trap region, form ion implantation window 114 for the third time; With the 3rd mask layer 113 for mask, carry out third time ion implantation, in deep trap 105, form two source regions 115 be connected with described channel region.Then, the 3rd mask layer 113 is removed.In the present embodiment, the ion of ion implantation is arsenic ion for the third time, and the energy range of ion implantation is 100Kev ~ 200Kev for the third time, and implantation dosage is 1.0E15/cm
2~ 1.0E16/cm
2.After completing the 3rd ion implantation, carry out second time annealing, the temperature range of described second time annealing is 800 DEG C ~ 1000 DEG C, and the time range of described second time annealing is 30min ~ 80min.
Then, as shown in Figure 9 and Figure 10, on described deep trap 105, source region 115 and grid 112, deposition forms dielectric layer 116, and then etching removes part dielectric layer, exposes the surface of deep trap 105 and the surface of fractional source regions 115.The material of dielectric layer 116 is boron-phosphorosilicate glass.
Then, as is illustrated by figs. 11 and 12, on the surface of described deep trap 105, the surface of fractional source regions 115 and dielectric layer 116 surface deposition form source electrode 117.Then, carry out thinning to described substrate 101 another side, after thinning, form drain electrode 118 at described substrate 101 another side.The material of described source electrode and drain electrode adopts a kind of or wherein several alloy of conventional aluminium, copper, gold, silver.So far, the manufacture of depletion type VDMOS is as shown in figure 12 completed.
Should be understood that, get on the contrary by all Doped ions in above-described embodiment or doping type, can obtain another embodiment, this belongs to ordinary skill in the art means, is not repeating at this.
Embodiment two
As shown in figure 15, the depletion type VDMOS of the embodiment of the present invention two comprises: N-type substrate 101; Be formed at the N-type epitaxy layer 102 in described substrate 101 one side; Be formed at shown at least one potential dividing ring 220, figure on described N-type epitaxy layer 102 neighboring area is the situation of a potential dividing ring; Be formed at the patterned mask 219 in the N-type epitaxy layer 102 of described potential dividing ring 220 both sides; Be formed at the high temperature oxide layer 221 on potential dividing ring 220; Be formed at the multiple P type doping deep traps 105 in the described N-type epitaxy layer 102 between described patterned mask 219; Be formed at the Liang GeNXing implanted channel district 108 of each deep trap 105 both sides; Two channel regions 108 being formed at two adjacent deep traps 105 cover the grid oxic horizon 111 of described two channel regions 108 completely; Be formed at the grid 112 on described grid oxic horizon 111; Be formed in described deep trap 105 and two source regions 115 be connected with described channel region 108; Dielectric layer 116 on the fractional source regions 115 being formed at described grid 112 both sides and on grid, is formed at the source electrode 117 on described deep trap 105, two source regions 112 and dielectric layer 116, and is formed at described substrate 101 another side drain electrode 118.
Below in conjunction with Figure 13 to Figure 15, each step of the manufacture method of the depletion type VDMOS of the embodiment of the present invention two is described in detail.
First, as shown in figure 13, provide a N-type substrate 101, described substrate 101 grows N-type epitaxy layer 102.Form patterned mask 219 on 102 on said epitaxial layer there.Wherein, the material of described mask 219 is silica, and the thickness range of described mask 219 is
Then, for mask, boron ion implantation ion is carried out to described epitaxial loayer 102 with patterned mask 219, in described epitaxial loayer 102, form at least one potential dividing ring 220.
Then, as shown in figure 14, high annealing is carried out to described epitaxial loayer 220, the boron uniform ion in potential dividing ring 220 is distributed, and form high temperature oxide layer 221 on potential dividing ring 220.
Then, identical with each step of the manufacture method of the step with embodiment one that epitaxial loayer 102 are formed other parts of the present embodiment depletion type VDMOS in the epitaxial loayer 102 in patterned mask 219, do not repeating at this.
Through above-mentioned steps, define the structure of the depletion type VDMOS of the embodiment of the present invention two as shown in figure 15.
Figure 16 is the vertical view of the depletion type VDMOS structure of the embodiment of the present invention two.As shown in figure 16, relative to embodiment one, around whole source electrode 117, add at least one potential dividing ring 220, separated by mask 219 between described potential dividing ring 220 and source electrode 117.The situation of the potential dividing ring 220 only illustrated in Figure 16.The potential dividing ring 220 increased effectively can improve the voltage endurance capability of depletion type VDMOS, and the quantity of potential dividing ring is more, and its voltage endurance capability is higher.
Should be understood that, get on the contrary by all Doped ions in above-described embodiment or doping type, can obtain another embodiment, this belongs to ordinary skill in the art means, is not repeating at this.
In sum, in depletion type VDMOS structure in the present invention, ion implantation formation is carried out by the second mask layer in its channel region, and the induction of the grid oxic horizon by doping in nontraditional technology generates channel region.By the channel region using mask layer to carry out ion implantation generation, accurately can be controlled position and the structure of channel region by mask layer, by adjusting the condition of ion implantation accurately to control the parameters such as the channel region degree of depth and doping content.And, the ion implanted regions forming raceway groove in the present invention exists only in channel region, and ion implantation is not existed to grid oxic horizon, therefore the voltage endurance capability of grid oxic horizon can significantly promote, also there is not prior art intermediate ion injects the problems such as the leakage current caused simultaneously, meanwhile, because do not need to carry out ion implantation to grid oxic horizon, the quality of grid oxic horizon have also been obtained guarantee.Structure and the high-quality grid oxic horizon of accurate channel region can both ensure high performance depletion type VDMOS.
It should be noted that, in this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (17)
1. a manufacture method of depletion type VDMOS, is characterized in that, comprising:
The doped substrate of one first doping type is provided;
The one side of described substrate is formed the epitaxial loayer of the first doping type;
Form the first mask layer on said epitaxial layer there;
Carry out first time ion implantation with described first mask layer for mask, in described epitaxial loayer, form the deep trap of at least two the second doping types;
Remove the first mask layer;
Carry out first time annealing;
Described epitaxial loayer and deep trap are formed the second mask layer, and described second mask layer exposes the two side areas of each deep trap; And
With described second mask layer for mask carries out second time ion implantation, form the implanted channel district of two the first doping types in each described second doping type deep trap two side areas.
2. the manufacture method of depletion type VDMOS as claimed in claim 1, it is characterized in that, the length range of described channel region is 1 μm ~ 3 μm.
3. the manufacture method of depletion type VDMOS as claimed in claim 1, it is characterized in that, the distance range between two adjacent described deep traps is 1 μm ~ 4 μm.
4. the manufacture method of depletion type VDMOS as claimed in claim 1, is characterized in that, also comprise after the forming step of described channel region:
Remove the second mask layer;
Oxide layer and polysilicon layer is formed on described each deep trap He on epitaxial loayer;
Etching removes portion of oxide layer and polysilicon layer, forms the grid structure of the channel region of epitaxial loayer and the described epitaxial loayer both sides covered completely between adjacent two deep traps;
Form the 3rd mask layer covered above each deep trap, described 3rd mask layer exposes the subregion of each deep trap both sides;
With described 3rd mask layer for mask, third time ion implantation is carried out to the subregion of described each deep trap both sides, in each deep trap, form two source regions be connected respectively with two channel regions of described deep trap;
On described deep trap, source region and grid structure, deposition forms dielectric layer;
Etching removes part dielectric layer, exposes the deep trap surface between the surface, fractional source regions of each deep trap and two source regions of each deep trap;
The surface, fractional source regions exposed described and deep trap surface and dielectric layer surface formation source electrode;
Carry out thinning to described substrate another side; And
Drain electrode is formed at described substrate another side.
5. the manufacture method of depletion type VDMOS as claimed in claim 4, is characterized in that, after described epitaxial loayer is formed, deep trap also comprises before being formed:
Patterned mask is formed in the neighboring area of described epitaxial loayer;
Inject for mask carries out the 4th secondary ion to described epitaxial loayer with described patterned mask, the neighboring area of described epitaxial loayer is formed at least one potential dividing ring.
6. the manufacture method of depletion type VDMOS as claimed in claim 4, is characterized in that, described third time the energy range of ion implantation be 100Kev ~ 200Kev, implantation dosage is 1.0E15/cm
2~ 1.0E16/cm
2; The energy range of described second time ion implantation is 80Kev ~ 200Kev, and implantation dosage is 1.0E12/cm
2~ 1.0E13/cm
2.
7. the manufacture method of depletion type VDMOS as claimed in claim 1, is characterized in that, described first time the energy range of ion implantation be 40Kev ~ 200Kev, implantation dosage is 1.0E13/cm
2~ 1.0E14/cm
2.
8. the manufacture method of depletion type VDMOS as claimed in claim 1, is characterized in that, the temperature range of described first time annealing is 1100 DEG C ~ 1200 DEG C, and the time range of described first time annealing is 60min ~ 180min.
9. the manufacture method of depletion type VDMOS as claimed in claim 4, is characterized in that, also comprises after completing third time ion implantation step: carry out second time annealing.
10. the manufacture method of depletion type VDMOS as claimed in claim 9, is characterized in that, the temperature range of described second time annealing is 800 DEG C ~ 1000 DEG C, and the time range of described second time annealing is 30min ~ 80min.
The depletion type VDMOS of the manufacture method manufacture of 11. 1 kinds of depletion type VDMOS as claimed in claim 1, is characterized in that, comprising:
The doped substrate of one first doping type;
Be formed at the epitaxial loayer of the first doping type in described substrate one side;
Be formed at the deep trap of at least two the second doping types in described epitaxial loayer; And
Be formed at the implanted channel district of two the first doping types of each described deep trap both sides, wherein, the length range of described channel region is 1 μm ~ 3 μm, and described channel region is separated from each other.
12. depletion type VDMOS as claimed in claim 11, is characterized in that, the distance range between two adjacent described deep traps is 1 μm ~ 4 μm.
13. depletion type VDMOS as claimed in claim 11, it is characterized in that, the injection ion forming described channel region exists only in described channel region.
14. depletion type VDMOS as claimed in claim 11, it is characterized in that, described depletion type VDMOS also comprises:
Be formed in described deep trap and two source regions be connected with described channel region;
Cover the grid structure of the channel region of epitaxial loayer between adjacent two deep traps and described epitaxial loayer both sides completely;
Dielectric layer on the fractional source regions being formed at described grid structure both sides and on grid structure;
Be formed at the source electrode on described deep trap, two source regions and dielectric layer; And
Be formed at the drain electrode of described substrate another side.
15. depletion type VDMOS as claimed in claim 14, it is characterized in that, described depletion type VDMOS also comprises: be formed at least one potential dividing ring on the epitaxial loayer of described source electrode both sides.
16. depletion type VDMOS as claimed in claim 14, is characterized in that, the doping type in described source region is the first doping type, and doping content is higher than the doping content of described channel region.
17. depletion type VDMOS as claimed in claim 14, is characterized in that, the material of described source electrode and drain electrode is a kind of or wherein several alloy of aluminium, copper, gold, silver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210271677.XA CN102760754B (en) | 2012-07-31 | 2012-07-31 | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210271677.XA CN102760754B (en) | 2012-07-31 | 2012-07-31 | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102760754A CN102760754A (en) | 2012-10-31 |
| CN102760754B true CN102760754B (en) | 2015-07-15 |
Family
ID=47055145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210271677.XA Active CN102760754B (en) | 2012-07-31 | 2012-07-31 | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102760754B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022138B (en) * | 2012-12-26 | 2016-07-06 | 杭州士兰微电子股份有限公司 | High-reliability depletion type power semiconductor device and manufacture method thereof |
| CN103094216A (en) * | 2013-01-11 | 2013-05-08 | 无锡华润上华科技有限公司 | Annealing technology of NOR flash memory device and NOR flash memory device |
| CN103208427B (en) * | 2013-03-22 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Depletion-type mos transistor and forming method thereof |
| CN104425274A (en) * | 2013-09-03 | 2015-03-18 | 北大方正集团有限公司 | Preparation method of DMOS (Double diffusion Metal-Oxide-Semiconductor) transistor and DMOS transistor |
| CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
| CN109980010B (en) * | 2017-12-28 | 2020-10-13 | 无锡华润上华科技有限公司 | Method for manufacturing semiconductor device and integrated semiconductor device |
| CN109979801B (en) * | 2017-12-28 | 2021-01-01 | 无锡华润上华科技有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN110648921B (en) * | 2019-10-08 | 2023-01-24 | 北京锐达芯集成电路设计有限责任公司 | N-channel depletion type VDMOS device and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4837606A (en) * | 1984-02-22 | 1989-06-06 | General Electric Company | Vertical MOSFET with reduced bipolar effects |
| US5045902A (en) * | 1989-07-17 | 1991-09-03 | Sgs-Thomson Microelectronics S.A. | VDMOS/logic integrated circuit comprising a vertical depleted MOS transistor and a zener diode and a method of making same |
| US5956582A (en) * | 1993-05-10 | 1999-09-21 | Sgs-Thomson Microelectronics S.A. | Current limiting circuit with continuous metallization |
| CN101969068A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| CN202758891U (en) * | 2012-07-31 | 2013-02-27 | 杭州士兰集成电路有限公司 | Depletion type VDMOS |
-
2012
- 2012-07-31 CN CN201210271677.XA patent/CN102760754B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4837606A (en) * | 1984-02-22 | 1989-06-06 | General Electric Company | Vertical MOSFET with reduced bipolar effects |
| US5045902A (en) * | 1989-07-17 | 1991-09-03 | Sgs-Thomson Microelectronics S.A. | VDMOS/logic integrated circuit comprising a vertical depleted MOS transistor and a zener diode and a method of making same |
| US5956582A (en) * | 1993-05-10 | 1999-09-21 | Sgs-Thomson Microelectronics S.A. | Current limiting circuit with continuous metallization |
| CN101969068A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| CN202758891U (en) * | 2012-07-31 | 2013-02-27 | 杭州士兰集成电路有限公司 | Depletion type VDMOS |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102760754A (en) | 2012-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102760754B (en) | Depletion type VDMOS (Vertical Double-diffusion Metal Oxide Semiconductor) and manufacturing method thereof | |
| JP2010135791A (en) | Semiconductor device and method of manufacturing the same | |
| CN103178093B (en) | The structure of high-voltage junction field-effect transistor and preparation method | |
| CN105070759A (en) | Nldmos device and manufacturing method thereof | |
| CN104716177A (en) | Radio frequency LOMOS device for overcoming electricity leakage and manufacturing method of radio frequency LOMOS device for overcoming electricity leakage | |
| CN106409676A (en) | Semiconductor structure and manufacturing method thereof | |
| CN105679820A (en) | Jfet and manufacturing method thereof | |
| CN103779414B (en) | The manufacturing method of semiconductor device and semiconductor device | |
| CN102931093B (en) | N-channel depletion type power MOSFET device and manufacture method | |
| CN102891180A (en) | Semiconductor device comprising MOSFET device and manufacturing method | |
| CN109830538B (en) | LDMOS device and manufacturing method thereof | |
| CN107785367B (en) | Device integrated with depletion type junction field effect transistor and manufacturing method thereof | |
| CN109273364B (en) | Semiconductor structure and forming method thereof | |
| CN105140289A (en) | N-type LDMOS device and technical method thereof | |
| CN111697080A (en) | Semiconductor unit cell, manufacturing method and semiconductor device | |
| CN104576732A (en) | FinFET parasitic lateral double-diffused semiconductor device | |
| CN105097921A (en) | VDMOS transistor structure and fabricating method thereof | |
| CN102646712A (en) | Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof | |
| CN103022125A (en) | NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method | |
| KR20110078861A (en) | Lateral double diffused metal oxide semiconductor | |
| CN202758891U (en) | Depletion type VDMOS | |
| CN107342224B (en) | Manufacturing method of VDMOS device | |
| CN104201203B (en) | High withstand voltage LDMOS device and manufacture method thereof | |
| CN108365010B (en) | VDMOS device with super junction structure and manufacturing method thereof | |
| CN112635330A (en) | LDMOS device manufacturing method, LDMOS device and terminal equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |