CN102768956A - Method for manufacturing thin line with relatively small edge roughness - Google Patents

Method for manufacturing thin line with relatively small edge roughness Download PDF

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Publication number
CN102768956A
CN102768956A CN2012102280421A CN201210228042A CN102768956A CN 102768956 A CN102768956 A CN 102768956A CN 2012102280421 A CN2012102280421 A CN 2012102280421A CN 201210228042 A CN201210228042 A CN 201210228042A CN 102768956 A CN102768956 A CN 102768956A
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Prior art keywords
side wall
layer
dry etching
substrate
hachure
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黄如
李佳
黎明
张耀凯
许晓燕
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Peking University
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Peking University
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Abstract

The invention provides a method for manufacturing a thin line with relatively small edge roughness, comprising the following steps of depositing a blocking layer and a sacrificial layer on a substrate; coating photoresist on the sacrificial layer, and defining a photoetching graph of the line; transferring the photoetching graph to the sacrificial layer by using a dry etching method; depositing a side wall material layer, and forming a side wall by using the dry etching method; carrying out wet etching on the sacrificial layer in the side wall to form a side wall mask layer; and transferring the line graph to the substrate by using the side wall mask layer and through the dry etching method, so as to obtain the thin line. The method disclosed by the invention is combined with the side wall technology and the wet etching technology; electron-beam lithography, high-temperature oxidation and the like are not used; and the thin line with small edge roughness can be obtained.

Description

A kind of method for preparing the less hachure of edge roughness
Technical field
The invention belongs to very lagre scale integrated circuit (VLSIC) manufacturing technology field, relate to a kind of method for preparing superfine line in the integrated circuit, relate in particular to a kind of method that combines side wall technology and wet etching to prepare the less superfine line of edge roughness.
Background technology
Along with development of integrated circuits, the integrated level of device improves constantly, and requires size of devices constantly to reduce, and preparation small size hachure is more and more crucial.
Though adopt electron beam lithography can prepare hachure, because length consuming time, cost is high, in commercial production, does not possess advantage, and has electron scattering in the electron beam lithography engineering, and the following hachure of preparation 30nm runs into very big challenge.Other preparation method, like common photoetching and oxidation technology, though can prepare hachure, hachure has bigger LER (edge roughness), adds oxidation and will carry out high temperature process, and the time is longer, and cost is higher, has limited its development in commercial production.
The side wall technology is to utilize established side wall as hard mask, and etch silicon forms hachure downwards.Side wall technical matters step is simple, makes the weak point in man-hour, and not high to equipment requirements, implementation is strong.Through appropriate design, can utilize the side wall technology to prepare the following hachure of 20nm.
Summary of the invention
The present invention proposes the method that a kind of combination side wall technology and wet etching prepare the less superfine nano lines of edge roughness (LER); Avoid the use of technologies such as electron beam lithography, high-temperature oxydation; Can obtain the hachure of size below 20nm, simultaneously, the LER of lines can improve.
For achieving the above object, the present invention adopts following technical scheme:
A kind of method for preparing the less hachure of edge roughness may further comprise the steps:
1) barrier layer and sacrifice layer on substrate;
2) resist coating on said sacrifice layer, and the litho pattern of definition lines;
3) adopt dry etching method that said litho pattern is transferred to said sacrifice layer;
4) deposit spacer material layer, and adopt dry etching method to form side wall;
5) sacrifice layer in the wet etching side wall forms the side wall mask layer;
6) utilize said side wall mask layer, bargraphs is transferred on the substrate, obtain hachure through dry etching.
Further, said substrate is a silicon substrate.
Further, said barrier layer is a silica, and said sacrifice layer is a polysilicon.
Further, adopt ordinary optical photoetching method definition bargraphs.
Further, said spacer material layer is a silicon nitride.
Further, adopt low-pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method to carry out said deposit.
Further, said dry etching is an anisotropic dry etch.
Further, adopt TMAH (Tetramethyl Ammonium Hydroxide, TMAH) solution to carry out said wet etching; The TMAH solution concentration is preferably 25wt%, and corrosion temperature is preferably 60 ℃.
Advantage of the present invention and good effect are following:
1) little as the silicon hachure roughness that mask etching goes out by the silicon nitride side wall, pattern is good.The dry etching side of polysilicon is steep than silica, silicon nitride, and the side wall smoothness that is formed by it is improved, and adds the wet etching polysilicon and more can thoroughly remove polysilicon than dry etching, can be not coarse at the residual lines that cause of side wall.
2) utilize the side wall technology can preparation size less than the lines of 20nm, satisfy the requirement of small size device critical process.
3) adopt TMAH solution wet etching polysilicon, easy and simple to handle, safety; And can not introduce metal ion, be applicable in the integrated circuit fabrication process.
4) technological process weak point consuming time is workable, is suitable for commercial production.
Description of drawings
Fig. 1 is the process chart of the method for the less hachure of the preparation edge roughness of the embodiment of the invention.
Fig. 2 is each material layer structures sketch map in the preparation hachure process of the embodiment of the invention.Wherein: 1 backing material; 2-silica; 3-polysilicon; 4-photoresist; 5-silicon nitride; 6-backing material anchor line (string) bar.
Embodiment
Pass through specific embodiment below, and conjunction with figs., the present invention is done detailed explanation.
Fig. 1 is the flow chart of steps of the method for the less hachure of the preparation edge roughness of present embodiment.This flow process can further be summarised as following three big steps:
1) barrier layer and sacrifice layer on substrate, and the litho pattern of definition lines.
Barrier material is a silica, and effect is the barrier layer of when subsequent etching sacrifice layer and corrosion sacrifice layer, making substrate.Sacrificial layer material is a polysilicon, as the supporting layer of subsequent deposition side wall.Concrete processing step comprises:
A) deposit one deck silica barrier layer stops subsequent etching and corrosion;
B) deposit one deck polysilicon membrane;
C) on polysilicon, be coated with the last layer photoresist, lithographic definition goes out hachure;
D) dry etching with figure transfer to polysilicon membrane.
2) wet etching forms side wall
Purpose is to prepare the used side wall of subsequent etching substrate silicon.Side wall is as the mask layer of etch silicon substrate, and its width has directly determined the size of the silicon lines that etching is come out.Concrete processing step is following:
E) the certain thickness silicon nitride of deposit one deck;
F) dry etching silicon nitride forms side wall;
G) wet etching sacrifice polysilicon layer forms silicon nitride side wall mask layer.
3) dry etching backing material forms hachure
The main dry etching that passes through utilizes the silicon nitride side wall to make mask layer, and lines are transferred to silicon substrate material, finally prepares the less hachure of LER.Concrete processing step is following:
H) dry etching silica barrier layer;
I) dry etching silicon substrate.
In the said method, silicon oxide deposition, polysilicon, silicon nitride adopt low-pressure chemical vapor deposition method, can also strengthen chemical vapour deposition (CVD) (PECVD) by using plasma, but the quality of deposited film are good not as low-pressure chemical vapor deposition.What the definition photoresist adopted is that the ordinary optical photoetching gets final product, and also can adopt more advanced optical lithography techniques.What etching oxidation silicon, polysilicon, silicon nitride and backing material adopted is the anisotropic dry etch technology.The wet etching polysilicon adopts TMAH solution, and the TMAH solution concentration is preferably 25wt%, and corrosion temperature is preferably 60 ℃; Can adopt potassium hydroxide (KOH) solution etc. in addition, but KOH is toxic, so in commercial production, use few.
The hachure of present embodiment preparation, little edge roughness is realized through adopting sacrifice polysilicon layer and wet etching polysilicon.The dry etching side of polysilicon is steep than silica, silicon nitride, and the side pattern is better, and follow-up silicon nitride side wall through the formation of deposit etching is also more steep.TMAH solution wet etching is adopted in the removal of sacrifice polysilicon layer, and TMAH is higher to the corrosion rate of silicon materials, and speed can be through regulating the concentration and the adjustment of etchant solution, and it all has higher selection ratio to silica and silicon nitride.Than dry etching, the reaction of wet etching sacrifice polysilicon layer is more thorough, removes cleaner.Like this, the LER of side wall is less, and the silicon lines LER after the etching is also less.The control of line size then is to realize through forming the less side wall size of size.Higher sacrificial layer thickness and thin silicon nitride thickness can form the less side wall size of size, through dry etching, can the side wall mask graph be transferred to the substrate silicon material, finally prepare the following superfine line of 20nm.
The instantiation of using the method for preparing hachure is provided below, but the invention is not restricted to wherein mentioned technological parameter.Fig. 2 is the sketch map of each material layer in the preparation process, specifies as follows in conjunction with this figure:
Embodiment 1:
1, chemical vapor deposition one deck silicon oxide film on the body silicon substrate of (100)/< 110 >, thickness are that
Figure BDA00001842683300031
is shown in Fig. 2 (a).
2, chemical vapor deposition one deck polysilicon membrane on silicon oxide film, thickness are that
Figure BDA00001842683300041
is shown in Fig. 2 (b);
3, resist coating on polysilicon membrane is shown in Fig. 2 (c);
4, go out will be as the zone of sacrifice layer, shown in Fig. 2 (d) for lithographic definition;
5, anisotropic dry etch polysilicon membrane, the figure transfer on the photoresist is to polycrystalline silicon film material, shown in Fig. 2 (e) the most at last;
6, remove photoresist, shown in Fig. 2 (f);
7, chemical vapor deposition silicon nitride on the surface of silicon oxide film and polysilicon membrane, thickness are that is shown in Fig. 2 (g);
8, anisotropic dry etch silicon nitride forms the silicon nitride side wall, shown in Fig. 2 (h);
9, at 25wt%, wet etching polysilicon in 60 ℃ the TMAH solution, sacrifice layer is corroded, and forms silicon nitride hard mask, shown in Fig. 2 (i);
10, anisotropic dry etch silica is shown in Fig. 2 (j);
11, anisotropic dry etch silicon substrate
Figure BDA00001842683300043
forms the silicon hachure, shown in Fig. 2 (k);
12, the SPA corroding silicon nitride of heat (170 ℃) is shown in Fig. 2 (1);
13, hydrofluoric acid: water (volume ratio 1:10) wet etching silica is to full sheet dehydration, shown in Fig. 2 (m).
Embodiment 2:
This example provides the technological parameter of the littler hachure of preparation size.Prepare the littler hachure of size, can the sacrifice polysilicon layer thickness be increased.When etch silicon nitride formed side wall, because laterally undercutting makes that more seriously the silicon nitride hard mask size is littler, finally prepd hachure size was also littler, can reach below the 10nm like this.Concrete steps are following:
1, chemical vapor deposition one deck silicon oxide film on the body silicon substrate of (100)/< 110 >, thickness are that
Figure BDA00001842683300044
is shown in Fig. 2 (a).
2, chemical vapor deposition one deck polysilicon membrane on silicon oxide film, thickness are that
Figure BDA00001842683300045
is shown in Fig. 2 (b);
3, resist coating on polysilicon membrane is shown in Fig. 2 (c);
4, go out will be as the zone of sacrifice layer, shown in Fig. 2 (d) for lithographic definition;
5, anisotropic dry etch polysilicon membrane, the figure transfer on the photoresist is to polycrystalline silicon film material, shown in Fig. 2 (e) the most at last;
6, remove photoresist, shown in Fig. 2 (f);
7, chemical vapor deposition silicon nitride on the surface of silicon oxide film and polysilicon membrane, thickness are that
Figure BDA00001842683300046
is shown in Fig. 2 (g);
8, anisotropic dry etch silicon nitride forms the silicon nitride side wall, shown in Fig. 2 (h);
9, at 25wt%, wet etching polysilicon in 60 ℃ the TMAH solution, sacrifice layer is corroded, and forms silicon nitride hard mask, shown in Fig. 2 (i);
10, anisotropic dry etch silica is shown in Fig. 2 (j);
11, anisotropic dry etch silicon substrate
Figure BDA00001842683300051
forms the silicon hachure, shown in Fig. 2 (k);
12, the SPA corroding silicon nitride of heat (170 ℃) is shown in Fig. 2 (1);
13, hydrofluoric acid: water (1:10) wet etching silica is to full sheet dehydration, shown in Fig. 2 (m).So far, can obtain the less hachure of LER.
Above embodiment is only in order to technical scheme of the present invention to be described but not limit it; Those of ordinary skill in the art can make amendment or is equal to replacement technical scheme of the present invention; And not breaking away from the spirit and scope of the present invention, protection scope of the present invention should be as the criterion so that claim is said.

Claims (10)

1. method for preparing the less hachure of edge roughness, its step comprises:
1) barrier layer and sacrifice layer on substrate;
2) resist coating on said sacrifice layer, and the litho pattern of definition lines;
3) adopt dry etching method that said litho pattern is transferred to said sacrifice layer;
4) deposit spacer material layer, and adopt dry etching method to form side wall;
5) sacrifice layer in the wet etching side wall forms the side wall mask layer;
6) utilize said side wall mask layer, bargraphs is transferred on the substrate, obtain hachure through dry etching.
2. the method for claim 1 is characterized in that, said substrate is a silicon substrate.
3. the method for claim 1 is characterized in that, said barrier layer is a silica, and said sacrifice layer is a polysilicon.
4. the method for claim 1 is characterized in that, adopts ordinary optical photoetching method definition bargraphs.
5. the method for claim 1 is characterized in that, said spacer material layer is a silicon nitride.
6. the method for claim 1 is characterized in that, adopts low-pressure chemical vapor deposition method to carry out said deposit.
7. the method for claim 1 is characterized in that, using plasma strengthens chemical gaseous phase depositing process and carries out said deposit.
8. the method for claim 1 is characterized in that, said dry etching is an anisotropic dry etch.
9. the method for claim 1 is characterized in that, adopts TMAH solution to carry out said wet etching.
10. method as claimed in claim 9 is characterized in that, the concentration of said TMAH solution is 25wt%, and corrosion temperature is 60 ℃.
CN2012102280421A 2012-07-02 2012-07-02 Method for manufacturing thin line with relatively small edge roughness Pending CN102768956A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261559A (en) * 2014-07-14 2016-01-20 超科技公司 Method for laser processing of photoresist agent in gaseous environment
CN108807170A (en) * 2018-06-11 2018-11-13 中国科学院微电子研究所 A kind of production method of nano wire
CN110890376A (en) * 2018-09-11 2020-03-17 长鑫存储技术有限公司 Method for manufacturing semiconductor device

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CN101427355A (en) * 2006-04-21 2009-05-06 国际商业机器公司 Patterning sub-lithographic features with variable widths
CN101554991A (en) * 2009-05-11 2009-10-14 北京大学 Processing method of diverse nano structure
CN101920932A (en) * 2009-06-10 2010-12-22 中国科学院半导体研究所 Method for manufacturing nano-size-spacing electrode

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Publication number Priority date Publication date Assignee Title
US20070215960A1 (en) * 2004-03-19 2007-09-20 The Regents Of The University Of California Methods for Fabrication of Positional and Compositionally Controlled Nanostructures on Substrate
CN101044595A (en) * 2004-09-01 2007-09-26 微米技术有限公司 Mask material conversion
CN101044596A (en) * 2004-09-02 2007-09-26 微米技术有限公司 Method for integrated circuit fabrication using pitch multiplication
CN101427355A (en) * 2006-04-21 2009-05-06 国际商业机器公司 Patterning sub-lithographic features with variable widths
CN101364537A (en) * 2007-08-09 2009-02-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method for grid and semiconductor device, construction for manufacturing grid
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261559A (en) * 2014-07-14 2016-01-20 超科技公司 Method for laser processing of photoresist agent in gaseous environment
CN108807170A (en) * 2018-06-11 2018-11-13 中国科学院微电子研究所 A kind of production method of nano wire
CN108807170B (en) * 2018-06-11 2021-10-22 中国科学院微电子研究所 Method for manufacturing nano wire
CN110890376A (en) * 2018-09-11 2020-03-17 长鑫存储技术有限公司 Method for manufacturing semiconductor device
CN110890376B (en) * 2018-09-11 2022-08-02 长鑫存储技术有限公司 Method for manufacturing semiconductor device

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Application publication date: 20121107