CN102778645A - JTAG (joint test action group) main controller and realization method of JTAG main controller - Google Patents
JTAG (joint test action group) main controller and realization method of JTAG main controller Download PDFInfo
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Abstract
The invention relates to a JTAG (joint test action group) main controller and a realization method of the JTAG main controller. The JTAG main controller comprises a JTAG signal generator. The JTAG signal generator obtains external HOST instructions, in addition, the HOST instructions are analyzed to obtain IR (instruction register) instructions or DR (data register) data, so corresponding JTAG interface signals are generated according to IR instructions or DR data, and a target chip is driven through the JTAG interface signals. The JTAG main controller and the realization method have high execution instruction efficiency, and can be applied into a JTAG device.
Description
Technical field
The present invention relates to electronic applications, relate in particular to the JTAG device.
Background technology
Jtag interface is as a kind of interface standard of IEEE, bringing into play important effect at aspects such as the test of integrated circuit, emulation, debugging.Existing most high-grade device is all supported the JTAG agreement, like devices such as DSP, FPGA.
The jtag interface of standard comprises test clock input signal TCK, input signal of test data TDI, test mode select signal TMS, test data output port TDO and an optional test reset input signal TRST.
JTAG device inside logic realizes through a TAP state machine, and Fig. 1 shows the state transitions synoptic diagram of TAP state machine of the JTAG device of IEEE1149.1 standard code.As shown in Figure 1, the TAP state machine comprises two branches, is respectively that command register inserts (IR Access) branch and data register inserts (DR Access) branch.And the state transitions of this TAP state machine is controlled by the test mode select signal in the JTAG device (TMS).
The IEEE1149.1 standard code command register (IR) and the data register (DR) of JTAG device; According to this regulation; When the state of TAP state machine is in the IR access tributary; Order moves on in the IR register under " displacement IR " state through the TDI port by turn, and the IR register is used for selecting when the TAP state machine is in the DR access tributary, being connected between TDI and the TDO by the selected DR register of IR register; And under " displacement DR " state, data are got into by in the selected register of IR register through the TDI displacement.
When Fig. 2 and Fig. 3 show the command register that inserts JTAG and data register respectively, the sequential chart of jtag interface signal.Fig. 2 accomplishes the 4-bit command register through jtag interface in the prior art to insert the JTAG signal timing diagram that produces.Fig. 3 accomplishes the 8-bit data register through jtag interface in the prior art to insert the JTAG signal timing diagram that produces.
Traditional JTAG primary controller all is to utilize processors such as MIPS, ARM to realize; Because the function that MIPS, ARM system carry out is realized by software; And what adopt is that specific function is accomplished in the instruction of MIPS, ARM self; A jtag instruction need use a plurality of MIPS instruction simulations, and owing to the completion of task in MIPS, the ARM system is accomplished through scheduling, therefore causes the JTAG signal that it produced (being signals such as TCK, TMS, TDI) irregular; And the delay between two instructions is bigger, and this is for the test of chip and unfavorable.Especially when the jtag interface control circuit is carried out performance test, can't produce the test clock of high frequency, influence test effect through MIPS, arm processor.The problems referred to above all are to be determined by system's own characteristics such as MIPS, ARM.
Summary of the invention
The invention provides a kind of JTAG master controller and its implementation that can overcome the above problems.
In first aspect, the invention provides a kind of JTAG master controller that is connected with objective chip.This JTAG master controller comprises the JTAG signal generator.This JTAG signal generator is used to obtain outside HOST instruction; And to this HOST instruction is resolved to obtain IR instruction or DR data; Thereby produce corresponding jtag interface signal according to this IR instruction or DR data, to drive this objective chip through this jtag interface signal.
In second aspect, the invention provides a kind of implementation method of JTAG master controller.This method is at first obtained the HOST instruction, then this HOST instruction is resolved, to obtain IR instruction or DR data.Produce corresponding jtag interface signal according to this IR instruction and/or DR data again.Objective chip is tested or emulation or debugging through said jtag interface signal at last.
JTAG master controller of the present invention no longer adopts processors such as MIPS, ARM, but realizes through the hardware architecture mode.The JTAG master controller of this kind structure; Its inside function is accomplished through hardware mode; Therefore it can make the signal period of being sent isometric, continuous, and delay is little between the different instruction, thereby can accomplish accurate test, emulation or the debugging to objective chip.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is explained in more detail, in the accompanying drawings:
Fig. 1 is the state transitions synoptic diagram of TAP state machine of the JTAG device of IEEE 1149.1 standard codes;
Fig. 2 accomplishes the 4-bit command register through jtag interface in the prior art to insert the jtag interface sequential chart that produces;
Fig. 3 accomplishes the 8-bit data register through jtag interface in the prior art to insert the JTAG signal timing diagram that produces;
Fig. 4 is the JTAG master controller principle of work synoptic diagram of one embodiment of the invention;
Fig. 5 is the JTAG signal generator inner structure synoptic diagram of one embodiment of the invention;
Fig. 6 is the state machine diagram of the HOST instruction parser of one embodiment of the invention.
Embodiment
Fig. 4 is the JTAG master controller principle of work synoptic diagram of one embodiment of the invention.
This JTAG master controller comprises outside NVM410, memory control module 420, clock module 430, embedded memory 440, JTAG signal generator 450; Wherein, memory control module 420, clock module 430, embedded memory 440, JTAG signal generator 450 are integrated on the chip, like FPGA or asic chip.
When this JTAG master controller work, it need link to each other with objective chip 460 through JTAG signal generator 450, to realize test or the operations such as debugging or emulation to objective chip 460.This objective chip 460 comprises the jtag interface of standard, and it meets the IEEE1149.1 standard.
Among Fig. 4, outside NVM 410 is used to store from the HOST instruction of main frame 470.This outside NVM 410 can be any one existing nonvolatile memory, is EEPROM (EEPROM) like it.
This memory control module 420 be used for the HOST instruction storage that sends over from main frame 470 to this outside NVM 410, and be used for the HOST of outside NVM 410 instruction is transported in the embedded memory 440.
This embedded memory 440 is used for temporary HOST instruction from main frame 470 or outside NVM 410.
Need to prove; When this JTAG master controller is used for the first time; This JTAG master controller need link to each other with main frame 470 through its memory control module 420, so that this JTAG master controller will be from the HOST instruction storage in the external host 470 to the NVM410 of this outside through this memory control module 420.Because this outside NVM 410 is nonvolatile memories; The HOST instruction of its storage inside is difficult for losing; Therefore when this JTAG master controller is used once more; Need not to be connected on this main frame 470, this JTAG master controller can directly be tested or debugging or emulation etc. objective chip.
This clock module 430 links to each other with memory control module 420, JTAG signal generator 450, and it is used to produce circuit and moves needed clock, and this clock module 430 provides tck signal to the TCK of this JTAG master controller interface.
In the example, this clock module 430 is that the PLL module by PLD realizes, promptly comes clocking by the PLL module of PLD.Because this PLL module can produce high frequency clock signal, so the present invention can produce the test clock of high frequency.And systems such as the MIPS that prior art adopted, ARM are because its build-in attribute can't produce the high-frequency test clock.
This JTAG signal generator 450 is used for reading the HOST instruction of embedded memory 440; And to this HOST instruction is resolved; To obtain corresponding IR instruction length, DR data length, IR instruction, DR data; And produce corresponding jtag interface signal, thereby realize test or debugging or emulation etc. to objective chip 460 according to this jtag interface signal according to this IR instruction length, DR data length, IR instruction, DR data and through TAP state machine (the TAP state machine among Fig. 1).Wherein, The HOST instruction is the custom instruction of present embodiment; Its definition rule will be able to detail in following content, and IR instruction, DR data then are to be defined according to the IEEE1149.1 prescribed by standard by the objective chip deviser, so objective chip 460 can be discerned this IR instruction and DR data.
To partly set forth the principle of work of JTAG signal generator 450 through Fig. 5 and respective description thereof below.
Fig. 5 is the JTAG signal generator inner structure synoptic diagram of one embodiment of the invention.This JTAG signal generator comprises that storer reads controller 510, HOST instruction parser 520, IR instruction length register 530, DR data length register 540, IR order register 550, DR data register 560, jtag interface logic 570.
Among Fig. 5, HOST instruction parser 520 is used to resolve the HOST instruction from embedded memory 440.This HOST order format is: Header+Data; Wherein, obtain the HOST instruction of IR instruction after Header representes to resolve, obtain the HOST instruction of DR data after Data representes to resolve.This shows that 450 pairs of HOST instructions of JTAG signal generator are resolved, and can obtain the IR instruction earlier and obtain the DR data again.
In the example, Header length is 32 bits, will be that 32 bits are that example is set forth with Header length below.
Table 1 is that length is the form of the Header of 32 bits.
Table 1
Table 1 is to satisfy under 000,001,010,011 situation implication that Header [28:0] is referred to respectively respectively at Header [31:29].With way of example above-mentioned table 1 is done further elaboration at present.When the instruction that receives when HOST instruction parser 520 was Header=32 ' h0000_0010, it write IR instruction length register with Header [28:0] corresponding contents, and the value of writing is 16.When the instruction that receives when HOST instruction parser 520 is Header=32 ' h2000_00FF; It writes DR data length register with Header [28:0] corresponding contents; And the value of writing is 255, and calculates the line number (below have do elaboration to how obtaining this line number) of DR data according to this DR data length value.When the instruction that receives when HOST instruction parser 520 was Header=32 ' h4000_3FAF, it write the IR register with Header [28:0] corresponding contents, and the value of writing is 29 ' h0000_3FAF.When instruction Header=32 ' h6000_0000 that HOST instruction parser 520 receives, HOST instruction parser and storer read controller and quit work.
These HOST instruction parser 520 inside comprise a counter, and this counter is used to count the line number that the DR data read.
This HOST instruction parser 520 also relates to a state machine, and referring to Fig. 6, Fig. 6 is the state machine diagram of the HOST instruction parser of one embodiment of the invention.
Among Fig. 6, during system reset, state machine is in Header state (command status); Under the Header state; When Header [31:29]==3 ' b010 (the expression present instruction is for sending the IR instruction); And when parsing non-0 value of DR data length; State machine is transferred to the Data state, and the value of the counter in the HOST instruction parser 520 is set to DR number of data lines+1, so that go counting to parsing the DR data; Under Data state (data mode), the counter of HOST instruction parser 520 begins to subtract counting, promptly whenever reads data in the line storage, and this Counter Value subtracts 1, reduces to till 0 up to this Counter Value, and this moment, this state machine was transferred to the Header state again.
The method that the HOST instruction parser obtains the DR number of data lines is: when instruction Header satisfied 3 ' b010, divided by 32, the numerical value that then obtains was the total line number of DR data with Header [29:0].Therefore, counter need begin counting from Header [29:5]+1, is read line number with record DR data.
Table 2 is examples of memory contents form in outside NVM 410 and the embedded memory 440.
Table 2
Be example with table 2 below, set forth the principle of work of HOST instruction parser in detail.
Instruction 32 ' the h0000_0010 of this HOST instruction parser 520 from table 2 begins to resolve, and can know according to table 1, and this instruction 32 ' h0000_0010 can be parsed " the IR instruction length is 16 ".
Instruction 32 ' h2000_00FF that this HOST instruction parser 520 continues in the resolution table 2; This instruction 32 ' h2000_00FF can be parsed " the DR data length is 255 "; Because every capable DR data are 32 bits; Therefore can further parse totally 8 row DR data, thereby the initial value of counter is 8+1=9.Because the jump condition of the Header state of above-mentioned instruction 32 ' h0000_0010 and the equal unmet Fig. 6 state machine of 32 ' h2000_00FF, i.e. equal unmet Header [32:29]==3 ' b010, and DR length is non-0, therefore, still is in the Header state this moment.
Instruction 32 ' h4000_3FAF that this HOST instruction parser 520 continues in the resolution table 2, this instruction 32 ' h4000_3FAF can be parsed " sending IR instruction 3FAF ".Because this instruction 32 ' h4000_3FAF satisfies Header [32:29]==3 ' b010, and DR data length non-0.Therefore, this moment from the Header state transitions to the Data state.
Instruction 32 ' h1234_5678 that this HOST instruction parser 520 continues in the resolution table 2 owing to transferred to the Data state this moment, therefore sends data 1234_5678...... this moment; By that analogy, be 0 up to the value of counter, sent 8 capable DR data this moment.
Need to prove that (instruction 32 ' h4000_3FAF) that promptly is stored in outside NVM 410 and the embedded memory 440 only is an example to this instruction 32 ' h4000_3FAF, that is to say, sending IR instruction 3FAF only is an example.In fact, specifically send which type of IR instruction and need set, and the IR that is sent instruction there are many usually, and be not limited to 32 ' h4000_3FAF instruction in the table 2 according to the configuration of objective chip.Equally, instruction 32 ' h1234_5678 also only is an example, specifically send which type of DR data, and to send how many bar DR data also is to set according to the configuration of objective chip.
Above-mentioned table 2 and respective description partly are the elaborations that the principle of work of HOST instruction parser 520 is carried out, and the storer among continuation description Fig. 5 reads the principle of work of controller 510 and jtag interface logic 570 below.
This storer reads controller 510 after receiving test beginning indicator signal (this signal can produce through button), reads the row of first in the embedded memory 440 content, and is sent to HOST instruction parser 520.This HOST instruction parser 520 is resolved and should be instructed, and concrete analytic method is referring to table 2, Fig. 6 and respective description part thereof, and after having resolved this instruction, these HOST instruction parser 520 these storeies of indication read controller 510 and read the next line data.And the like; Read controller 510 up to this storer and read instruction Header==32 ' h6000_0000; And after 520 pairs of this HOST instruction parsers should instruct and resolve, this HOST instruction parser 520 and this storer read controller 510 and quit work.
(this HOST instruction parser 520 is after sending to IR order register or DR data register with the information that parses after the register effective index signal that detects these HOST instruction parser 520 transmissions for this jtag interface logic 570; A register effective index signal is sent to this jtag interface logic in the capital); Obtain value or the value in the DR data length register or value in the IR order register or the value in the DR data register in the IR instruction length register; And according to the value of this acquisition; According to the TAP state machine among Fig. 1 and Fig. 2, jtag interface sequential chart shown in Figure 3, drive the jtag interface of objective chip.
Particularly, the value of IR order register is at Fig. 1 state machine under " displacement IR " state to be exported from the TDI interface, and the transfer of each state of IR is decided by the value in the IR instruction length register; The value of DR data register is at Fig. 1 state machine under " displacement DR " state to be exported from the TDI interface, and the transfer of each state of DR is decided by the value in the DR data length register.And the TCK interface among Fig. 5 is exported the clock signal from clock module 430, and the output of TMS interface then comes from the control signal that Fig. 1 state machine shifts.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited described claims.
Claims (17)
1. a JTAG master controller that is connected with objective chip is characterized in that, comprising:
The JTAG signal generator; Obtain outside HOST instruction; And to this HOST instruction is resolved obtaining IR instruction or DR data, thereby produce corresponding jtag interface signal according to this IR instruction or DR data, to drive this objective chip through this jtag interface signal.
2. a kind of JTAG master controller as claimed in claim 1 is characterized in that, comprises the embedded memory that links to each other with the JTAG signal generator, temporary said HOST instruction.
3. a kind of JTAG master controller as claimed in claim 1 is characterized in that, comprises memory control module and external memory storage, is used for the HOST instruction from main frame is sent to this external memory storage and reads the HOST instruction from this external memory storage.
4. a kind of JTAG master controller as claimed in claim 1 is characterized in that this JTAG master controller also comprises clock module, and this clock module is used for providing the tck signal of jtag interface signal.
5. a kind of JTAG master controller as claimed in claim 1 is characterized in that said JTAG signal generator comprises the HOST instruction parser, and this HOST instruction parser is used to resolve the HOST instruction from said embedded memory.
6. a kind of JTAG master controller as claimed in claim 1 is characterized in that, the part definition IR instruction length of said HOST instruction, the DR data length with send one or more in the IR instruction.
7. a kind of JTAG master controller as claimed in claim 6 is characterized in that, another part of said HOST instruction is represented the IR instruction length, the DR data length with send one or more in the IR instruction.
8. a kind of JTAG master controller as claimed in claim 5 is characterized in that said HOST instruction parser also comprises a state machine, and this state machine comprises command status (Header) and data mode (Data state);
During system reset, this state machine is in command status (Header state); Satisfying the instruction parse for sending the IR instruction, and during non-0 condition of DR data length, this state machine is transferred to data mode (Data state) by command status (Header state).
9. a kind of JTAG master controller as claimed in claim 8 is characterized in that said HOST instruction parser also comprises a counter, and this counter is used for the DR number of data lines is counted;
When said state machine is in data mode (Data state); The initial value of this counter is set; And said HOST instruction parser whenever parses the DR of delegation data; This Counter Value increasing or decreasing shows that up to this Counter Value the DR data parsing finishes, and this state machine is transferred to command status (Header state) by data mode (Data state).
10. a kind of JTAG master controller as claimed in claim 5 is characterized in that said JTAG signal generator comprises that also storer reads controller; This storer reads the HOST instruction that controller is used for reading said embedded memory, and after said HOST instruction parser is made indication to it, this storer reads controller will read next the bar HOST instruction in the said embedded memory again.
11. a kind of JTAG master controller as claimed in claim 5 is characterized in that, said JTAG signal generator also comprises IR instruction length register, IR order register, DR data register, DR data length register;
This IR instruction length register is used to store by said HOST instruction parser resolves the IR instruction length value that obtains; This IR order register is used to store by said HOST instruction parser resolves the IR instruction that obtains; This DR data register is used to store by said HOST instruction parser resolves the DR data that obtain; This DR data length register is used to store by said HOST instruction parser resolves the DR data length value that obtains.
12. a kind of JTAG master controller as claimed in claim 11 is characterized in that said JTAG signal generator also comprises the jtag interface logic; This jtag interface logic is used for obtaining the value of said IR instruction length register, the value in the IR order register; And obtain the value in the said DR data length register, the value in the DR data register; And according to this value that gets access to, and drive objective chip through the TAP state machine.
13. the implementation method of a JTAG master controller is characterized in that, comprising:
Obtain the HOST instruction;
This HOST instruction is resolved, to obtain IR instruction or DR data;
Produce corresponding jtag interface signal according to this IR instruction and/or DR data.
Objective chip is tested or emulation or debugging through said jtag interface signal.
14. the implementation method of a kind of JTAG master controller as claimed in claim 13 is characterized in that, the part definition IR instruction length of said HOST instruction, the DR data length with send one or more in the IR instruction; The corresponding expression of another part IR instruction length of said HOST instruction, the DR data length with send IR one or more in instructing.
15. the implementation method of a kind of JTAG master controller as claimed in claim 14 is characterized in that, another part of said HOST instruction is represented the IR instruction length, the DR data length with send one or more in the IR instruction.
16. the implementation method of a kind of JTAG master controller as claimed in claim 13 is characterized in that, this JTAG master controller also comprises the state machine that a command status (Header state) and data mode (Data state) shift each other;
Instruction is resolved to this HOST, is included in to resolve when this state machine is in command status with the step that obtains IR instruction and/or DR data to obtain the IR instruction; Satisfying the instruction parse for sending the IR instruction, and during non-0 condition of DR data length, this state machine is transferred to data mode by command status; Under data mode, resolve and obtain the DR data.
17. the implementation method of a kind of JTAG master controller as claimed in claim 16 is characterized in that, this JTAG master controller comprises counter; This HOST instruction is resolved; Step to obtain IR instruction and/or DR data comprises that this JTAG master controller whenever parses the DR of delegation data, this Counter Value increasing or decreasing; Finish when this Counter Value shows the DR data parsing, this state machine is transferred to command status by data mode.
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| CN104502645A (en) * | 2015-01-26 | 2015-04-08 | 浪潮(北京)电子信息产业有限公司 | JTAG signal generation method and generator |
| CN108107351A (en) * | 2017-12-06 | 2018-06-01 | 西安智多晶微电子有限公司 | Adjustment method, debugger and the system of JTAG debuggers |
| CN112596434A (en) * | 2020-12-07 | 2021-04-02 | 天津津航计算技术研究所 | CPLD pin logic state monitoring method |
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